Analyze and improve constant support Verilog Parser

[thunder-hammer]

It would be useful to make sure the handling of constant assignments and port mappings makes sense, and compare with what we are doing with the EDIF parser/composer.

some example syntax

assign my_cable = 1'b0

and

module_name instance_name(.i(1'b0));

This may also be valid in a concatenation construct or top level ports. not sure about that though. Don't think i've seen it yet.