Handling Intel architecture definitions

[agg23]

As far as I am aware, the only way to get a netlist out of modern Quartus is using the EDA Netlist Writer feature, which outputs a Verilog post-synthesis netlist, designed for simulation with timing. The IP components provided (say with ModelSim/Questa) are not optimized like a netlist is, and as such, it is not customized to the particular design you are implementing.

In particular, the simulator definitions use parameters and dynamically sized ports for various base IPs (say RAMs), which SpyDrNet doesn't support because that's not a typical netlist construct. However, unless we find another way to get netlists out of Quartus, or preprocess more of the corresponding Verilog, we'll never get the correct sizes for those ports.

// Example port
input [port_a_data_width - 1:0] portadatain;

That begs the question of how this should be handled. For my current usecase, it doesn't matter, because I don't care about the net size (though it may cause problems if wires are concatenated, I'm not sure), and I can just comment out the numeric check for the port size specification. This obviously doesn't work elsewhere though.

Since we can’t distribute the Intel file anyway due to licensing, I wonder if building a minimal module list with properly sized input/outputs (like your existing architecture IPs), and just using some large default port size (say 128) for each parameterized net size would work

[jacobdbrown4]

@agg23 Can you create a small, barebones module to illustrate this problem to help me understand better?

If I understand correctly, the alternate solution you proposed would be to make the port size large (like 128) when a parameterized port size like this is encountered. Am I correct?