diff --git a/COMPILE.TXT b/COMPILE.TXT index 5d914ffc69..8674c8dfd3 100644 --- a/COMPILE.TXT +++ b/COMPILE.TXT @@ -17,7 +17,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install. (0) Tailor Capstone to your need. - Out of all archtitectures supported by Capstone, if you just need several + Out of all architectures supported by Capstone, if you just need several selected archs, choose the ones you want to compile in by editing "config.mk" before going to next steps. diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT index 6b0d4e14bc..77d16c558b 100644 --- a/COMPILE_MSVC.TXT +++ b/COMPILE_MSVC.TXT @@ -19,7 +19,7 @@ or newer versions are required. (0) Tailor Capstone to your need. - Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, + Out of 9 architectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln", then directly editing the projects "capstone_static" & "capstone_dll" for static diff --git a/ChangeLog b/ChangeLog index b06d27e0c5..fb4c214bdc 100644 --- a/ChangeLog +++ b/ChangeLog @@ -424,7 +424,7 @@ Version 3.0.5: July 18th, 2018 [ Core ] - Fix the include path for Android builds when building cstool. -- Add posibility to disable universal build for Mac OS. +- Add possibility to disable universal build for Mac OS. - cstool: Separate instruction bytes by spaces. - Fix code path of pkg-config in Cmake. - Update XCode project for XCode 9.1. @@ -444,7 +444,7 @@ Version 3.0.5: July 18th, 2018 [ ARM ] -- Fix an integer overlow bug. +- Fix an integer overflow bug. [ ARM64 ] @@ -464,12 +464,12 @@ Version 3.0.5: July 18th, 2018 [ Sparc ] -- Fix an integer overlow bug. +- Fix an integer overflow bug. [ SystemZ ] -- Fix an integer overlow bug. +- Fix an integer overflow bug. [ Python binding ] @@ -961,7 +961,7 @@ Version 2.1: March 5th, 2014 ---------------------------------- Version 2.0: January 22nd, 2014 -Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. +Release 2.0 deprecates version 1.0 and brings a lot of crucial changes. [ API changes ] @@ -973,7 +973,7 @@ Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. cs_option(). - New option CS_OPT_MEM allows to specify user-defined functions for dynamically memory management used internally by Capstone. This is useful to embed Capstone - into special environments such as kernel or firware. + into special environments such as kernel or firmware. - New API cs_support() can be used to check if this lib supports a particular architecture (this is necessary since we now allow to choose which architectures to compile in). @@ -1009,7 +1009,7 @@ Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. - Cython support has been added, which can further speed up over the default pure Python binding (up to 30% in some cases) - Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list) - to return succesfully disassembled instructions. This improves the performance + to return successfully disassembled instructions. This improves the performance and reduces memory usage. diff --git a/MCInst.c b/MCInst.c index aed26086ae..933327a468 100644 --- a/MCInst.c +++ b/MCInst.c @@ -18,7 +18,7 @@ void MCInst_Init(MCInst *inst) { - // unnecessary to initialize in loop . its expensive and inst->size shuold be honored + // unnecessary to initialize in loop . its expensive and inst->size should be honored inst->Operands[0].Kind = kInvalid; inst->Operands[0].ImmVal = 0; @@ -89,7 +89,7 @@ unsigned MCInst_getNumOperands(const MCInst *inst) return inst->size; } -// This addOperand2 function doesnt free Op +// This addOperand2 function doesn't free Op void MCInst_addOperand2(MCInst *inst, MCOperand *Op) { assert(inst->size < MAX_MC_OPS); diff --git a/MCInst.h b/MCInst.h index 25f8f5c469..08a4f5891d 100644 --- a/MCInst.h +++ b/MCInst.h @@ -153,7 +153,7 @@ MCOperand *MCInst_getOperand(MCInst *inst, unsigned i); unsigned MCInst_getNumOperands(const MCInst *inst); -// This addOperand2 function doesnt free Op +// This addOperand2 function doesn't free Op void MCInst_addOperand2(MCInst *inst, MCOperand *Op); bool MCInst_isPredicable(const MCInstrDesc *MIDesc); diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h index b5f0a17a99..b67054eb94 100644 --- a/arch/AArch64/AArch64BaseInfo.h +++ b/arch/AArch64/AArch64BaseInfo.h @@ -815,7 +815,7 @@ typedef enum TOF { /// an LDG instruction to obtain the tag value. AArch64II_MO_TAGGED = 0x400, - /// MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub. On + /// MO_DLLIMPORTAUX - Symbol refers to "auxiliary" import stub. On /// Arm64EC, there are two kinds of import stubs used for DLL import of /// functions: MO_DLLIMPORT refers to natively callable Arm64 code, and /// MO_DLLIMPORTAUX refers to the original address which can be compared diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index f5bcf70552..a1bf0e2a11 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -318,7 +318,7 @@ void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O) (ImmR == 0 || ImmS < ImmR) && (AArch64_getFeatureBits(MI->csh->mode, AArch64_FeatureAll) || AArch64_getFeatureBits(MI->csh->mode, AArch64_HasV8_2aOps))) { - // BFC takes precedence over its entire range, sligtly differently + // BFC takes precedence over its entire range, slightly differently // to BFI. int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; int LSB = (BitWidth - ImmR) % BitWidth; diff --git a/arch/AArch64/AArch64Linkage.h b/arch/AArch64/AArch64Linkage.h index aa1a0ba2d7..7245a0ce73 100644 --- a/arch/AArch64/AArch64Linkage.h +++ b/arch/AArch64/AArch64Linkage.h @@ -4,7 +4,7 @@ #ifndef CS_AARCH64_LINKAGE_H #define CS_AARCH64_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 7b2fa56094..2a208e3bda 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -247,7 +247,7 @@ void AArch64_init_cs_detail(MCInst *MI) /// So the only generic way to determine, if the memory access is in /// post-indexed addressing mode, is by search for "], #" in /// @p OS. -/// Searching the asm string to determine such a property is enourmously ugly +/// Searching the asm string to determine such a property is enormously ugly /// and wastes resources. /// Sorry, I know and do feel bad about it. But for now it works. static bool AArch64_check_post_index_am(const MCInst *MI, const SStream *OS) { @@ -279,7 +279,7 @@ static void AArch64_check_updates_flags(MCInst *MI) if (!detail_is_set(MI)) return; cs_detail *detail = get_detail(MI); - // Implicity written registers + // Implicitly written registers for (int i = 0; i < detail->regs_write_count; ++i) { if (detail->regs_write[i] == 0) break; diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index 01a96fd69c..a982885fa3 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -14,7 +14,7 @@ typedef enum { #include "AArch64GenCSOpGroup.inc" } aarch64_op_group; -// return name of regiser in friendly string +// return name of register in friendly string const char *AArch64_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h index c6d248287e..16d4b14337 100644 --- a/arch/ARM/ARMAddressingModes.h +++ b/arch/ARM/ARMAddressingModes.h @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMBaseInfo.c b/arch/ARM/ARMBaseInfo.c index 0f46c31639..fc15921eb6 100644 --- a/arch/ARM/ARMBaseInfo.c +++ b/arch/ARM/ARMBaseInfo.c @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index da91a758e1..383c7b1be1 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ @@ -6411,7 +6411,7 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, // Inst. Reason is because MRRC2 stores to two // registers so it's tablegen desc has has two // outputs whereas MCRR doesn't store to any - // registers so all of it's operands are listed + // registers so all of its operands are listed // as inputs, therefore the operand order for // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 212887d1c4..14170eb522 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMInstPrinter.h b/arch/ARM/ARMInstPrinter.h index 772584756c..dcc7ba141e 100644 --- a/arch/ARM/ARMInstPrinter.h +++ b/arch/ARM/ARMInstPrinter.h @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMLinkage.h b/arch/ARM/ARMLinkage.h index deb3b9842a..3dc431d14b 100644 --- a/arch/ARM/ARMLinkage.h +++ b/arch/ARM/ARMLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_ARM_LINKAGE_H #define CS_ARM_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index 19cbcd11f6..beb0214a02 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -531,7 +531,7 @@ static void ARM_add_not_defined_ops(MCInst *MI) } /// Unfortunately there is currently no way to easily extract -/// informaion about the vector data usage (sign and width used). +/// information about the vector data usage (sign and width used). /// See: https://github.com/capstone-engine/capstone/issues/2152 void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type) { @@ -541,7 +541,7 @@ void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type) } /// Unfortunately there is currently no way to easily extract -/// informaion about the vector size. +/// information about the vector size. /// See: https://github.com/capstone-engine/capstone/issues/2152 void ARM_add_vector_size(MCInst *MI, unsigned size) { @@ -2110,7 +2110,7 @@ void ARM_set_detail_op_sysop(MCInst *MI, int Val, arm_op_type type, ARM_get_detail_op(MI, 0)->type = type; switch (type) { default: - assert(0 && "Unkown system operand type."); + assert(0 && "Unknown system operand type."); case ARM_OP_SYSREG: ARM_get_detail_op(MI, 0)->sysop.reg.mclasssysreg = Val; break; diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index 045530302c..21092428f3 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -17,7 +17,7 @@ ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding); extern const ARMSysReg_MClassSysReg * ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding); -// return name of regiser in friendly string +// return name of register in friendly string const char *ARM_reg_name(csh handle, unsigned int reg); void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info); diff --git a/arch/Alpha/AlphaLinkage.h b/arch/Alpha/AlphaLinkage.h index c3501ddecd..ae5008da8b 100644 --- a/arch/Alpha/AlphaLinkage.h +++ b/arch/Alpha/AlphaLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_ALPHA_LINKAGE_H #define CS_ALPHA_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCInst.h" #include "../../MCRegisterInfo.h" diff --git a/arch/HPPA/HPPADisassembler.c b/arch/HPPA/HPPADisassembler.c index 5da27156e0..7db01d7e93 100644 --- a/arch/HPPA/HPPADisassembler.c +++ b/arch/HPPA/HPPADisassembler.c @@ -884,7 +884,7 @@ static void fill_alu_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) goto unit_cond; case 0x2f: push_str_modifier(hppa_ext, "i"); - // fallthough + // fallthrough case 0x26: case 0x0e: case 0x2e: @@ -2857,7 +2857,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) case 0x05: CREATE_FPR_REG(MI, r1); CREATE_FPR_REG(MI, t); - // fallthough + // fallthrough case 0x00: break; default: @@ -2882,7 +2882,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) case 0x00: CREATE_FPR_REG(MI, r1); CREATE_FPR_REG(MI, r2); - // fallthough + // fallthrough case 0x01: break; default: @@ -3041,7 +3041,7 @@ static void fill_float_mods(uint32_t insn, uint32_t class, hppa_ext *hppa_ext, return; case 0x03: push_str_modifier(hppa_ext, "t"); - // fallthough + // fallthrough case 0x02: push_str_modifier(hppa_ext, float_format_names[sf]); diff --git a/arch/M680X/M680XDisassembler.c b/arch/M680X/M680XDisassembler.c index a0ade36733..6e71c465f3 100644 --- a/arch/M680X/M680XDisassembler.c +++ b/arch/M680X/M680XDisassembler.c @@ -149,7 +149,7 @@ typedef struct insn_props { ////////////////////////////////////////////////////////////////////////////// -// M680X instuctions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2). +// M680X instructions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2). // A reader is needed to read a byte or word from a given memory address. // See also X86 reader(...) static bool read_byte(const m680x_info *info, uint8_t *byte, uint16_t address) @@ -627,7 +627,7 @@ typedef struct insn_desc { uint16_t insn_size; } insn_desc; -// If successfull return the additional byte size needed for M6809 +// If successful return the additional byte size needed for M6809 // indexed addressing mode (including the indexed addressing post_byte). // On error return -1. static int get_indexed09_post_byte_size(const m680x_info *info, @@ -681,7 +681,7 @@ static int get_indexed09_post_byte_size(const m680x_info *info, return 1; } -// If successfull return the additional byte size needed for CPU12 +// If successful return the additional byte size needed for CPU12 // indexed addressing mode (including the indexed addressing post_byte). // On error return -1. static int get_indexed12_post_byte_size(const m680x_info *info, @@ -750,7 +750,7 @@ static bool is_tfm_reg_valid(const m680x_info *info, uint8_t reg_nibble) return reg_nibble <= 4; } -// If successfull return the additional byte size needed for CPU12 +// If successful return the additional byte size needed for CPU12 // loop instructions DBEQ/DBNE/IBEQ/IBNE/TBEQ/TBNE (including the post byte). // On error return -1. static int get_loop_post_byte_size(const m680x_info *info, uint16_t address) @@ -772,7 +772,7 @@ static int get_loop_post_byte_size(const m680x_info *info, uint16_t address) return 2; } -// If successfull return the additional byte size needed for HD6309 +// If successful return the additional byte size needed for HD6309 // bit move instructions BAND/BEOR/BIAND/BIEOR/BIOR/BOR/LDBT/STBT // (including the post byte). // On error return -1. @@ -1885,7 +1885,7 @@ static unsigned int m680x_disassemble(MCInst *MI, m680x_info *info, access_mode = g_insn_props[info->insn].access_mode; - // Fix for M6805 BSET/BCLR. It has a differnt operand order + // Fix for M6805 BSET/BCLR. It has a different operand order // in comparison to the M6811 if ((info->cpu->insn_cc_not_modified[0] == info->insn) || (info->cpu->insn_cc_not_modified[1] == info->insn)) diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c index b502e5ae9f..5c555ae4c1 100644 --- a/arch/M68K/M68KDisassembler.c +++ b/arch/M68K/M68KDisassembler.c @@ -3526,7 +3526,7 @@ static void build_regs_read_write_counts(m68k_info *info) // first operand is always read update_op_reg_list(info, &info->extension.operands[0], 0); - // remaning write + // remaining write for (i = 1; i < info->extension.op_count; ++i) update_op_reg_list(info, &info->extension.operands[i], 1); } diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index 294082394a..c5c6b5c97b 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -365,7 +365,7 @@ void Mips_init(MCRegisterInfo *MRI) } /// Read two bytes from the ArrayRef and return 16 bit halfword sorted -/// according to the given endianess. +/// according to the given endianness. static void readInstruction16(unsigned char *code, uint32_t *insn, bool isBigEndian) { @@ -377,7 +377,7 @@ static void readInstruction16(unsigned char *code, uint32_t *insn, } /// readInstruction - read four bytes from the MemoryObject -/// and return 32 bit word sorted according to the given endianess +/// and return 32 bit word sorted according to the given endianness static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) { // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) diff --git a/arch/Mips/MipsMapping.h b/arch/Mips/MipsMapping.h index 42b86e6e98..2b5c95dce5 100644 --- a/arch/Mips/MipsMapping.h +++ b/arch/Mips/MipsMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *Mips_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c index 7ce0916fd8..a13aa0fbd9 100644 --- a/arch/PowerPC/PPCInstPrinter.c +++ b/arch/PowerPC/PPCInstPrinter.c @@ -650,7 +650,7 @@ void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O) { add_cs_detail(MI, PPC_OP_GROUP_TLSCall, OpNo); - // Expresion logic removed. + // Expression logic removed. set_mem_access(MI, true); SStream_concat0(O, "("); @@ -682,7 +682,7 @@ bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName) } /// getVerboseConditionalRegName - This method expands the condition register -/// when requested explicitly or targetting Darwin. +/// when requested explicitly or targeting Darwin. const char *getVerboseConditionRegName(const MCInst *MI, unsigned RegNum, unsigned RegEncoding) { diff --git a/arch/PowerPC/PPCLinkage.h b/arch/PowerPC/PPCLinkage.h index 58725c59bb..9b0463a3a9 100644 --- a/arch/PowerPC/PPCLinkage.h +++ b/arch/PowerPC/PPCLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_PPC_LINKAGE_H #define CS_PPC_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c index 73444de7fa..f3e4503f73 100644 --- a/arch/PowerPC/PPCMapping.c +++ b/arch/PowerPC/PPCMapping.c @@ -203,7 +203,7 @@ void PPC_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen) } } -/// Inialize PPCs detail. +/// Initialize PPCs detail. void PPC_init_cs_detail(MCInst *MI) { if (!detail_is_set(MI)) diff --git a/arch/PowerPC/PPCMapping.h b/arch/PowerPC/PPCMapping.h index bfaaa3009e..a30813144b 100644 --- a/arch/PowerPC/PPCMapping.h +++ b/arch/PowerPC/PPCMapping.h @@ -16,7 +16,7 @@ void PPC_init_mri(MCRegisterInfo *MRI); void PPC_init_cs_detail(MCInst *MI); -// return name of regiser in friendly string +// return name of register in friendly string const char *PPC_reg_name(csh handle, unsigned int reg); void PPC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info); diff --git a/arch/RISCV/RISCVGenAsmWriter.inc b/arch/RISCV/RISCVGenAsmWriter.inc index dadbd5c621..b4dde75836 100644 --- a/arch/RISCV/RISCVGenAsmWriter.inc +++ b/arch/RISCV/RISCVGenAsmWriter.inc @@ -2619,7 +2619,7 @@ static void printCustomAliasOperand( static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, unsigned PredicateIndex) { // TODO: need some constant untils operate the MCOperand, - // but current CAPSTONE does't have. + // but current CAPSTONE doesn't have. // So, We just return true return true; diff --git a/arch/SH/SHDisassembler.c b/arch/SH/SHDisassembler.c index 879a8508a5..8f788096b4 100644 --- a/arch/SH/SHDisassembler.c +++ b/arch/SH/SHDisassembler.c @@ -2108,7 +2108,7 @@ static bool sh_disassemble(const uint8_t *code, MCInst *MI, uint64_t address, insn = code[1] << 8 | code[0]; } if (mode & CS_MODE_SH2A) { - /* SH2A 32bit instrcution test */ + /* SH2A 32bit instruction test */ if (((insn & 0xf007) == 0x3001 || (insn & 0xf00e) == 0x0000)) { if (code_len < 4) diff --git a/arch/Sparc/SparcMapping.h b/arch/Sparc/SparcMapping.h index 1c8c1b19d6..9c930f0f51 100644 --- a/arch/Sparc/SparcMapping.h +++ b/arch/Sparc/SparcMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *Sparc_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h index 9a6ceb356e..0f8909cea2 100644 --- a/arch/SystemZ/SystemZMapping.h +++ b/arch/SystemZ/SystemZMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *SystemZ_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/TMS320C64x/TMS320C64xMapping.h b/arch/TMS320C64x/TMS320C64xMapping.h index ce26d3e89a..e8514283f9 100644 --- a/arch/TMS320C64x/TMS320C64xMapping.h +++ b/arch/TMS320C64x/TMS320C64xMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *TMS320C64x_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/TriCore/TriCoreCallingConv.td b/arch/TriCore/TriCoreCallingConv.td index 0a43914802..f9ebe1b30a 100644 --- a/arch/TriCore/TriCoreCallingConv.td +++ b/arch/TriCore/TriCoreCallingConv.td @@ -46,7 +46,7 @@ def CC_TriCore : CallingConv<[ // Pointer arguments are handled inside TriCoreIselLowering, because // LLVM lowers i32** type into i32, hence there is no way to distingusish - // beetwen a pointer type and an integer type. + // between a pointer type and an integer type. diff --git a/arch/TriCore/TriCoreLinkage.h b/arch/TriCore/TriCoreLinkage.h index cfee58f77f..3689de36c2 100644 --- a/arch/TriCore/TriCoreLinkage.h +++ b/arch/TriCore/TriCoreLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_TRICORE_LINKAGE_H #define CS_TRICORE_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index 800d9e4e70..3106dc74a0 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -534,7 +534,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; - // truncat imm for non-64bit + // truncate imm for non-64bit if (MI->csh->mode != CS_MODE_64) { imm = imm & 0xffffffff; } diff --git a/arch/X86/X86DisassemblerDecoder.c b/arch/X86/X86DisassemblerDecoder.c index 22acab36e5..95ac06f8b7 100644 --- a/arch/X86/X86DisassemblerDecoder.c +++ b/arch/X86/X86DisassemblerDecoder.c @@ -1155,8 +1155,8 @@ static int getID(struct InternalInstruction *insn) } /* - * The tables can't distinquish between cases where the W-bit is used to - * select register size and cases where its a required part of the opcode. + * The tables can't distinguish between cases where the W-bit is used to + * select register size and cases where it's a required part of the opcode. */ if ((insn->vectorExtensionType == TYPE_EVEX && wFromEVEX3of4(insn->vectorExtensionPrefix[2])) || diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c index bdd4457850..7f83cddd5d 100644 --- a/arch/X86/X86IntelInstPrinter.c +++ b/arch/X86/X86IntelInstPrinter.c @@ -765,7 +765,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; uint8_t opsize = X86_immediate_size(MI->Opcode, NULL); - // truncat imm for non-64bit + // truncate imm for non-64bit if (MI->csh->mode != CS_MODE_64) { imm = imm & 0xffffffff; } diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c index a5b8729082..46ecfcb77b 100644 --- a/arch/X86/X86Mapping.c +++ b/arch/X86/X86Mapping.c @@ -2098,7 +2098,7 @@ void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v) #ifndef CAPSTONE_DIET // map instruction to its characteristics typedef struct insn_op { - uint64_t flags; // how this instruction update EFLAGS(arithmetic instrcutions) of FPU FLAGS(for FPU instructions) + uint64_t flags; // how this instruction update EFLAGS(arithmetic instructions) of FPU FLAGS(for FPU instructions) uint8_t access[6]; } insn_op; diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h index c6dc40377f..933f208dfa 100644 --- a/arch/X86/X86Mapping.h +++ b/arch/X86/X86Mapping.h @@ -32,7 +32,7 @@ x86_reg x86_map_sib_index(int r); // map seg_override to x86_reg x86_reg x86_map_segment(int r); -// return name of regiser in friendly string +// return name of register in friendly string const char *X86_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/XCore/XCoreMapping.h b/arch/XCore/XCoreMapping.h index f9b506a252..f4cad95c91 100644 --- a/arch/XCore/XCoreMapping.h +++ b/arch/XCore/XCoreMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *XCore_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java index b1117d242d..1a37b5d400 100644 --- a/bindings/java/capstone/Capstone.java +++ b/bindings/java/capstone/Capstone.java @@ -490,13 +490,13 @@ public void setMode(int opt) { } } - // destructor automatically caled at destroyed time. + // destructor automatically called at destroyed time. protected void finalize() { // FIXME: crashed on Ubuntu 14.04 64bit, OpenJDK java 1.6.0_33 // cs.cs_close(ns.handleRef); } - // destructor automatically caled at destroyed time. + // destructor automatically called at destroyed time. public int close() { return cs.cs_close(ns.handleRef); } diff --git a/bindings/ocaml/capstone.ml b/bindings/ocaml/capstone.ml index 9019cde996..7899091826 100644 --- a/bindings/ocaml/capstone.ml +++ b/bindings/ocaml/capstone.ml @@ -63,7 +63,7 @@ type mode = (* Runtime option for the disassembled engine *) type opt_type = - | CS_OPT_SYNTAX (* Asssembly output syntax *) + | CS_OPT_SYNTAX (* Assembly output syntax *) | CS_OPT_DETAIL (* Break down instruction structure into details *) | CS_OPT_MODE (* Change engine's mode at run-time *) | CS_OPT_MEM (* User-defined dynamic memory related functions *) diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 8e1174e396..154e6f1105 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -341,7 +341,7 @@ CS_GRP_BRANCH_RELATIVE = 7 # all relative branching instructions # Access types for instruction operands. -CS_AC_INVALID = 0 # Invalid/unitialized access type. +CS_AC_INVALID = 0 # Invalid/uninitialized access type. CS_AC_READ = (1 << 0) # Operand that is read from. CS_AC_WRITE = (1 << 1) # Operand that is written to. CS_AC_READ_WRITE = (2) diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py index 3c08e7783c..3ac5348dab 100755 --- a/bindings/python/test_x86.py +++ b/bindings/python/test_x86.py @@ -180,7 +180,7 @@ def print_string_hex(comment, str): # print instruction's opcode print_string_hex("\tOpcode:", insn.opcode) - # print operand's REX prefix (non-zero value is relavant for x86_64 instructions) + # print operand's REX prefix (non-zero value is relevant for x86_64 instructions) print("\trex: 0x%x" % (insn.rex)) # print operand's address size diff --git a/bindings/vb6/CX86Inst.cls b/bindings/vb6/CX86Inst.cls index bfdb19765e..70e62258d4 100644 --- a/bindings/vb6/CX86Inst.cls +++ b/bindings/vb6/CX86Inst.cls @@ -31,12 +31,12 @@ Option Explicit ' // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) ' uint8_t prefix[4]; ' -' // Instruction opcode, wich can be from 1 to 4 bytes in size. +' // Instruction opcode, which can be from 1 to 4 bytes in size. ' // This contains VEX opcode as well. ' // An trailing opcode byte gets value 0 when irrelevant. ' uint8_t opcode[4]; ' -' // REX prefix: only a non-zero value is relavant for x86_64 +' // REX prefix: only a non-zero value is relevant for x86_64 ' uint8_t rex; ' ' // Address size, which can be overrided with above prefix[5]. @@ -54,7 +54,7 @@ Option Explicit ' /* SIB state */ ' // SIB index register, or X86_REG_INVALID when irrelevant. ' x86_reg sib_index; -' // SIB scale. only applicable if sib_index is relavant. +' // SIB scale. only applicable if sib_index is relevant. ' int8_t sib_scale; ' // SIB base register, or X86_REG_INVALID when irrelevant. ' x86_reg sib_base; diff --git a/bindings/vb6/mMisc.bas b/bindings/vb6/mMisc.bas index 2ccb1308e0..561d1b68d7 100644 --- a/bindings/vb6/mMisc.bas +++ b/bindings/vb6/mMisc.bas @@ -148,7 +148,7 @@ Function AryIsEmpty(ary) As Boolean Dim i As Long On Error GoTo oops - i = UBound(ary) '<- throws error if not initalized + i = UBound(ary) '<- throws error if not initialized AryIsEmpty = False Exit Function oops: AryIsEmpty = True @@ -211,7 +211,7 @@ Private Sub bpush(bAry() As Byte, b As Byte) 'this modifies parent ary object On Error GoTo init Dim x As Long - x = UBound(bAry) '<-throws Error If Not initalized + x = UBound(bAry) '<-throws Error If Not initialized ReDim Preserve bAry(UBound(bAry) + 1) bAry(UBound(bAry)) = b diff --git a/bindings/vb6/mx86.bas b/bindings/vb6/mx86.bas index 2fc47da180..c10b8b4ecc 100644 --- a/bindings/vb6/mx86.bas +++ b/bindings/vb6/mx86.bas @@ -388,18 +388,18 @@ Public Type cs_x86 ' prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) prefix(0 To 3) As Byte ' UNSIGNED - ' Instruction opcode, wich can be from 1 to 4 bytes in size. + ' Instruction opcode, which can be from 1 to 4 bytes in size. ' This contains VEX opcode as well. ' An trailing opcode byte gets value 0 when irrelevant. opcode(0 To 3) As Byte ' UNSIGNED - rex As Byte ' REX prefix: only a non-zero value is relavant for x86_64 UNSIGNED + rex As Byte ' REX prefix: only a non-zero value is relevant for x86_64 UNSIGNED addr_size As Byte ' Address size, which can be overrided with above prefix[5]. UNSIGNED modrm As Byte ' ModR/M byte UNSIGNED sib As Byte ' SIB value, or 0 when irrelevant. UNSIGNED disp As Long ' Displacement value, or 0 when irrelevant. sib_index As x86_reg ' SIB index register, or X86_REG_INVALID when irrelevant. - sib_scale As Byte ' SIB scale. only applicable if sib_index is relavant. + sib_scale As Byte ' SIB scale. only applicable if sib_index is relevant. sib_base As x86_reg ' SIB base register, or X86_REG_INVALID when irrelevant. sse_cc As x86_sse_cc ' SSE Code Condition avx_cc As x86_avx_cc ' AVX Code Condition diff --git a/config.mk b/config.mk index 5b7a3d14e0..fb92ac7449 100644 --- a/config.mk +++ b/config.mk @@ -25,7 +25,7 @@ CAPSTONE_USE_SYS_DYN_MEM ?= yes # such as @regs_read/write & @group. The amount of binary size reduced is # up to 50% in some individual archs. # -# NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read, +# NOTE: we still keep all those related fields @mnemonic, @op_str, @regs_read, # @regs_write, @groups, etc in fields in cs_insn structure regardless, but they # will not be updated (i.e empty), thus become irrelevant. diff --git a/cs.c b/cs.c index 25476df9f6..65f89b8e5b 100644 --- a/cs.c +++ b/cs.c @@ -784,7 +784,7 @@ static int str_replace(char *result, char *target, const char *str1, char *str2) { // only perform replacement if the output fits into result if (strlen(target) - strlen(str1) + strlen(str2) < CS_MNEMONIC_SIZE - 1) { - // copy str2 to begining of result + // copy str2 to beginning of result strcpy(result, str2); // skip str1 - already replaced by str2 strcat(result, target + strlen(str1)); @@ -1120,7 +1120,7 @@ static void skipdata_opstr(char *opstr, const uint8_t *buffer, size_t size) } #endif -// dynamicly allocate memory to contain disasm insn +// dynamically allocate memory to contain disasm insn // NOTE: caller must free() the allocated memory itself to avoid memory leaking CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) @@ -1288,7 +1288,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64 // continue to fill in the cache after the last instruction insn_cache = (cs_insn *)((char *)total + sizeof(cs_insn) * c); - // reset f back to 0, so we fill in the cache from begining + // reset f back to 0, so we fill in the cache from beginning f = 0; } else insn_cache++; diff --git a/include/capstone/cs_operand.h b/include/capstone/cs_operand.h index 9110813c1b..81f2697c46 100644 --- a/include/capstone/cs_operand.h +++ b/include/capstone/cs_operand.h @@ -26,8 +26,8 @@ typedef enum cs_op_type { CS_OP_SPECIAL = 0x10, ///< Special operands from archs CS_OP_MEM = 0x80, ///< Memory operand. Can be ORed with another operand type. - CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referenceing register operand. - CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referenceing immediate operand. + CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referencing register operand. + CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referencing immediate operand. } cs_op_type; diff --git a/include/capstone/m680x.h b/include/capstone/m680x.h index c8296e49de..07533cce97 100644 --- a/include/capstone/m680x.h +++ b/include/capstone/m680x.h @@ -161,7 +161,7 @@ typedef enum m680x_group_type { /// instruction mnemonic #define M680X_SECOND_OP_IN_MNEM 2 -/// The M680X instruction and it's operands +/// The M680X instruction and its operands typedef struct cs_m680x { uint8_t flags; ///< See: M680X instruction flags uint8_t op_count; ///< number of operands for the instruction or 0 diff --git a/include/capstone/m68k.h b/include/capstone/m68k.h index 41e23f3883..35918d38ac 100644 --- a/include/capstone/m68k.h +++ b/include/capstone/m68k.h @@ -206,7 +206,7 @@ typedef struct m68k_op_size { }; } m68k_op_size; -/// The M68K instruction and it's operands +/// The M68K instruction and its operands typedef struct cs_m68k { // Number of operands of this instruction or 0 when instruction has no operand. cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction. diff --git a/include/capstone/mos65xx.h b/include/capstone/mos65xx.h index 13c2788a3e..e942c96184 100644 --- a/include/capstone/mos65xx.h +++ b/include/capstone/mos65xx.h @@ -186,7 +186,7 @@ typedef struct cs_mos65xx_op { }; } cs_mos65xx_op; -/// The MOS65XX address mode and it's operands +/// The MOS65XX address mode and its operands typedef struct cs_mos65xx { mos65xx_address_mode am; bool modifies_flags; diff --git a/include/capstone/ppc.h b/include/capstone/ppc.h index 27789dafe3..b38c4eee97 100644 --- a/include/capstone/ppc.h +++ b/include/capstone/ppc.h @@ -42,7 +42,7 @@ extern "C" { /// |--------|-------------|-------|------------|------------| /// Alter- | | Hint bit: | | Hint bit: | Hint bit: | /// native | None | a | None | a | t | -/// meaning | | or ingored | | or ignored | or ignored | +/// meaning | | or ignored | | or ignored | or ignored | /// /// NOTE: If we do not decrement the counter, it is not used for the condition. /// @@ -62,8 +62,8 @@ typedef enum ppc_pred { PPC_PRED_GE = (0 << 5) | 4, PPC_PRED_GT = (1 << 5) | 12, PPC_PRED_NE = (2 << 5) | 4, - PPC_PRED_UN = (3 << 5) | 12, ///< Unordered (after fp comparision) - PPC_PRED_NU = (3 << 5) | 4, ///< Not Unordered (after fp comparision) + PPC_PRED_UN = (3 << 5) | 12, ///< Unordered (after fp comparison) + PPC_PRED_NU = (3 << 5) | 4, ///< Not Unordered (after fp comparison) PPC_PRED_SO = (3 << 5) | 12, ///< summary overflow PPC_PRED_NS = (3 << 5) | 4, ///< not summary overflow @@ -154,7 +154,7 @@ typedef enum { } ppc_bh; -/// Returns the predicate wihtout branch hint information. +/// Returns the predicate without branch hint information. inline static ppc_pred PPC_get_no_hint_pred(ppc_pred Code) { switch (Code) { diff --git a/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch b/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch index 795f5ba5f6..d59b2dc870 100644 --- a/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch +++ b/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch @@ -1,4 +1,4 @@ -# Sets the correct access attributes for register lists of LDM instrucions. +# Sets the correct access attributes for register lists of LDM instructions. # See issue: https://github.com/llvm/llvm-project/issues/62455 diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc diff --git a/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch b/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch index fadb1a462f..5c59b0d873 100644 --- a/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch +++ b/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch @@ -1,4 +1,4 @@ -# Sets the correct access attributes for register lists of VSCCLRM instrucions. +# Sets the correct access attributes for register lists of VSCCLRM instructions. # See issue: https://github.com/llvm/llvm-project/issues/62455 diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc diff --git a/suite/autogen_x86imm.py b/suite/autogen_x86imm.py index 1e6fb67803..a764b81a65 100755 --- a/suite/autogen_x86imm.py +++ b/suite/autogen_x86imm.py @@ -1,6 +1,6 @@ #!/usr/bin/python # By Nguyen Anh Quynh, 2015 -# This tool extract sizes of immediadte operands from X86 instruction names. +# This tool extract sizes of immediate operands from X86 instruction names. # Syntax: ./autogen_x86imm.py # Gather immediate sizes to put into X86ImmSize.inc diff --git a/suite/cstest/README.md b/suite/cstest/README.md index a9880dadf6..d2d2b4cc8e 100644 --- a/suite/cstest/README.md +++ b/suite/cstest/README.md @@ -19,7 +19,7 @@ mkdir build cd build cmake .. make -sudo make isntall +sudo make install ``` ## Build diff --git a/suite/disasm_mc.sh b/suite/disasm_mc.sh index 8de5a1529b..6b8936cd2c 100755 --- a/suite/disasm_mc.sh +++ b/suite/disasm_mc.sh @@ -4,7 +4,7 @@ find MC/ -name *.cs | ./disasm_mc.py -# To test just one architecture, specify the corresponsing dir: +# To test just one architecture, specify the corresponding dir: # $ find MC/X86 -name *.cs | ./disasm_mc.py # To test just one input file, run disasm_mc.py with that file: diff --git a/suite/fuzz/driverbin.c b/suite/fuzz/driverbin.c index d5e3a0fcc2..dfb5293850 100644 --- a/suite/fuzz/driverbin.c +++ b/suite/fuzz/driverbin.c @@ -77,7 +77,7 @@ int main(int argc, char** argv) } printf("\n"); - //lauch fuzzer + //launch fuzzer LLVMFuzzerTestOneInput(Data, Size); fclose(fp); } diff --git a/suite/fuzz/drivermc.c b/suite/fuzz/drivermc.c index ff31ebdeec..5b53543d3c 100644 --- a/suite/fuzz/drivermc.c +++ b/suite/fuzz/drivermc.c @@ -128,7 +128,7 @@ int main(int argc, char** argv) return 1; } } - //lauch fuzzer + //launch fuzzer LLVMFuzzerTestOneInput(Data, Size); } fclose(fp); diff --git a/suite/fuzz/onefile.c b/suite/fuzz/onefile.c index 74be3063a8..c3c6551abc 100644 --- a/suite/fuzz/onefile.c +++ b/suite/fuzz/onefile.c @@ -42,7 +42,7 @@ int main(int argc, char** argv) return 2; } - //lauch fuzzer + //launch fuzzer LLVMFuzzerTestOneInput(Data, Size); free(Data); fclose(fp); diff --git a/suite/synctools/README b/suite/synctools/README index 61a0ec45d8..247ee93439 100644 --- a/suite/synctools/README +++ b/suite/synctools/README @@ -11,7 +11,7 @@ For X86 2. Run disassemblertables_reduce2 & disassemblertables_reduce2 to generate optimized (index table) X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc - # use 2x name to avoid overwritting X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc + # use 2x name to avoid overwriting X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc $ make $ ./disassemblertables2 > X86GenDisassemblerTables2x.inc diff --git a/suite/synctools/asmwriter.py b/suite/synctools/asmwriter.py index 33d0a22312..7549b64ceb 100755 --- a/suite/synctools/asmwriter.py +++ b/suite/synctools/asmwriter.py @@ -682,7 +682,7 @@ def print_line(line): break; } } - // Chech for match + // Check for match if(opcode != OpToPatterns[OpToIndex].Opcode) return NULL; diff --git a/suite/synctools/tablegen/X86/X86InstrAVX512.td b/suite/synctools/tablegen/X86/X86InstrAVX512.td index 17ac45ba6f..3872b128ba 100644 --- a/suite/synctools/tablegen/X86/X86InstrAVX512.td +++ b/suite/synctools/tablegen/X86/X86InstrAVX512.td @@ -107,7 +107,7 @@ class X86VectorVTInfo("v" # !srl(Size, 6) # "i64"); @@ -251,7 +251,7 @@ multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. // This version uses a separate dag for non-masking and masking. multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, @@ -272,7 +272,7 @@ multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -423,7 +423,7 @@ multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable_logic O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -7557,7 +7557,7 @@ multiclass avx512_cvt_fp_scalar opc, string OpcodeStr, X86VectorVTInfo _ } } -// Scalar Coversion with SAE - suppress all exceptions +// Scalar Conversion with SAE - suppress all exceptions multiclass avx512_cvt_fp_sae_scalar opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { @@ -7671,7 +7671,7 @@ multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, ))>, EVEX, EVEX_B, Sched<[sched.Folded]>; } -// Coversion with SAE - suppress all exceptions +// Conversion with SAE - suppress all exceptions multiclass avx512_vcvt_fp_sae opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { diff --git a/suite/synctools/tablegen/X86/X86InstrCompiler.td b/suite/synctools/tablegen/X86/X86InstrCompiler.td index 373f850203..76b93bdada 100644 --- a/suite/synctools/tablegen/X86/X86InstrCompiler.td +++ b/suite/synctools/tablegen/X86/X86InstrCompiler.td @@ -795,9 +795,9 @@ defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; // the base pointer. Indeed, in such situation RBX is a reserved // register and the register allocator will ignore any use/def of // it. In other words, the register will not fix the clobbering of -// RBX that will happen when setting the arguments for the instrucion. +// RBX that will happen when setting the arguments for the instruction. // -// Unlike the actual related instuction, we mark that this one +// Unlike the actual related instruction, we mark that this one // defines EBX (instead of using EBX). // The rationale is that we will define RBX during the expansion of // the pseudo. The argument feeding EBX is ebx_input. diff --git a/suite/synctools/tablegen/X86/X86InstrFMA.td b/suite/synctools/tablegen/X86/X86InstrFMA.td index a559f62c8f..18277417a3 100644 --- a/suite/synctools/tablegen/X86/X86InstrFMA.td +++ b/suite/synctools/tablegen/X86/X86InstrFMA.td @@ -166,7 +166,7 @@ let ExeDomain = SSEPackedDouble in { } // All source register operands of FMA opcodes defined in fma3s_rm multiclass -// can be commuted. In many cases such commute transformation requres an opcode +// can be commuted. In many cases such commute transformation requires an opcode // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form // would require an opcode change to FMA*231: // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; diff --git a/suite/synctools/tablegen/X86/X86InstrFPStack.td b/suite/synctools/tablegen/X86/X86InstrFPStack.td index b0c9bd1637..a21f077927 100644 --- a/suite/synctools/tablegen/X86/X86InstrFPStack.td +++ b/suite/synctools/tablegen/X86/X86InstrFPStack.td @@ -242,7 +242,7 @@ defm MUL : FPBinary_rr; defm DIV : FPBinary_rr; } -// Sets the scheduling resources for the actual NAME#_Fm defintions. +// Sets the scheduling resources for the actual NAME#_Fm definitions. let SchedRW = [WriteFAddLd] in { defm ADD : FPBinary; defm SUB : FPBinary; diff --git a/suite/synctools/tablegen/X86/X86InstrSSE.td b/suite/synctools/tablegen/X86/X86InstrSSE.td index c99af69f6f..5c6b4155b1 100644 --- a/suite/synctools/tablegen/X86/X86InstrSSE.td +++ b/suite/synctools/tablegen/X86/X86InstrSSE.td @@ -1004,7 +1004,7 @@ defm CVTSI642SD : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64, // and/or XMM operand(s). // FIXME: We probably want to match the rm form only when optimizing for -// size, to avoid false depenendecies (see sse_fp_unop_s for details) +// size, to avoid false dependencies (see sse_fp_unop_s for details) multiclass sse12_cvt_sint opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, Operand memop, ComplexPattern mem_cpat, string asm, X86FoldableSchedWrite sched> { @@ -3122,7 +3122,7 @@ def PAUSE : I<0x90, RawFrm, (outs), (ins), let SchedRW = [WriteFence] in { // Load, store, and memory fence -// TODO: As with mfence, we may want to ease the availablity of sfence/lfence +// TODO: As with mfence, we may want to ease the availability of sfence/lfence // to include any 64-bit target. def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>, PS, Requires<[HasSSE1]>; diff --git a/suite/synctools/tablegen/X86/X86InstrSystem.td b/suite/synctools/tablegen/X86/X86InstrSystem.td index 5bb0a5f37d..5bc58e298c 100644 --- a/suite/synctools/tablegen/X86/X86InstrSystem.td +++ b/suite/synctools/tablegen/X86/X86InstrSystem.td @@ -711,7 +711,7 @@ def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, let Predicates = [In64BitMode, HasRDPID] in { // Due to silly instruction definition, we have to compensate for the - // instruction outputing a 64-bit register. + // instruction outputting a 64-bit register. def : Pat<(int_x86_rdpid), (EXTRACT_SUBREG (RDPID64), sub_32bit)>; } diff --git a/suite/synctools/tablegen/X86/X86InstrTSX.td b/suite/synctools/tablegen/X86/X86InstrTSX.td index b1fdd18074..8b9f723a41 100644 --- a/suite/synctools/tablegen/X86/X86InstrTSX.td +++ b/suite/synctools/tablegen/X86/X86InstrTSX.td @@ -32,7 +32,7 @@ def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), "xbegin\t$dst", []>, OpSize32; } -// Psuedo instruction to fake the definition of EAX on the fallback code path. +// Pseudo instruction to fake the definition of EAX on the fallback code path. //let isPseudo = 1, Defs = [EAX] in { //def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; //} diff --git a/suite/synctools/tablegen/X86/X86RegisterInfo.td b/suite/synctools/tablegen/X86/X86RegisterInfo.td index ee9e7891f9..907d402223 100644 --- a/suite/synctools/tablegen/X86/X86RegisterInfo.td +++ b/suite/synctools/tablegen/X86/X86RegisterInfo.td @@ -488,7 +488,7 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; -// When RBP is used as a base pointer in a 32-bit addresses environement, +// When RBP is used as a base pointer in a 32-bit addresses environment, // this is also safe to use the full register to access addresses. // Since RBP will never be spilled, stick to a 32 alignment to save // on memory consumption. diff --git a/suite/synctools/tablegen/X86/X86Schedule.td b/suite/synctools/tablegen/X86/X86Schedule.td index ef9ce94706..6215d58ae1 100644 --- a/suite/synctools/tablegen/X86/X86Schedule.td +++ b/suite/synctools/tablegen/X86/X86Schedule.td @@ -628,8 +628,8 @@ def SchedWriteFShuffleSizes // Generic Processor Scheduler Models. // IssueWidth is analogous to the number of decode units. Core and its -// descendents, including Nehalem and SandyBridge have 4 decoders. -// Resources beyond the decoder operate on micro-ops and are bufferred +// descendants, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are buffered // so adjacent micro-ops don't directly compete. // // MicroOpBufferSize > 1 indicates that RAW dependencies can be diff --git a/suite/synctools/tablegen/X86/X86ScheduleAtom.td b/suite/synctools/tablegen/X86/X86ScheduleAtom.td index a7f461c456..daa6fc73cc 100644 --- a/suite/synctools/tablegen/X86/X86ScheduleAtom.td +++ b/suite/synctools/tablegen/X86/X86ScheduleAtom.td @@ -20,8 +20,8 @@ def AtomModel : SchedMachineModel { let IssueWidth = 2; // Allows 2 instructions per scheduling group. let MicroOpBufferSize = 0; // In-order execution, always hide latency. - let LoadLatency = 3; // Expected cycles, may be overriden. - let HighLatency = 30;// Expected, may be overriden. + let LoadLatency = 3; // Expected cycles, may be overridden. + let HighLatency = 30;// Expected, may be overridden. // On the Atom, the throughput for taken branches is 2 cycles. For small // simple loops, expand by a small factor to hide the backedge cost. diff --git a/suite/synctools/tablegen/X86/back/X86InstrAVX512.td b/suite/synctools/tablegen/X86/back/X86InstrAVX512.td index 43f16634c2..fcb3723121 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrAVX512.td +++ b/suite/synctools/tablegen/X86/back/X86InstrAVX512.td @@ -107,7 +107,7 @@ class X86VectorVTInfo("v" # !srl(Size, 6) # "i64"); @@ -251,7 +251,7 @@ multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. // This version uses a separate dag for non-masking and masking. multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, @@ -272,7 +272,7 @@ multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -423,7 +423,7 @@ multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable_logic O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -7557,7 +7557,7 @@ multiclass avx512_cvt_fp_scalar opc, string OpcodeStr, X86VectorVTInfo _ } } -// Scalar Coversion with SAE - suppress all exceptions +// Scalar Conversion with SAE - suppress all exceptions multiclass avx512_cvt_fp_sae_scalar opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { @@ -7671,7 +7671,7 @@ multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, ))>, EVEX, EVEX_B, Sched<[sched.Folded]>; } -// Coversion with SAE - suppress all exceptions +// Conversion with SAE - suppress all exceptions multiclass avx512_vcvt_fp_sae opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { diff --git a/suite/synctools/tablegen/X86/back/X86InstrCompiler.td b/suite/synctools/tablegen/X86/back/X86InstrCompiler.td index 373f850203..76b93bdada 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrCompiler.td +++ b/suite/synctools/tablegen/X86/back/X86InstrCompiler.td @@ -795,9 +795,9 @@ defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; // the base pointer. Indeed, in such situation RBX is a reserved // register and the register allocator will ignore any use/def of // it. In other words, the register will not fix the clobbering of -// RBX that will happen when setting the arguments for the instrucion. +// RBX that will happen when setting the arguments for the instruction. // -// Unlike the actual related instuction, we mark that this one +// Unlike the actual related instruction, we mark that this one // defines EBX (instead of using EBX). // The rationale is that we will define RBX during the expansion of // the pseudo. The argument feeding EBX is ebx_input. diff --git a/suite/synctools/tablegen/X86/back/X86InstrFMA.td b/suite/synctools/tablegen/X86/back/X86InstrFMA.td index a559f62c8f..18277417a3 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrFMA.td +++ b/suite/synctools/tablegen/X86/back/X86InstrFMA.td @@ -166,7 +166,7 @@ let ExeDomain = SSEPackedDouble in { } // All source register operands of FMA opcodes defined in fma3s_rm multiclass -// can be commuted. In many cases such commute transformation requres an opcode +// can be commuted. In many cases such commute transformation requires an opcode // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form // would require an opcode change to FMA*231: // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; diff --git a/suite/synctools/tablegen/X86/back/X86InstrFPStack.td b/suite/synctools/tablegen/X86/back/X86InstrFPStack.td index b0c9bd1637..a21f077927 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrFPStack.td +++ b/suite/synctools/tablegen/X86/back/X86InstrFPStack.td @@ -242,7 +242,7 @@ defm MUL : FPBinary_rr; defm DIV : FPBinary_rr; } -// Sets the scheduling resources for the actual NAME#_Fm defintions. +// Sets the scheduling resources for the actual NAME#_Fm definitions. let SchedRW = [WriteFAddLd] in { defm ADD : FPBinary; defm SUB : FPBinary; diff --git a/suite/synctools/tablegen/X86/back/X86InstrSSE.td b/suite/synctools/tablegen/X86/back/X86InstrSSE.td index 910b80636f..54db88114a 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrSSE.td +++ b/suite/synctools/tablegen/X86/back/X86InstrSSE.td @@ -1004,7 +1004,7 @@ def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}", // and/or XMM operand(s). // FIXME: We probably want to match the rm form only when optimizing for -// size, to avoid false depenendecies (see sse_fp_unop_s for details) +// size, to avoid false dependencies (see sse_fp_unop_s for details) multiclass sse12_cvt_sint opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, Operand memop, ComplexPattern mem_cpat, string asm, X86FoldableSchedWrite sched> { @@ -3122,7 +3122,7 @@ def PAUSE : I<0x90, RawFrm, (outs), (ins), let SchedRW = [WriteFence] in { // Load, store, and memory fence -// TODO: As with mfence, we may want to ease the availablity of sfence/lfence +// TODO: As with mfence, we may want to ease the availability of sfence/lfence // to include any 64-bit target. def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>, PS, Requires<[HasSSE1]>; diff --git a/suite/synctools/tablegen/X86/back/X86InstrSystem.td b/suite/synctools/tablegen/X86/back/X86InstrSystem.td index e9dba76f44..c0d51aa3bf 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrSystem.td +++ b/suite/synctools/tablegen/X86/back/X86InstrSystem.td @@ -699,7 +699,7 @@ def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, let Predicates = [In64BitMode, HasRDPID] in { // Due to silly instruction definition, we have to compensate for the - // instruction outputing a 64-bit register. + // instruction outputting a 64-bit register. def : Pat<(int_x86_rdpid), (EXTRACT_SUBREG (RDPID64), sub_32bit)>; } diff --git a/suite/synctools/tablegen/X86/back/X86InstrTSX.td b/suite/synctools/tablegen/X86/back/X86InstrTSX.td index b1fdd18074..8b9f723a41 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrTSX.td +++ b/suite/synctools/tablegen/X86/back/X86InstrTSX.td @@ -32,7 +32,7 @@ def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), "xbegin\t$dst", []>, OpSize32; } -// Psuedo instruction to fake the definition of EAX on the fallback code path. +// Pseudo instruction to fake the definition of EAX on the fallback code path. //let isPseudo = 1, Defs = [EAX] in { //def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; //} diff --git a/suite/synctools/tablegen/X86/back/X86RegisterInfo.td b/suite/synctools/tablegen/X86/back/X86RegisterInfo.td index ee9e7891f9..907d402223 100644 --- a/suite/synctools/tablegen/X86/back/X86RegisterInfo.td +++ b/suite/synctools/tablegen/X86/back/X86RegisterInfo.td @@ -488,7 +488,7 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; -// When RBP is used as a base pointer in a 32-bit addresses environement, +// When RBP is used as a base pointer in a 32-bit addresses environment, // this is also safe to use the full register to access addresses. // Since RBP will never be spilled, stick to a 32 alignment to save // on memory consumption. diff --git a/suite/synctools/tablegen/X86/back/X86Schedule.td b/suite/synctools/tablegen/X86/back/X86Schedule.td index ef9ce94706..6215d58ae1 100644 --- a/suite/synctools/tablegen/X86/back/X86Schedule.td +++ b/suite/synctools/tablegen/X86/back/X86Schedule.td @@ -628,8 +628,8 @@ def SchedWriteFShuffleSizes // Generic Processor Scheduler Models. // IssueWidth is analogous to the number of decode units. Core and its -// descendents, including Nehalem and SandyBridge have 4 decoders. -// Resources beyond the decoder operate on micro-ops and are bufferred +// descendants, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are buffered // so adjacent micro-ops don't directly compete. // // MicroOpBufferSize > 1 indicates that RAW dependencies can be diff --git a/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td b/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td index a7f461c456..daa6fc73cc 100644 --- a/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td +++ b/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td @@ -20,8 +20,8 @@ def AtomModel : SchedMachineModel { let IssueWidth = 2; // Allows 2 instructions per scheduling group. let MicroOpBufferSize = 0; // In-order execution, always hide latency. - let LoadLatency = 3; // Expected cycles, may be overriden. - let HighLatency = 30;// Expected, may be overriden. + let LoadLatency = 3; // Expected cycles, may be overridden. + let HighLatency = 30;// Expected, may be overridden. // On the Atom, the throughput for taken branches is 2 cycles. For small // simple loops, expand by a small factor to hide the backedge cost. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h b/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h index 1190d6061e..e49ac1b6c1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h @@ -190,7 +190,7 @@ class AccelTableBase { }; /// This class holds an abstract representation of an Accelerator Table, -/// consisting of a sequence of buckets, each bucket containint a sequence of +/// consisting of a sequence of buckets, each bucket containing a sequence of /// HashData entries. The class is parameterized by the type of entries it /// holds. The type template parameter also defines the hash function to use for /// hashing names. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h b/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h index c5c2b57486..7c7cb04ca9 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h @@ -39,7 +39,7 @@ class AntiDepBreaker { /// Initialize anti-dep breaking for a new basic block. virtual void StartBlock(MachineBasicBlock *BB) = 0; - /// Identifiy anti-dependencies within a basic-block region and break them by + /// Identify anti-dependencies within a basic-block region and break them by /// renaming registers. Return the number of anti-dependencies broken. virtual unsigned BreakAntiDependencies(const std::vector &SUnits, MachineBasicBlock::iterator Begin, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h b/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h index d911bfd435..40898d8a81 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h @@ -268,7 +268,7 @@ class AsmPrinter : public MachineFunctionPass { void EmitToStreamer(MCStreamer &S, const MCInst &Inst); - /// Emits inital debug location directive. + /// Emits initial debug location directive. void emitInitialRawDwarfLocDirective(const MachineFunction &MF); /// Return the current section we are emitting to. @@ -444,7 +444,7 @@ class AsmPrinter : public MachineFunctionPass { /// Print a general LLVM constant to the .s file. void emitGlobalConstant(const DataLayout &DL, const Constant *CV); - /// Unnamed constant global variables solely contaning a pointer to + /// Unnamed constant global variables solely containing a pointer to /// another globals variable act like a global variable "proxy", or GOT /// equivalents, i.e., it's only used to hold the address of the latter. One /// optimization is to replace accesses to these proxies by using the GOT diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h b/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h index 0b27376289..83e09115e5 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h @@ -447,7 +447,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// Relative lookup table entries consist of 32-bit offsets. /// Do not generate relative lookup tables for large code models - /// in 64-bit achitectures where 32-bit offsets might not be enough. + /// in 64-bit architectures where 32-bit offsets might not be enough. if (TM.getCodeModel() == CodeModel::Medium || TM.getCodeModel() == CodeModel::Large) return false; @@ -2198,7 +2198,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { // The minimal length of the vector is limited by the real length of vector // operations performed on the current platform. That's why several final - // reduction opertions are perfomed on the vectors with the same + // reduction operations are performed on the vectors with the same // architecture-dependent length. ShuffleCost += NumReduxLevels * thisT()->getShuffleCost( TTI::SK_PermuteSingleSrc, Ty, None, 0, Ty); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h index dbc36888fb..5fc32cd9a5 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -409,7 +409,7 @@ template class CodeGenPassBuilder { /// codegen pass pipeline where targets may insert passes. Methods with /// out-of-line standard implementations are major CodeGen stages called by /// addMachinePasses. Some targets may override major stages when inserting - /// passes is insufficient, but maintaining overriden stages is more work. + /// passes is insufficient, but maintaining overridden stages is more work. /// /// addMachineSSAOptimization - Add standard passes that optimize machine @@ -448,11 +448,11 @@ template class CodeGenPassBuilder { /// this target at the current optimization level. void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const; - /// addMachinePasses helper to create the target-selected or overriden + /// addMachinePasses helper to create the target-selected or overridden /// regalloc pass. void addRegAllocPass(AddMachinePass &, bool Optimized) const; - /// Add core register alloator passes which do the actual register assignment + /// Add core register allocator passes which do the actual register assignment /// and rewriting. \returns true if any passes were added. Error addRegAssignmentFast(AddMachinePass &) const; Error addRegAssignmentOptimized(AddMachinePass &) const; @@ -830,7 +830,7 @@ Error CodeGenPassBuilder::addCoreISelPasses( /// with nontrivial configuration or multiple passes are broken out below in /// add%Stage routines. /// -/// Any CodeGenPassBuilder::addXX routine may be overriden by the +/// Any CodeGenPassBuilder::addXX routine may be overridden by the /// Target. The addPre/Post methods with empty header implementations allow /// injecting target-specific fixups just before or after major stages. /// Additionally, targets have the flexibility to change pass order within a @@ -1023,7 +1023,7 @@ void CodeGenPassBuilder::addRegAllocPass(AddMachinePass &addPass, else if (Opt.RegAlloc == RegAllocType::PBQP) addPass(RAPBQPPass()); else - llvm_unreachable("unknonwn register allocator type"); + llvm_unreachable("unknown register allocator type"); } template diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h b/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h index 9cdaedc9e8..7668d76f80 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h @@ -94,7 +94,7 @@ class DFAPacketizer { // packet. The resources are returned as a bitvector of functional units. // // Note that a bundle may be packed in multiple valid ways. This function - // returns one arbitary valid packing. + // returns one arbitrary valid packing. // // Requires setTrackResources(true) to have been called. unsigned getUsedResources(unsigned InstIdx); @@ -179,7 +179,7 @@ class VLIWPacketizerList { return false; } - // Check if it is legal to prune dependece between SUI and SUJ. + // Check if it is legal to prune dependence between SUI and SUJ. virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { return false; } diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h b/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h index 45823b2ba3..c0305b834a 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h @@ -92,7 +92,7 @@ class DebugHandlerBase : public AsmPrinterHandler { /// Maps instruction with label emitted after instruction. DenseMap LabelsAfterInsn; - /// Indentify instructions that are marking the beginning of or + /// Identify instructions that are marking the beginning of or /// ending of a scope. void identifyScopeMarkers(); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h index 03f4f3bf0b..0f1b11b1b1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -560,7 +560,7 @@ class InstructionSelector { /// Return true if MI can obviously be folded into IntoMI. /// MI and IntoMI do not need to be in the same basic blocks, but MI must - /// preceed IntoMI. + /// precede IntoMI. bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const; }; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h index 3cacdc99db..281ca39ccd 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h @@ -161,7 +161,7 @@ class LegacyLegalizerInfo { } /// The setAction calls record the non-size-changing legalization actions - /// to take on specificly-sized types. The SizeChangeStrategy defines what + /// to take on specifically-sized types. The SizeChangeStrategy defines what /// to do when the size of the type needs to be changed to reach a legally /// sized type (i.e., one that was defined through a setAction call). /// e.g. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h index 179f2f07ac..cf4c649b9c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h @@ -82,7 +82,7 @@ class LegalizerHelper { LegalizeResult legalizeInstrStep(MachineInstr &MI, LostDebugLocObserver &LocObserver); - /// Legalize an instruction by emiting a runtime library call instead. + /// Legalize an instruction by emitting a runtime library call instead. LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver); /// Legalize an instruction by reducing the width of the underlying scalar diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index c09c69b062..1e7111cd23 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -945,7 +945,7 @@ class MachineIRBuilder { /// Build and insert instructions to put \p Ops together at the specified p /// Indices to form a larger register. /// - /// If the types of the input registers are uniform and cover the entirity of + /// If the types of the input registers are uniform and cover the entirety of /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF /// followed by a sequence of G_INSERT instructions. /// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h index 45006eecfc..421aa555dc 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h @@ -610,7 +610,7 @@ class RegBankSelect : public MachineFunctionPass { /// Apply \p Mapping to \p MI. \p RepairPts represents the different /// mapping action that need to happen for the mapping to be /// applied. - /// \return True if the mapping was applied sucessfully, false otherwise. + /// \return True if the mapping was applied successfully, false otherwise. bool applyMapping(MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping, SmallVectorImpl &RepairPts); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h index da785406bc..906819bb2c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -40,7 +40,7 @@ class RegisterBankInfo { public: /// Helper struct that represents how a value is partially mapped /// into a register. - /// The StartIdx and Length represent what region of the orginal + /// The StartIdx and Length represent what region of the original /// value this partial mapping covers. /// This can be represented as a Mask of contiguous bit starting /// at StartIdx bit and spanning Length bits. @@ -77,7 +77,7 @@ class RegisterBankInfo { void print(raw_ostream &OS) const; /// Check that the Mask is compatible with the RegBank. - /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask, + /// Indeed, if the RegBank cannot accommodate the "active bits" of the mask, /// there is no way this mapping is valid. /// /// \note This method does not check anything when assertions are disabled. @@ -255,7 +255,7 @@ class RegisterBankInfo { return getID() != InvalidMappingID && OperandsMapping; } - /// Verifiy that this mapping makes sense for \p MI. + /// Verify that this mapping makes sense for \p MI. /// \pre \p MI must be connected to a MachineFunction. /// /// \note This method does not check anything when assertions are disabled. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h b/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h index c2b722e084..f343f2dd72 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h @@ -294,7 +294,7 @@ enum NodeType { /// subtraction. These nodes take three operands: The first two are normal lhs /// and rhs to the add or sub, and the third is a boolean indicating if there /// is an incoming carry. They produce two results: the normal result of the - /// add or sub, and a boolean that indicates if an overflow occured (*not* + /// add or sub, and a boolean that indicates if an overflow occurred (*not* /// flag, because it may be a store to memory, etc.). If the type of the /// boolean is not i1 then the high bits conform to getBooleanContents. SADDO_CARRY, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h b/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h index 9617ba80c1..0366de8ecb 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h @@ -142,7 +142,7 @@ class LexicalScopes { public: LexicalScopes() = default; - /// initialize - Scan machine function and constuct lexical scope nest, resets + /// initialize - Scan machine function and construct lexical scope nest, resets /// the instance if necessary. void initialize(const MachineFunction &); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h index 09ae23bb2c..7de2e42f26 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h @@ -359,7 +359,7 @@ namespace llvm { /// Merge all of the live segments of a specific val# in RHS into this live /// range as the specified value number. The segments in RHS are allowed /// to overlap with segments in the current range, it will replace the - /// value numbers of the overlaped live segments with the specified value + /// value numbers of the overlapped live segments with the specified value /// number. void MergeSegmentsInAsValue(const LiveRange &RHS, VNInfo *LHSValNo); @@ -416,7 +416,7 @@ namespace llvm { } /// getVNInfoBefore - Return the VNInfo that is live up to but not - /// necessarilly including Idx, or NULL. Use this to find the reaching def + /// necessarily including Idx, or NULL. Use this to find the reaching def /// used by an instruction at this SlotIndex position. VNInfo *getVNInfoBefore(SlotIndex Idx) const { const_iterator I = FindSegmentContaining(Idx.getPrevSlot()); @@ -977,7 +977,7 @@ namespace llvm { } /// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a - /// LiveInterval into equivalence clases of connected components. A + /// LiveInterval into equivalence classes of connected components. A /// LiveInterval that has multiple connected components can be broken into /// multiple LiveIntervals. /// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h index fa08166791..22d10bb93a 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // /// \file This file implements the LiveInterval analysis pass. Given some -/// numbering of each the machine instructions (in this implemention depth-first +/// numbering of each the machine instructions (in this implementation depth-first /// order) an interval [i, j) is said to be a live interval for register v if /// there is no instruction with number j' > j such that v is live at j' and /// there is no instruction with number i' < i such that v is live at i'. In diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h b/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h index 99ba1a28c9..710737feff 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h @@ -51,7 +51,7 @@ class LivePhysRegs { RegisterSet LiveRegs; public: - /// Constructs an unitialized set. init() needs to be called to initialize it. + /// Constructs an uninitialized set. init() needs to be called to initialize it. LivePhysRegs() = default; /// Constructs and initializes an empty set. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h index d80522f5bd..7000bfac7d 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h @@ -161,7 +161,7 @@ class LiveRangeEdit : private MachineRegisterInfo::Delegate { /// dead after rematerialization, we still want to keep it for following /// rematerializations. We save the def instruction in DeadRemats, /// and replace the original dst register with a new dummy register so - /// the live range of original dst register can be shrinked normally. + /// the live range of original dst register can be shrunk normally. /// We don't want to allocate phys register for the dummy register, so /// we want to drop it from the NewRegs set. void pop_back() { NewRegs.pop_back(); } diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h index 39a1ec461e..3ef3e6bab4 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h @@ -43,7 +43,7 @@ class LiveRegUnits { /// For a machine instruction \p MI, adds all register units used in /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is /// useful when walking over a range of instructions to track registers - /// used or defined seperately. + /// used or defined separately. static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h b/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h index 93d140cabd..eaa4594d92 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h @@ -33,7 +33,7 @@ class MachineFunction; /// We want to visit every instruction in every basic block in order to update /// it's execution domain or collect clearance information. However, for the /// clearance calculation, we need to know clearances from all predecessors -/// (including any backedges), therfore we need to visit some blocks twice. +/// (including any backedges), therefore we need to visit some blocks twice. /// As an example, consider the following loop. /// /// @@ -57,7 +57,7 @@ class MachineFunction; /// straight-line code, and a small loop, that would be a lot of unnecessary /// work (since only the BBs that are part of the loop require two passes). /// -/// E.g., the naive iteration order for the above exmple is as follows: +/// E.g., the naive iteration order for the above example is as follows: /// Naive: PH A B C D A' B' C' D' /// /// In the optimized approach we avoid processing D twice, because we @@ -80,7 +80,7 @@ class LoopTraversal { MBBInfo() = default; }; using MBBInfoMap = SmallVector; - /// Helps keep track if we proccessed this block and all its predecessors. + /// Helps keep track if we processed this block and all its predecessors. MBBInfoMap MBBInfos; public: diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h b/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h index fb276ff117..12be5ede28 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h @@ -42,7 +42,7 @@ class MIRFormatter { } /// Implement target specific parsing of immediate mnemonics. The mnemonic is - /// dot seperated strings. + /// dot separated strings. virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, StringRef Src, int64_t &Imm, ErrorCallbackType ErrorCallback) const { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h b/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h index 45e30686b6..5e94418d5f 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h @@ -34,7 +34,7 @@ void printMIR(raw_ostream &OS, const MachineFunction &MF); /// you the correct list of successor blocks in most cases except for things /// like jump tables where the basic block references can't easily be found. /// The MIRPRinter will skip printing successors if they match the result of -/// this funciton and the parser will use this function to construct a list if +/// this function and the parser will use this function to construct a list if /// it is missing. void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl &Result, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h b/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h index 2503524ccf..a9638fc3fd 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the supoorting functions for machine level Sample FDO +// This file contains the supporting functions for machine level Sample FDO // loader. This is used in Flow Sensitive SampelFDO. // //===----------------------------------------------------------------------===// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h index 638b6732a5..02a7308d54 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h @@ -787,7 +787,7 @@ class MachineBasicBlock /// \c SkipPseudoOp should be true when it's used in optimizations that /// unlikely hurt profile quality, e.g., without block merging. The default /// value of \c SkipPseudoOp is set to true to maximize code quality in - /// general, with an explict false value passed in in a few places like branch + /// general, with an explicit false value passed in in a few places like branch /// folding and if-conversion to favor profile quality. iterator getFirstNonDebugInstr(bool SkipPseudoOp = true); const_iterator getFirstNonDebugInstr(bool SkipPseudoOp = true) const { @@ -809,7 +809,7 @@ class MachineBasicBlock /// \c SkipPseudoOp should be true when it's used in optimizations that /// unlikely hurt profile quality, e.g., without block merging. The default /// value of \c SkipPseudoOp is set to true to maximize code quality in - /// general, with an explict false value passed in in a few places like branch + /// general, with an explicit false value passed in in a few places like branch /// folding and if-conversion to favor profile quality. iterator getLastNonDebugInstr(bool SkipPseudoOp = true); const_iterator getLastNonDebugInstr(bool SkipPseudoOp = true) const { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h index 7e7e0a9c47..06f9ee3abb 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This pass is used to evaluate branch probabilties on machine basic blocks. +// This pass is used to evaluate branch probabilities on machine basic blocks. // //===----------------------------------------------------------------------===// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h index 864ca73180..0105c14101 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h @@ -148,7 +148,7 @@ class MachineFrameInfo { /// register allocator. bool isStatepointSpillSlot = false; - /// Identifier for stack memory type analagous to address space. If this is + /// Identifier for stack memory type analogous to address space. If this is /// non-0, the meaning is target defined. Offsets cannot be directly /// compared between objects with different stack IDs. The object may not /// necessarily reside in the same contiguous memory block as other stack diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h index c4767a51b0..a41fcb4072 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h @@ -906,7 +906,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// into \p MBB before \p InsertBefore. /// /// Note: Does not perform target specific adjustments; consider using - /// TargetInstrInfo::duplicate() intead. + /// TargetInstrInfo::duplicate() instead. MachineInstr & cloneMachineInstrBundle(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, @@ -1020,7 +1020,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Returns a reference to a list of cfi instructions in the function's /// prologue. Used to construct frame maps for debug and exception handling - /// comsumers. + /// consumers. const std::vector &getFrameInstructions() const { return FrameInstructions; } diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h index 2893e138a9..357dba79f4 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h @@ -96,7 +96,7 @@ class MachineInstr FmContract = 1 << 8, // Instruction supports Fast math // contraction operations like fma. FmAfn = 1 << 9, // Instruction may map to Fast math - // instrinsic approximation. + // intrinsic approximation. FmReassoc = 1 << 10, // Instruction supports Fast math // reassociation of operand order. NoUWrap = 1 << 11, // Instruction supports binary operator @@ -488,7 +488,7 @@ class MachineInstr /// Returns the opcode of this MachineInstr. unsigned getOpcode() const { return MCID->Opcode; } - /// Retuns the total number of operands. + /// Returns the total number of operands. unsigned getNumOperands() const { return NumOperands; } /// Returns the total number of operands which are debug locations. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h index c07606e893..b7569acf4d 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h @@ -64,14 +64,14 @@ class MachineModuleInfoImpl { virtual ~MachineModuleInfoImpl(); protected: - /// Return the entries from a DenseMap in a deterministic sorted orer. + /// Return the entries from a DenseMap in a deterministic sorted order. /// Clears the map. static SymbolListTy getSortedStubs(DenseMap&); }; //===----------------------------------------------------------------------===// /// This class contains meta information specific to a module. Queries can be -/// made by different debugging and exception handling schemes and reformated +/// made by different debugging and exception handling schemes and reformatted /// for specific use. /// class MachineModuleInfo { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h index eded28183e..9bc946a54e 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h @@ -249,7 +249,7 @@ class MachineOperand { void clearParent() { ParentMI = nullptr; } /// Print a subreg index operand. - /// MO_Immediate operands can also be subreg idices. If it's the case, the + /// MO_Immediate operands can also be subreg indices. If it's the case, the /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be /// called to check this. static void printSubRegIdx(raw_ostream &OS, uint64_t Index, @@ -296,8 +296,8 @@ class MachineOperand { /// \param TiedOperandIdx - if we need to print register ties this needs to /// provide the index of the tied register. If not, it will be ignored. /// \param TRI - provide more target-specific information to the printer. - /// Unlike the previous function, this one will not try and get the - /// information from it's parent. + /// Unlike the previous function, this one will not try to get the + /// information from its parent. /// \param IntrinsicInfo - same as \p TRI. void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint, Optional OpIdx, bool PrintDef, bool IsStandalone, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h index 75b8a89c81..1f1dddba02 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h @@ -117,7 +117,7 @@ extern template class PassManager; /// `PreservedAnalyses run(MachineFunction &, /// MachineFunctionAnalysisManager &)` /// But this interface wouldn't be executed. It is just a placeholder -/// to satisfy the pass manager type-erased inteface. This +/// to satisfy the pass manager type-erased interface. This /// special-casing of machine module pass is due to its limited use /// cases and the unnecessary complexity it may bring to the machine /// pass manager. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h index 7e7fa57d80..1237005fa2 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h @@ -17,7 +17,7 @@ // // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa, // A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Proceedings of the 1996 -// Conference on Parallel Architectures and Compilation Techiniques. +// Conference on Parallel Architectures and Compilation Techniques. // // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J. // Llosa, E. Ayguade, A. Gonzalez, M. Valero, and J. Eckhardt. In IEEE @@ -480,7 +480,7 @@ class ResourceManager { /// This class represents the scheduled code. The main data structure is a /// map from scheduled cycle to instructions. During scheduling, the /// data structure explicitly represents all stages/iterations. When -/// the algorithm finshes, the schedule is collapsed into a single stage, +/// the algorithm finishes, the schedule is collapsed into a single stage, /// which represents instructions from different loop iterations. /// /// The SMS algorithm allows negative values for cycles, so the first cycle diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h index 267c4b595e..fab296c2a1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h @@ -174,7 +174,7 @@ class MachineSchedRegistry class ScheduleDAGMI; /// Define a generic scheduling policy for targets that don't provide their own -/// MachineSchedStrategy. This can be overriden for each scheduling region +/// MachineSchedStrategy. This can be overridden for each scheduling region /// before building the DAG. struct MachineSchedPolicy { // Allow the scheduler to disable register pressure tracking. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h b/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h index e8dbf49994..dfe8f0f517 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h @@ -17,7 +17,7 @@ // // A schedule is, for every instruction in a block, a Cycle and a Stage. Note // that we only support single-block loops, so "block" and "loop" can be used -// interchangably. +// interchangeably. // // The Cycle of an instruction defines a partial order of the instructions in // the remapped loop. Instructions within a cycle must not consume the output diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h b/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h index 5c802802a8..5077ae8377 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h @@ -352,7 +352,7 @@ namespace PBQP { /// Lock this graph to the given solver instance in preparation /// for running the solver. This method will call solver.handleAddNode for /// each node in the graph, and handleAddEdge for each edge, to give the - /// solver an opportunity to set up any requried metadata. + /// solver an opportunity to set up any required metadata. void setSolver(SolverT &S) { assert(!Solver && "Solver already set. Call unsetSolver()."); Solver = &S; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h b/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h index 5144548a27..68e913576c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h @@ -138,7 +138,7 @@ class ReachingDefAnalysis : public MachineFunctionPass { void traverse(); /// Provides the instruction id of the closest reaching def instruction of - /// PhysReg that reaches MI, relative to the begining of MI's basic block. + /// PhysReg that reaches MI, relative to the beginning of MI's basic block. int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const; /// Return whether A and B use the same def of PhysReg. @@ -179,7 +179,7 @@ class ReachingDefAnalysis : public MachineFunctionPass { bool isRegDefinedAfter(MachineInstr *MI, MCRegister PhysReg) const; /// Provides the clearance - the number of instructions since the closest - /// reaching def instuction of PhysReg that reaches MI. + /// reaching def instruction of PhysReg that reaches MI. int getClearance(MachineInstr *MI, MCRegister PhysReg) const; /// Provides the uses, in the same block as MI, of register that MI defines. @@ -271,7 +271,7 @@ class ReachingDefAnalysis : public MachineFunctionPass { MachineInstr *getInstFromId(MachineBasicBlock *MBB, int InstId) const; /// Provides the instruction of the closest reaching def instruction of - /// PhysReg that reaches MI, relative to the begining of MI's basic block. + /// PhysReg that reaches MI, relative to the beginning of MI's basic block. MachineInstr *getReachingLocalMIDef(MachineInstr *MI, MCRegister PhysReg) const; }; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h b/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h index 1deeb4d415..32da3e032b 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h @@ -440,7 +440,7 @@ class RegPressureTracker { /// RegisterOperands of the instruction. void advance(const RegisterOperands &RegOpers); - /// Finalize the region boundaries and recored live ins and live outs. + /// Finalize the region boundaries and record live ins and live outs. void closeRegion(); /// Initialize the LiveThru pressure set based on the untied defs found in diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h b/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h index 7c0ebe7191..461b57f2af 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h @@ -1,4 +1,4 @@ -//===- ReplaceWithVeclib.h - Replace vector instrinsics with veclib calls -===// +//===- ReplaceWithVeclib.h - Replace vector intrinsics with veclib calls -===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h index 4f348c9fea..6f140da1ef 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h @@ -1425,7 +1425,7 @@ class SelectionDAG { /// Expand the specified \c ISD::VACOPY node as the Legalize pass would. SDValue expandVACopy(SDNode *Node); - /// Returs an GlobalAddress of the function from the current module with + /// Returns an GlobalAddress of the function from the current module with /// name matching the given ExternalSymbol. Additionally can provide the /// matched function. /// Panics the function doesn't exists. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h index 04c6b50197..40d7c4d6d1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1761,7 +1761,7 @@ class FrameIndexSDNode : public SDNode { }; /// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate -/// the offet and size that are started/ended in the underlying FrameIndex. +/// the offset and size that are started/ended in the underlying FrameIndex. class LifetimeSDNode : public SDNode { friend class SelectionDAG; int64_t Size; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h b/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h index 928d7cc6cc..c2f374d689 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h @@ -381,7 +381,7 @@ class StackMaps { /// Record the locations of the operands of the provided instruction in a /// record keyed by the provided label. For instructions w/AnyReg calling /// convention the return register is also recorded if requested. For - /// STACKMAP, and PATCHPOINT the label is expected to immediately *preceed* + /// STACKMAP, and PATCHPOINT the label is expected to immediately *precede* /// lowering of the MI to MCInsts. For STATEPOINT, it expected to /// immediately *follow*. It's not clear this difference was intentional, /// but it exists today. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h b/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h index daaa27f72d..4ff43bfcd4 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h @@ -65,7 +65,7 @@ class TailDuplicator { /// probabilities when modifying the CFG. /// @param LayoutMode - When true, don't use the existing layout to make /// decisions. - /// @param TailDupSize - Maxmimum size of blocks to tail-duplicate. Zero + /// @param TailDupSize - Maximum size of blocks to tail-duplicate. Zero /// default implies using the command line value TailDupSize. void initMF(MachineFunction &MF, bool PreRegAlloc, const MachineBranchProbabilityInfo *MBPI, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h index 411811d08c..b937f2f284 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h @@ -140,7 +140,7 @@ class TargetInstrInfo : public MCInstrInfo { /// set, this hook lets the target specify whether the instruction is actually /// trivially rematerializable, taking into consideration its operands. This /// predicate must return false if the instruction has any side effects other - /// than producing a value, or if it requres any address registers that are + /// than producing a value, or if it requires any address registers that are /// not always available. /// Requirements must be check as stated in isTriviallyReMaterializable() . virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h index 049dee25dd..981cfe648c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h @@ -734,10 +734,10 @@ class TargetLoweringBase { return true; } - /// Should we tranform the IR-optimal check for whether given truncation + /// Should we transform the IR-optimal check for whether given truncation /// down into KeptBits would be truncating or not: /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits) - /// Into it's more traditional form: + /// Into its more traditional form: /// ((%x << C) a>> C) dstcond %x /// Return true if we should transform. /// Return false if there is no preference. @@ -822,8 +822,8 @@ class TargetLoweringBase { virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const; - /// Return the ValueType for comparison libcalls. Comparions libcalls include - /// floating point comparion calls, and Ordered/Unordered check calls on + /// Return the ValueType for comparison libcalls. Comparison libcalls include + /// floating point comparison calls, and Ordered/Unordered check calls on /// floating point numbers. virtual MVT::SimpleValueType getCmpLibcallReturnType() const; @@ -3269,7 +3269,7 @@ class TargetLoweringBase { bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const; - /// Replace/modify any TargetFrameIndex operands with a targte-dependent + /// Replace/modify any TargetFrameIndex operands with a target-dependent /// sequence of memory operands that is recognized by PrologEpilogInserter. MachineBasicBlock *emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const; @@ -4672,12 +4672,12 @@ class TargetLowering : public TargetLoweringBase { unsigned Scale, SelectionDAG &DAG) const; /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion - /// always suceeds and populates the Result and Overflow arguments. + /// always succeeds and populates the Result and Overflow arguments. void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const; /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion - /// always suceeds and populates the Result and Overflow arguments. + /// always succeeds and populates the Result and Overflow arguments. void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const; @@ -4774,7 +4774,7 @@ class TargetLowering : public TargetLoweringBase { // combiner can fold the new nodes. SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const; - /// Give targets the chance to reduce the number of distinct addresing modes. + /// Give targets the chance to reduce the number of distinct addressing modes. ISD::MemIndexType getCanonicalIndexType(ISD::MemIndexType IndexType, EVT MemVT, SDValue Offsets) const; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h index ff23cffdcd..6f04a1b713 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h @@ -40,11 +40,11 @@ using legacy::PassManagerBase; /// /// The PassConfig API prefers dealing with IDs because they are safer and more /// efficient. IDs decouple configuration from instantiation. This way, when a -/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to +/// pass is overridden, it isn't unnecessarily instantiated. It is also unsafe to /// refer to a Pass pointer after adding it to a pass manager, which deletes /// redundant pass instances. /// -/// However, it is convient to directly instantiate target passes with +/// However, it is convenient to directly instantiate target passes with /// non-default ctors. These often don't have a registered PassInfo. Rather than /// force all target passes to implement the pass registry boilerplate, allow /// the PassConfig API to handle either type. @@ -209,7 +209,7 @@ class TargetPassConfig : public ImmutablePass { bool getOptimizeRegAlloc() const; /// Return true if the default global register allocator is in use and - /// has not be overriden on the command line with '-regalloc=...' + /// has not be overridden on the command line with '-regalloc=...' bool usingDefaultRegAlloc() const; /// High level function that adds all passes necessary to go from llvm IR @@ -349,7 +349,7 @@ class TargetPassConfig : public ImmutablePass { /// codegen pass pipeline where targets may insert passes. Methods with /// out-of-line standard implementations are major CodeGen stages called by /// addMachinePasses. Some targets may override major stages when inserting - /// passes is insufficient, but maintaining overriden stages is more work. + /// passes is insufficient, but maintaining overridden stages is more work. /// /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM @@ -454,7 +454,7 @@ class TargetPassConfig : public ImmutablePass { /// pass. void addPass(Pass *P); - /// addMachinePasses helper to create the target-selected or overriden + /// addMachinePasses helper to create the target-selected or overridden /// regalloc pass. virtual FunctionPass *createRegAllocPass(bool Optimized); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h index c3b842052e..04a1252512 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h @@ -680,7 +680,7 @@ class TargetRegisterInfo : public MCRegisterInfo { } /// Return the register cost table index. This implementation is sufficient - /// for most architectures and can be overriden by targets in case there are + /// for most architectures and can be overridden by targets in case there are /// multiple cost values associated with each register. virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const { return 0; @@ -996,7 +996,7 @@ class TargetRegisterInfo : public MCRegisterInfo { return false; } - /// This method must be overriden to eliminate abstract frame indices from + /// This method must be overridden to eliminate abstract frame indices from /// instructions which may use them. The instruction referenced by the /// iterator contains an MO_FrameIndex operand which must be eliminated by /// this method. This method may modify or replace the specified instruction, @@ -1170,7 +1170,7 @@ class BitMaskClassIterator { const unsigned NumRegClasses; /// Base index of CurrentChunk. /// In other words, the number of bit we read to get at the - /// beginning of that chunck. + /// beginning of that chunk. unsigned Base = 0; /// Adjust base index of CurrentChunk. /// Base index + how many bit we read within CurrentChunk. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h b/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h index a39f04f6db..e0ed86e97e 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h @@ -165,7 +165,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy { CriticalPathLength = DAG->getBBSize() / SchedModel->getIssueWidth(); if (DAG->getBBSize() < 50) // We divide by two as a cheap and simple heuristic to reduce the - // critcal path length, which increases the priority of using the graph + // critical path length, which increases the priority of using the graph // height/depth in the scheduler's cost computation. CriticalPathLength >>= 1; else { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h b/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h index 42e8d294a6..639368fe5e 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h @@ -189,7 +189,7 @@ class TargetInstrInfo; return Virt2StackSlotMap[virtReg.id()]; } - /// create a mapping for the specifed virtual register to + /// create a mapping for the specified virtual register to /// the next available stack slot int assignVirt2StackSlot(Register virtReg); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h index f098316de7..ddfb49a2a3 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h @@ -32,7 +32,7 @@ class InvokeInst; class MachineBasicBlock; class MCSymbol; -// The following structs respresent the .xdata tables for various +// The following structs represent the .xdata tables for various // Windows-related EH personalities. using MBBOrBasicBlock = PointerUnion; diff --git a/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td b/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td index e40f40f74c..d47c12483a 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td +++ b/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td @@ -40,7 +40,7 @@ class DirectiveLanguage { // Generate include and macro to enable LLVM BitmaskEnum. bit enableBitmaskEnumInNamespace = false; - // Header file included in the implementation code generated. Ususally the + // Header file included in the implementation code generated. Usually the // output file of the declaration code generation. Can be left blank. string includeHeader = ""; @@ -108,7 +108,7 @@ class VersionedClause { // Actual clause. Clause clause = c; - // Mininum version number where this clause is valid. + // Minimum version number where this clause is valid. int minVersion = min; // Maximum version number where this clause is valid. @@ -117,7 +117,7 @@ class VersionedClause { // Information about a specific directive. class Directive { - // Name of the directive. Can be composite directive sepearted by whitespace. + // Name of the directive. Can be composite directive separated by whitespace. string name = d; // Define an alternative name return in getDirectiveName diff --git a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h index bee90281e0..695eca784f 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h +++ b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// \file /// -/// This file defines constans and helpers used when dealing with OpenMP. +/// This file defines constants and helpers used when dealing with OpenMP. /// //===----------------------------------------------------------------------===// @@ -62,7 +62,7 @@ enum class DefaultKind { #include "llvm/Frontend/OpenMP/OMPKinds.def" /// IDs for all omp runtime library ident_t flag encodings (see -/// their defintion in openmp/runtime/src/kmp.h). +/// their definition in openmp/runtime/src/kmp.h). enum class IdentFlag { #define OMP_IDENT_FLAG(Enum, Str, Value) Enum = Value, #include "llvm/Frontend/OpenMP/OMPKinds.def" diff --git a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h index 544f698655..ca81b94b9c 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h +++ b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h @@ -114,8 +114,8 @@ bool isValidTraitPropertyForTraitSetAndSelector(TraitProperty Property, TraitSet Set); /// Variant match information describes the required traits and how they are -/// scored (via the ScoresMap). In addition, the required consturct nesting is -/// decribed as well. +/// scored (via the ScoresMap). In addition, the required construct nesting is +/// described as well. struct VariantMatchInfo { /// Add the trait \p Property to the required trait set. \p RawString is the /// string we parsed and derived \p Property from. If \p Score is not null, it diff --git a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h index f60debe841..dd3e197b3c 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -176,7 +176,7 @@ class OpenMPIRBuilder { /// /// \param Loc The location where the directive was encountered. /// \param IfCondition The evaluated 'if' clause expression, if any. - /// \param CanceledDirective The kind of directive that is cancled. + /// \param CanceledDirective The kind of directive that is canceled. /// /// \returns The insertion point after the barrier. InsertPointTy createCancel(const LocationDescription &Loc, Value *IfCondition, @@ -392,7 +392,7 @@ class OpenMPIRBuilder { /// \param AllocaIP An insertion point for Alloca instructions usable in the /// preheader of the loop. /// \param SchedType Type of scheduling to be passed to the init function. - /// \param NeedsBarrier Indicates whether a barrier must be insterted after + /// \param NeedsBarrier Indicates whether a barrier must be inserted after /// the loop. /// \param Chunk The size of loop chunk considered as a unit when /// scheduling. If \p nullptr, defaults to 1. @@ -418,7 +418,7 @@ class OpenMPIRBuilder { /// \param CLI A descriptor of the canonical loop to workshare. /// \param AllocaIP An insertion point for Alloca instructions usable in the /// preheader of the loop. - /// \param NeedsBarrier Indicates whether a barrier must be insterted after + /// \param NeedsBarrier Indicates whether a barrier must be inserted after /// the loop. /// /// \returns Point where to insert code after the workshare construct. @@ -699,7 +699,7 @@ class OpenMPIRBuilder { /// Generate control flow and cleanup for cancellation. /// /// \param CancelFlag Flag indicating if the cancellation is performed. - /// \param CanceledDirective The kind of directive that is cancled. + /// \param CanceledDirective The kind of directive that is canceled. /// \param ExitCB Extra code to be generated in the exit block. void emitCancelationCheckImpl(Value *CancelFlag, omp::Directive CanceledDirective, @@ -873,7 +873,7 @@ class OpenMPIRBuilder { /// /// \param Loc The insert and source location description. /// \param BodyGenCB Callback that will generate the region code. - /// \param FiniCB Callback to finialize variable copies. + /// \param FiniCB Callback to finalize variable copies. /// /// \returns The insertion position *after* the masked. InsertPointTy createMasked(const LocationDescription &Loc, @@ -1008,7 +1008,7 @@ class OpenMPIRBuilder { /// \param Loc The insert and source location description. /// \param InteropVar variable to be allocated /// \param InteropType type of interop operation - /// \param Device devide to which offloading will occur + /// \param Device device to which offloading will occur /// \param NumDependences number of dependence variables /// \param DependenceAddress pointer to dependence variables /// \param HaveNowaitClause does nowait clause exist @@ -1025,7 +1025,7 @@ class OpenMPIRBuilder { /// /// \param Loc The insert and source location description. /// \param InteropVar variable to be allocated - /// \param Device devide to which offloading will occur + /// \param Device device to which offloading will occur /// \param NumDependences number of dependence variables /// \param DependenceAddress pointer to dependence variables /// \param HaveNowaitClause does nowait clause exist @@ -1041,7 +1041,7 @@ class OpenMPIRBuilder { /// /// \param Loc The insert and source location description. /// \param InteropVar variable to be allocated - /// \param Device devide to which offloading will occur + /// \param Device device to which offloading will occur /// \param NumDependences number of dependence variables /// \param DependenceAddress pointer to dependence variables /// \param HaveNowaitClause does nowait clause exist @@ -1206,7 +1206,7 @@ class OpenMPIRBuilder { /// \param AO The required atomic ordering /// \param AK The OpenMP atomic operation kind used. /// - /// \returns wether a flush was emitted or not + /// \returns whether a flush was emitted or not bool checkAndEmitFlushAfterAtomic(const LocationDescription &Loc, AtomicOrdering AO, AtomicKind AK); @@ -1388,7 +1388,7 @@ class OpenMPIRBuilder { /// such that the CanonicalLoopInfo itself can be side-effect free. /// /// Keep in mind that CanonicalLoopInfo is meant to only describe a repeated -/// execution of a loop body that satifies these constraints. It does NOT +/// execution of a loop body that satisfies these constraints. It does NOT /// represent arbitrary SESE regions that happen to contain a loop. Do not use /// CanonicalLoopInfo for such purposes. /// @@ -1425,11 +1425,11 @@ class OpenMPIRBuilder { /// Latch to guarantee that there is only a single edge to the latch. It would /// make loop transformations easier to not needing to consider multiple /// predecessors of the latch (See redirectAllPredecessorsTo) and would give us -/// an equivalant to PreheaderIP, AfterIP and BodyIP for inserting code that +/// an equivalent to PreheaderIP, AfterIP and BodyIP for inserting code that /// executes after each body iteration. /// /// There must be no loop-carried dependencies through llvm::Values. This is -/// equivalant to that the Latch has no PHINode and the Header's only PHINode is +/// equivalent to that the Latch has no PHINode and the Header's only PHINode is /// for the induction variable. /// /// All code in Header, Cond, Latch and Exit (plus the terminator of the @@ -1487,7 +1487,7 @@ class CanonicalLoopInfo { public: /// Returns whether this object currently represents the IR of a loop. If /// returning false, it may have been consumed by a loop transformation or not - /// been intialized. Do not use in this case; + /// been initialized. Do not use in this case; bool isValid() const { return Header; } /// The preheader ensures that there is only a single edge entering the loop. diff --git a/suite/synctools/tablegen/include/llvm/IR/Attributes.h b/suite/synctools/tablegen/include/llvm/IR/Attributes.h index 74b60f1e3d..b75917822f 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Attributes.h +++ b/suite/synctools/tablegen/include/llvm/IR/Attributes.h @@ -72,7 +72,7 @@ class Attribute { None, ///< No attributes have been set #define GET_ATTR_ENUM #include "llvm/IR/Attributes.inc" - EndAttrKinds, ///< Sentinal value useful for loops + EndAttrKinds, ///< Sentinel value useful for loops EmptyKey, ///< Use as Empty key for DenseMap of AttrKind TombstoneKey, ///< Use as Tombstone key for DenseMap of AttrKind }; @@ -665,7 +665,7 @@ class AttributeList { return removeAttributesAtIndex(C, ArgNo + FirstArgIndex); } - /// Replace the type contained by attribute \p AttrKind at index \p ArgNo wih + /// Replace the type contained by attribute \p AttrKind at index \p ArgNo with /// \p ReplacementTy, preserving all other attributes. LLVM_NODISCARD AttributeList replaceAttributeTypeAtIndex( LLVMContext &C, unsigned ArgNo, Attribute::AttrKind Kind, diff --git a/suite/synctools/tablegen/include/llvm/IR/CallingConv.h b/suite/synctools/tablegen/include/llvm/IR/CallingConv.h index fd28542465..ece864e731 100644 --- a/suite/synctools/tablegen/include/llvm/IR/CallingConv.h +++ b/suite/synctools/tablegen/include/llvm/IR/CallingConv.h @@ -75,13 +75,13 @@ namespace CallingConv { // CXX_FAST_TLS - Calling convention for access functions. CXX_FAST_TLS = 17, - /// Tail - This calling convention attemps to make calls as fast as + /// Tail - This calling convention attempts to make calls as fast as /// possible while guaranteeing that tail call optimization can always /// be performed. Tail = 18, /// Special calling convention on Windows for calling the Control - /// Guard Check ICall funtion. The function takes exactly one argument + /// Guard Check ICall function. The function takes exactly one argument /// (address of the target function) passed in the first argument register, /// and has no return value. All register values are preserved. CFGuard_Check = 19, diff --git a/suite/synctools/tablegen/include/llvm/IR/Constants.h b/suite/synctools/tablegen/include/llvm/IR/Constants.h index fb884912b3..e23ecd8e4c 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Constants.h +++ b/suite/synctools/tablegen/include/llvm/IR/Constants.h @@ -986,7 +986,7 @@ class ConstantExpr : public Constant { public: // Static methods to construct a ConstantExpr of different kinds. Note that - // these methods may return a object that is not an instance of the + // these methods may return an object that is not an instance of the // ConstantExpr class, because they will attempt to fold the constant // expression into something simpler if possible. diff --git a/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h b/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h index fc461fc3f4..69949b96f7 100644 --- a/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h +++ b/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h @@ -222,7 +222,7 @@ namespace llvm { /// Create debugging information entry for a qualified /// type, e.g. 'const int'. - /// \param Tag Tag identifing type, e.g. dwarf::TAG_volatile_type + /// \param Tag Tag identifying type, e.g. dwarf::TAG_volatile_type /// \param FromTy Base Type. DIDerivedType *createQualifiedType(unsigned Tag, DIType *FromTy); diff --git a/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h b/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h index 9656917906..4dc3d5d2e0 100644 --- a/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h +++ b/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h @@ -2235,7 +2235,7 @@ DILocation::cloneWithDiscriminator(unsigned Discriminator) const { DIScope *Scope = getScope(); // Skip all parent DILexicalBlockFile that already have a discriminator // assigned. We do not want to have nested DILexicalBlockFiles that have - // mutliple discriminators because only the leaf DILexicalBlockFile's + // multiple discriminators because only the leaf DILexicalBlockFile's // dominator will be used. for (auto *LBF = dyn_cast(Scope); LBF && LBF->getDiscriminator() != 0; diff --git a/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h b/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h index 55e5e59758..5edcc678a3 100644 --- a/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h +++ b/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h @@ -18,8 +18,8 @@ namespace llvm { class DiagnosticInfo; /// This is the base class for diagnostic handling in LLVM. -/// The handleDiagnostics method must be overriden by the subclasses to handle -/// diagnostic. The *RemarkEnabled methods can be overriden to control +/// The handleDiagnostics method must be overridden by the subclasses to handle +/// diagnostic. The *RemarkEnabled methods can be overridden to control /// which remarks are enabled. struct DiagnosticHandler { void *DiagnosticContext = nullptr; diff --git a/suite/synctools/tablegen/include/llvm/IR/Function.h b/suite/synctools/tablegen/include/llvm/IR/Function.h index 90095cd1bc..0eb3910c1b 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Function.h +++ b/suite/synctools/tablegen/include/llvm/IR/Function.h @@ -516,7 +516,7 @@ class LLVM_EXTERNAL_VISIBILITY Function : public GlobalObject, addFnAttr(Attribute::WriteOnly); } - /// Determine if the call can access memmory only using pointers based + /// Determine if the call can access memory only using pointers based /// on its arguments. bool onlyAccessesArgMemory() const { return hasFnAttribute(Attribute::ArgMemOnly); diff --git a/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h b/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h index 4fa8e3a8dc..d42fcf5534 100644 --- a/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h +++ b/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h @@ -121,7 +121,7 @@ class GCStrategy { /// Subclasses of GCStrategy are made available for use during compilation by /// adding them to the global GCRegistry. This can done either within the -/// LLVM source tree or via a loadable plugin. An example registeration +/// LLVM source tree or via a loadable plugin. An example registration /// would be: /// static GCRegistry::Add X("custom-name", /// "my custom supper fancy gc strategy"); diff --git a/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h b/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h index 1818f2a8f3..d7236ca0a2 100644 --- a/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h +++ b/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h @@ -414,7 +414,7 @@ class GlobalValue : public Constant { return !mayBeDerefined(); } - /// Return true if this global has an exact defintion. + /// Return true if this global has an exact definition. bool hasExactDefinition() const { // While this computes exactly the same thing as // isStrongDefinitionForLinker, the intended uses are different. This diff --git a/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h b/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h index e772964fcc..d3123dba6b 100644 --- a/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h +++ b/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h @@ -180,7 +180,7 @@ class GlobalVariable : public GlobalObject, public ilist_node { /// Attach a DIGlobalVariableExpression. void addDebugInfo(DIGlobalVariableExpression *GV); - /// Fill the vector with all debug info attachements. + /// Fill the vector with all debug info attachments. void getDebugInfo(SmallVectorImpl &GVs) const; /// Add attribute to this global. diff --git a/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h b/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h index a178975996..2968a89527 100644 --- a/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h +++ b/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h @@ -439,7 +439,7 @@ class IRBuilderBase { /// /// Make a new global variable with an initializer that has array of i8 type /// filled in with the null terminated string value specified. The new global - /// variable will be marked mergable with any others of the same contents. If + /// variable will be marked mergeable with any others of the same contents. If /// Name is specified, it is the name of the global variable created. /// /// If no module is given via \p M, it is take from the insertion point basic diff --git a/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h b/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h index 585129904d..359a4e6e4b 100644 --- a/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h +++ b/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h @@ -200,7 +200,7 @@ class InstVisitor { RetTy visitCatchPadInst(CatchPadInst &I) { DELEGATE(FuncletPadInst); } RetTy visitFreezeInst(FreezeInst &I) { DELEGATE(Instruction); } - // Handle the special instrinsic instruction classes. + // Handle the special intrinsic instruction classes. RetTy visitDbgDeclareInst(DbgDeclareInst &I) { DELEGATE(DbgVariableIntrinsic);} RetTy visitDbgValueInst(DbgValueInst &I) { DELEGATE(DbgVariableIntrinsic);} RetTy visitDbgVariableIntrinsic(DbgVariableIntrinsic &I) diff --git a/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h b/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h index a73285b484..6a1f5c67ed 100644 --- a/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h +++ b/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h @@ -621,7 +621,7 @@ class CastInst : public UnaryInstruction { const Value *Val, ///< The value to cast bool SrcIsSigned, ///< Whether to treat the source as signed Type *Ty, ///< The Type to which the value should be casted - bool DstIsSigned ///< Whether to treate the dest. as signed + bool DstIsSigned ///< Whether to treat the dest. as signed ); /// There are several places where we need to know if a cast instruction @@ -1838,7 +1838,7 @@ class CallBase : public Instruction { } void setOnlyWritesMemory() { addFnAttr(Attribute::WriteOnly); } - /// Determine if the call can access memmory only using pointers based + /// Determine if the call can access memory only using pointers based /// on its arguments. bool onlyAccessesArgMemory() const { return hasFnAttr(Attribute::ArgMemOnly); diff --git a/suite/synctools/tablegen/include/llvm/IR/Instruction.h b/suite/synctools/tablegen/include/llvm/IR/Instruction.h index 1937ffd36f..a5d364f0bc 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Instruction.h +++ b/suite/synctools/tablegen/include/llvm/IR/Instruction.h @@ -55,7 +55,7 @@ class Instruction : public User, using OpaqueField = Bitfield::Element; // Template alias so that all Instruction storing alignment use the same - // definiton. + // definition. // Valid alignments are powers of two from 2^0 to 2^MaxAlignmentExponent = // 2^32. We store them as Log2(Alignment), so we need 6 bits to encode the 33 // possible values. diff --git a/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h b/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h index 2ff48380ac..fea543b795 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h +++ b/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h @@ -236,7 +236,7 @@ namespace Intrinsic { /// This method returns true on error. bool matchIntrinsicVarArg(bool isVarArg, ArrayRef &Infos); - /// Gets the type arguments of an intrinsic call by matching type contraints + /// Gets the type arguments of an intrinsic call by matching type constraints /// specified by the .td file. The overloaded types are pushed into the /// AgTys vector. /// diff --git a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td index c5d266eb57..e709c77ee5 100644 --- a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td @@ -976,7 +976,7 @@ def int_amdgcn_buffer_store : AMDGPUBufferStore; // it is const 0. A struct intrinsic with constant 0 index is different to the // corresponding raw intrinsic on gfx9+ because the behavior of bound checking // and swizzling changes depending on whether idxen is set in the instruction. -// These new instrinsics also keep the offset and soffset arguments separate as +// These new intrinsics also keep the offset and soffset arguments separate as // they behave differently in bounds checking and swizzling. class AMDGPURawBufferLoad : Intrinsic < [data_ty], diff --git a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td index a424847575..ab5f6023fa 100644 --- a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td +++ b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td @@ -1158,7 +1158,7 @@ defm int_arm_mve_vabav: MVEPredicated< [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], llvm_anyvector_ty>; -// The following 3 instrinsics are MVE vector reductions with two vector +// The following 3 intrinsics are MVE vector reductions with two vector // operands. // The first 3 operands are boolean flags (must be compile-time constants): // * unsigned - the instruction operates on vectors of unsigned values and diff --git a/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h b/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h index 446bcecf1c..4250c94ef5 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h +++ b/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h @@ -233,7 +233,7 @@ class LLVMContext { std::unique_ptr MainRemarkStreamer); /// The "LLVM remark streamer" used by LLVM to serialize remark diagnostics - /// comming from IR and MIR passes. + /// coming from IR and MIR passes. /// /// If it does not exist, diagnostics are not saved in a file but only emitted /// via the diagnostic handler. diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h index b3a4820ba0..70c9e418d7 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h +++ b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h @@ -63,7 +63,7 @@ class PassManager : public PassManagerBase { private: /// PassManagerImpl_New is the actual class. PassManager is just the - /// wraper to publish simple pass manager interface + /// wrapper to publish simple pass manager interface PassManagerImpl *PM; }; diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h index caba0ee223..62351e34ed 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h +++ b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h @@ -36,7 +36,7 @@ // derive from another pass manager. // // PassManager and FunctionPassManager are two top-level pass manager that -// represents the external interface of this entire pass manager infrastucture. +// represents the external interface of this entire pass manager infrastructure. // // Important classes : // @@ -276,7 +276,7 @@ class PMTopLevelManager { // all allocated nodes in one fell swoop. SpecificBumpPtrAllocator AUFoldingSetNodeAllocator; - // Maps from a pass to it's associated entry in UniqueAnalysisUsages. Does + // Maps from a pass to its associated entry in UniqueAnalysisUsages. Does // not own the storage associated with either key or value.. DenseMap AnUsageMap; @@ -305,7 +305,7 @@ class PMDataManager { /// Augment AvailableAnalysis by adding analysis made available by pass P. void recordAvailableAnalysis(Pass *P); - /// verifyPreservedAnalysis -- Verify analysis presreved by pass P. + /// verifyPreservedAnalysis -- Verify analysis preserved by pass P. void verifyPreservedAnalysis(Pass *P); /// Remove Analysis that is not preserved by the pass diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h index c33b9fc404..103bfab74c 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h +++ b/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h @@ -51,7 +51,7 @@ class PassNameParser : public PassRegistrationListener, enumeratePasses(); } - // ignorablePassImpl - Can be overriden in subclasses to refine the list of + // ignorablePassImpl - Can be overridden in subclasses to refine the list of // which passes we want to include. // virtual bool ignorablePassImpl(const PassInfo *P) const { return false; } diff --git a/suite/synctools/tablegen/include/llvm/IR/Metadata.h b/suite/synctools/tablegen/include/llvm/IR/Metadata.h index 7965884990..eeeeb90550 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Metadata.h +++ b/suite/synctools/tablegen/include/llvm/IR/Metadata.h @@ -169,7 +169,7 @@ inline raw_ostream &operator<<(raw_ostream &OS, const Metadata &MD) { /// Metadata wrapper in the Value hierarchy. /// /// A member of the \a Value hierarchy to represent a reference to metadata. -/// This allows, e.g., instrinsics to have metadata as operands. +/// This allows, e.g., intrinsics to have metadata as operands. /// /// Notably, this is the only thing in either hierarchy that is allowed to /// reference \a LocalAsMetadata. diff --git a/suite/synctools/tablegen/include/llvm/IR/PassManager.h b/suite/synctools/tablegen/include/llvm/IR/PassManager.h index 12f9052a9e..6c5e8f3616 100644 --- a/suite/synctools/tablegen/include/llvm/IR/PassManager.h +++ b/suite/synctools/tablegen/include/llvm/IR/PassManager.h @@ -680,7 +680,7 @@ template class AnalysisManager { /// cyclic dependencies between analysis results. /// /// This returns true if the given analysis's result is invalid. Any - /// dependecies on it will become invalid as a result. + /// dependencies on it will become invalid as a result. template bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA) { using ResultModelT = @@ -944,7 +944,7 @@ class InnerAnalysisManagerProxy Result(Result &&Arg) : InnerAM(std::move(Arg.InnerAM)) { // We have to null out the analysis manager in the moved-from state - // because we are taking ownership of the responsibilty to clear the + // because we are taking ownership of the responsibility to clear the // analysis state. Arg.InnerAM = nullptr; } @@ -962,7 +962,7 @@ class InnerAnalysisManagerProxy Result &operator=(Result &&RHS) { InnerAM = RHS.InnerAM; // We have to null out the analysis manager in the moved-from state - // because we are taking ownership of the responsibilty to clear the + // because we are taking ownership of the responsibility to clear the // analysis state. RHS.InnerAM = nullptr; return *this; diff --git a/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h b/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h index f55f521681..e2b1fea407 100644 --- a/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h +++ b/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h @@ -123,7 +123,7 @@ template struct AnalysisResultConcept { virtual ~AnalysisResultConcept() = default; - /// Method to try and mark a result as invalid. + /// Method to try to mark a result as invalid. /// /// When the outer analysis manager detects a change in some underlying /// unit of the IR, it will call this method on all of the results cached. diff --git a/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h b/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h index 4bb6bb8d4a..dfd61e8fba 100644 --- a/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h +++ b/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h @@ -83,7 +83,7 @@ class ProfileSummary { /// Return summary information as metadata. Metadata *getMD(LLVMContext &Context, bool AddPartialField = true, bool AddPartialProfileRatioField = true); - /// Construct profile summary from metdata. + /// Construct profile summary from metadata. static ProfileSummary *getFromMD(Metadata *MD); const SummaryEntryVector &getDetailedSummary() { return DetailedSummary; } uint32_t getNumFunctions() const { return NumFunctions; } diff --git a/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h b/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h index 1d6b10d9a7..02c57239e8 100644 --- a/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h +++ b/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h @@ -26,7 +26,7 @@ template class SmallPtrSetImpl; /// The given instruction \p I contains given constant expression \p CE as one /// of its operands, possibly nested within constant expression trees. Convert -/// all reachable paths from contant expression operands of \p I to \p CE into +/// all reachable paths from constant expression operands of \p I to \p CE into /// corresponding instructions, insert them before \p I, update operands of \p I /// accordingly, and if required, return all such converted instructions at /// \p Insts. diff --git a/suite/synctools/tablegen/include/llvm/IR/Statepoint.h b/suite/synctools/tablegen/include/llvm/IR/Statepoint.h index da9c732ad8..61f3f748b7 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Statepoint.h +++ b/suite/synctools/tablegen/include/llvm/IR/Statepoint.h @@ -129,7 +129,7 @@ class GCStatepointInst : public CallBase { /// Return the number of arguments to the underlying call. size_t actual_arg_size() const { return getNumCallArgs(); } - /// Return an iterator to the begining of the arguments to the underlying call + /// Return an iterator to the beginning of the arguments to the underlying call const_op_iterator actual_arg_begin() const { assert(CallArgsBeginPos <= (int)arg_size()); return arg_begin() + CallArgsBeginPos; @@ -177,7 +177,7 @@ class GCStatepointInst : public CallBase { return make_range(deopt_begin(), deopt_end()); } - /// Returns an iterator to the begining of the argument range describing gc + /// Returns an iterator to the beginning of the argument range describing gc /// values for the statepoint. const_op_iterator gc_args_begin() const { if (auto Opt = getOperandBundle(LLVMContext::OB_gc_live)) diff --git a/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h b/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h index d7377398b9..229dc73357 100644 --- a/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h +++ b/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h @@ -101,7 +101,7 @@ class TrackingMDRef { /// Typed tracking ref. /// -/// Track refererences of a particular type. It's useful to use this for \a +/// Track references of a particular type. It's useful to use this for \a /// MDNode and \a ValueAsMetadata. template class TypedTrackingMDRef { TrackingMDRef Ref; diff --git a/suite/synctools/tablegen/include/llvm/IR/Value.h b/suite/synctools/tablegen/include/llvm/IR/Value.h index fc2ed00d77..bab3149870 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Value.h +++ b/suite/synctools/tablegen/include/llvm/IR/Value.h @@ -242,7 +242,7 @@ class Value { /// /// This is useful when you just want to print 'int %reg126', not the /// instruction that generated it. If you specify a Module for context, then - /// even constanst get pretty-printed; for example, the type of a null + /// even constants get pretty-printed; for example, the type of a null /// pointer is printed symbolically. /// @{ void printAsOperand(raw_ostream &O, bool PrintType = true, @@ -479,8 +479,8 @@ class Value { /// Remove every uses that can safely be removed. /// /// This will remove for example uses in llvm.assume. - /// This should be used when performing want to perform a tranformation but - /// some Droppable uses pervent it. + /// This should be used when performing want to perform a transformation but + /// some Droppable uses prevent it. /// This function optionally takes a filter to only remove some droppable /// uses. void dropDroppableUses(llvm::function_ref ShouldDrop = diff --git a/suite/synctools/tablegen/include/llvm/IR/ValueMap.h b/suite/synctools/tablegen/include/llvm/IR/ValueMap.h index 67f275cc06..fb3f002b00 100644 --- a/suite/synctools/tablegen/include/llvm/IR/ValueMap.h +++ b/suite/synctools/tablegen/include/llvm/IR/ValueMap.h @@ -104,7 +104,7 @@ class ValueMap { : Map(NumInitBuckets), Data() {} explicit ValueMap(const ExtraData &Data, unsigned NumInitBuckets = 64) : Map(NumInitBuckets), Data(Data) {} - // ValueMap can't be copied nor moved, beucase the callbacks store pointer + // ValueMap can't be copied nor moved, because the callbacks store pointer // to it. ValueMap(const ValueMap &) = delete; ValueMap(ValueMap &&) = delete; diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h b/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h index e1f45019b1..4e1d9030f9 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h @@ -739,7 +739,7 @@ getLineCoverageStats(const coverage::CoverageData &CD) { return make_range(Begin, End); } -// Coverage mappping data (V2) has the following layout: +// Coverage mapping data (V2) has the following layout: // IPSK_covmap: // [CoverageMapFileHeader] // [ArrayStart] @@ -749,7 +749,7 @@ getLineCoverageStats(const coverage::CoverageData &CD) { // [ArrayEnd] // [Encoded Filenames and Region Mapping Data] // -// Coverage mappping data (V3) has the following layout: +// Coverage mapping data (V3) has the following layout: // IPSK_covmap: // [CoverageMapFileHeader] // [Encoded Filenames] diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h b/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h index a416eb2890..746a7875aa 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h @@ -102,7 +102,7 @@ inline StringRef getInstrProfNamesVarName() { return "__llvm_prf_nm"; } -/// Return the name of a covarage mapping variable (internal linkage) +/// Return the name of a coverage mapping variable (internal linkage) /// for each instrumented source module. Such variables are allocated /// in the __llvm_covmap section. inline StringRef getCoverageMappingVarName() { @@ -485,7 +485,7 @@ class InstrProfSymtab { /// indicates if this is called from LTO optimization passes. Error create(Module &M, bool InLTO = false); - /// Create InstrProfSymtab from a set of names iteratable from + /// Create InstrProfSymtab from a set of names iterable from /// \p IterRange. This interface is used by IndexedProfReader. template Error create(const NameIterRange &IterRange); @@ -536,7 +536,7 @@ class InstrProfSymtab { inline Function *getFunction(uint64_t FuncMD5Hash); /// Return the function's original assembly name by stripping off - /// the prefix attached (to symbols with priviate linkage). For + /// the prefix attached (to symbols with private linkage). For /// global functions, it returns the same string as getFuncName. inline StringRef getOrigFuncName(uint64_t FuncMD5Hash); @@ -1038,7 +1038,7 @@ struct Summary { uint64_t Cutoff; ///< The required percentile of total execution count. uint64_t MinBlockCount; ///< The minimum execution count for this percentile. - uint64_t NumBlocks; ///< Number of blocks >= the minumum execution count. + uint64_t NumBlocks; ///< Number of blocks >= the minimum execution count. }; // The field kind enumerator to assigned value mapping should remain // unchanged when a new kind is added or an old kind gets deleted in @@ -1061,7 +1061,7 @@ struct Summary { NumKinds = TotalBlockCount + 1 }; - // The number of summmary fields following the summary header. + // The number of summary fields following the summary header. uint64_t NumSummaryFields; // The number of Cutoff Entries (Summary::Entry) following summary fields. uint64_t NumCutoffEntries; diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h index bad2139fe8..50ae26c568 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h @@ -1157,7 +1157,7 @@ template class SampleSorter { SamplesWithLocList V; }; -/// SampleContextTrimmer impelements helper functions to trim, merge cold +/// SampleContextTrimmer implements helper functions to trim, merge cold /// context profiles. It also supports context profile canonicalization to make /// sure ProfileMap's key is consistent with FunctionSample's name/context. class SampleContextTrimmer { @@ -1167,8 +1167,8 @@ class SampleContextTrimmer { // should only be effective when TrimColdContext is true. On top of // TrimColdContext, TrimBaseProfileOnly can be used to specify to trim all // cold profiles or only cold base profiles. Trimming base profiles only is - // mainly to honor the preinliner decsion. Note that when MergeColdContext is - // true, preinliner decsion is not honored anyway so TrimBaseProfileOnly will + // mainly to honor the preinliner decision. Note that when MergeColdContext is + // true, preinliner decision is not honored anyway so TrimBaseProfileOnly will // be ignored. void trimAndMergeColdContextProfiles(uint64_t ColdCountThreshold, bool TrimColdContext, diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h index a2caca246d..db9ce345c4 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h @@ -167,7 +167,7 @@ // The minimum number of samples required to reach the target // CUTOFF. // NUM_COUNTS (uint64_t) -// Number of samples to get to the desrired percentile. +// Number of samples to get to the desired percentile. // // NAME TABLE // SIZE (uint32_t) @@ -306,7 +306,7 @@ class SampleProfileReaderItaniumRemapper { std::unique_ptr Remappings; // Map remapping key to the name in the profile. By looking up the // key in the remapper, a given new name can be mapped to the - // cannonical name using the NameMap. + // canonical name using the NameMap. DenseMap NameMap; // The Reader the remapper is servicing. SampleProfileReader &Reader; @@ -379,7 +379,7 @@ class SampleProfileReader { return sampleprof_error::success; } - /// The implementaion to read sample profiles from the associated file. + /// The implementation to read sample profiles from the associated file. virtual std::error_code readImpl() = 0; /// Print the profile for \p FContext on stream \p OS. diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h index 42decd2552..b4a2da3a7b 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h @@ -277,7 +277,7 @@ class SampleProfileWriterExtBinaryBase : public SampleProfileWriterBinary { std::error_code writeProfileSymbolListSection(); SectionLayout SecLayout = DefaultLayout; - // Specifiy the order of sections in section header table. Note + // Specify the order of sections in section header table. Note // the order of sections in SecHdrTable may be different that the // order in SectionHdrLayout. sample Reader will follow the order // in SectionHdrLayout to read each section. diff --git a/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td b/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td index 4859cf6b57..6416afa3a7 100644 --- a/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td +++ b/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td @@ -73,7 +73,7 @@ class GIDefKindWithArgs; /// Declare a root node. There must be at least one of these in every combine /// rule. /// TODO: The plan is to elide `root` definitions and determine it from the DAG -/// itself with an overide for situations where the usual determination +/// itself with an override for situations where the usual determination /// is incorrect. def root : GIDefKind; diff --git a/suite/synctools/tablegen/include/llvm/Target/Target.td b/suite/synctools/tablegen/include/llvm/Target/Target.td index 85dabebcb1..21af476254 100644 --- a/suite/synctools/tablegen/include/llvm/Target/Target.td +++ b/suite/synctools/tablegen/include/llvm/Target/Target.td @@ -642,8 +642,8 @@ class Instruction : InstructionEncoding { /// Should generate helper functions that help you to map a logical operand's /// index to the underlying MIOperand's index. - /// In most architectures logical operand indicies are equal to - /// MIOperand indicies, but for some CISC architectures, a logical operand + /// In most architectures logical operand indices are equal to + /// MIOperand indices, but for some CISC architectures, a logical operand /// might be consist of multiple MIOperand (e.g. a logical operand that /// uses complex address mode). bit UseLogicalOperandMappings = false; diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h b/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h index 392ee4334c..ff62907ff9 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h +++ b/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h @@ -139,7 +139,7 @@ class TargetLoweringObjectFile : public MCObjectFileInfo { const Function &F) const; /// Targets should implement this method to assign a section to globals with - /// an explicit section specfied. The implementation of this method can + /// an explicit section specified. The implementation of this method can /// assume that GO->hasSection() is true. virtual MCSection * getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind, diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h b/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h index acfb265a9f..9048d84301 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h +++ b/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h @@ -153,7 +153,7 @@ class TargetMachine { return nullptr; } - /// Parse out the target's MachineFunctionInfo from the YAML reprsentation. + /// Parse out the target's MachineFunctionInfo from the YAML representation. virtual bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, @@ -439,13 +439,13 @@ class LLVMTargetMachine : public TargetMachine { raw_pwrite_stream &, raw_pwrite_stream *, CodeGenFileType, CGPassBuilderOption, PassInstrumentationCallbacks *) { - return make_error("buildCodeGenPipeline is not overriden", + return make_error("buildCodeGenPipeline is not overridden", inconvertibleErrorCode()); } virtual std::pair getPassNameFromLegacyName(StringRef) { llvm_unreachable( - "getPassNameFromLegacyName parseMIRPipeline is not overriden"); + "getPassNameFromLegacyName parseMIRPipeline is not overridden"); } /// Add passes to the specified pass manager to get machine code emitted with diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h b/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h index a636c48228..19968c83e0 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h +++ b/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h @@ -353,7 +353,7 @@ namespace llvm { /// If greater than 0, override TargetLoweringBase::PrefLoopAlignment. unsigned LoopAlignment = 0; - /// FloatABIType - This setting is set by -float-abi=xxx option is specfied + /// FloatABIType - This setting is set by -float-abi=xxx option is specified /// on the command line. This setting may either be Default, Soft, or Hard. /// Default selects the target's default behavior. Soft selects the ABI for /// software floating point, but does not indicate that FP hardware may not diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td b/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td index 3bc467fbbf..b312618fe3 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td +++ b/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td @@ -67,7 +67,7 @@ def instregex; // coarse grained instruction cost model. Default values for the // properties are defined in MCSchedModel. A value of "-1" in the // target description's SchedMachineModel indicates that the property -// is not overriden by the target. +// is not overridden by the target. // // Target hooks allow subtargets to associate LoadLatency and // HighLatency with groups of opcodes. @@ -491,7 +491,7 @@ class SchedAlias { // // This is what happens for example on AMD processors (at least from Bulldozer // onwards), where AL and AH are not treated as independent from AX, and AX is -// not treated as independent from EAX. A write to AL has an implicity false +// not treated as independent from EAX. A write to AL has an implicitly false // dependency on the last write to EAX (or a portion of EAX). As a consequence, // a write to AL cannot go in parallel with a write to AH. // diff --git a/suite/test_mc.sh b/suite/test_mc.sh index 5430f5f544..b4552aedad 100755 --- a/suite/test_mc.sh +++ b/suite/test_mc.sh @@ -8,7 +8,7 @@ find MC/ -name *.cs | ./test_mc.py -# To test just one architecture, specify the corresponsing dir: +# To test just one architecture, specify the corresponding dir: # $ find MC/X86 -name *.cs | ./test_mc.py # To test just one input file, run test_mc.py with that file: diff --git a/utils.c b/utils.c index c97902e5b6..bd5fcf5612 100644 --- a/utils.c +++ b/utils.c @@ -111,7 +111,7 @@ uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes) /// @brief Appends the string @p src to the string @p str. @p src is put to lower case. /// @param str The string to append to. -/// @param str_size The lengt of @p str +/// @param str_size The length of @p str /// @param src The string to append. void append_to_str_lower(char *str, size_t str_size, const char *src) { char *dest = strchr(str, '\0'); diff --git a/windowsce/COMPILE.md b/windowsce/COMPILE.md index b41dcb7bac..6ed5abc4cd 100644 --- a/windowsce/COMPILE.md +++ b/windowsce/COMPILE.md @@ -10,7 +10,7 @@ We support the following scenario regarding the build machine: - Build running on Microsoft Windows. - The C Software Develepment Kit of the target Windows CE **device** installed. - Only for Windows CE 7: - - C compiler toolchain installed, targetting **Windows Embedded Compact 7** on **ARMv7**. We recommend the toolchain provided with [Windows Embedded Compact 7 toolkit](https://msdn.microsoft.com/en-us/library/jj200349%28v=winembedded.70%29.aspx), as the toolchain originally provided with **Visual Studio 2008** is relatively old. + - C compiler toolchain installed, targeting **Windows Embedded Compact 7** on **ARMv7**. We recommend the toolchain provided with [Windows Embedded Compact 7 toolkit](https://msdn.microsoft.com/en-us/library/jj200349%28v=winembedded.70%29.aspx), as the toolchain originally provided with **Visual Studio 2008** is relatively old. Before building Capstone for Windows CE 7 (respectively, Windows CE 8), the build script `windowsce/make_windowsce7-armv7.bat` (respectively, `windowsce/make_windowsce8-armv7.bat`) needs to be modified. The variables specified in the rest of this section are set in this script file.