ARM T2 encoding lsl #imm bug

[pzread]

Hi,
Capstone correctly outputs this T2 encoding instruction (thumb mode, detail enabled

ldr.w r3, [r2, r3, lsl #2]

But the <cs_arm_op>.mem.shift.type of the second operand = ARM_SFT_INVALID, which is wrong.

I found that in printT2AddrModeSoRegOperand at arch/ARM/ARMInstPrinter.c

line 2094:    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
line 2095:    MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;

It seems like
MI->flat_insn->detail->arm.op_count - 1 should be MI->flat_insn->detail->arm.op_count

[aquynh]

On Sat, Feb 14, 2015 at 11:09 PM, PZ Read notifications@github.com wrote:

Hi,
Capstone correct output below T2 encoding intruction (thumb mode

ldr.w r3, [r2, r3, lsl #2]

But the <cs_arm_op>.mem.shift.type of the second operand =
ARM_SFT_INVALID, which is wrong.

I found that in printT2AddrModeSoRegOperand at arch/ARM/ARMInstPrinter.c

line 2094: MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
line 2095: MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = ShAmt;

It seems like
MI->flat_insn->detail->arm.op_count - 1 should be
MI->flat_insn->detail->arm.op_count

can you provide the input (hexcode) that triggers the problem, so i can
test it?

thanks.

[pzread]

sorry, I forget it
here it is
\x52\xF8\x23\x30

[aquynh]

this issue was fixed in the next branch with this commit 706b808

this fix will not be ported back to 3.x version because it breaks the API, so please use the next branch (which will released as 4.0 in the future).

thanks.