From 5f9edb312123f94397972cf27bc796693128265b Mon Sep 17 00:00:00 2001 From: Changqing Jing Date: Thu, 9 Jan 2025 17:09:49 +0800 Subject: [PATCH] add tricore tc1.8 instructions: div64 div64.u rem64 rem64.u --- llvm/lib/Target/TriCore/TriCoreInstrInfo.td | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/TriCore/TriCoreInstrInfo.td b/llvm/lib/Target/TriCore/TriCoreInstrInfo.td index 7af2a325c53a..37b86d7e8517 100644 --- a/llvm/lib/Target/TriCore/TriCoreInstrInfo.td +++ b/llvm/lib/Target/TriCore/TriCoreInstrInfo.td @@ -815,6 +815,12 @@ multiclass mI_U_RR_Eab op1, bits<8> op2, bits<8> op3, bits<8> op4, def _U_rr # posfix : IRR_dab; } +multiclass mI_U_RR_Eab_n op1, bits<8> op2, bits<8> op3, bits<8> op4, bits<2> n, + string asmstr, string posfix = "", RegisterClass RC1=RD, RegisterClass RC2=RD> { + def _rr # posfix : IRR_dab_n; + def _U_rr # posfix : IRR_dab_n; +} + multiclass mIU_RR_Eab op1, bits<8> op2, bits<8> op3, bits<8> op4, string asmstr, string posfix = ""> { def _rr # posfix : IRR_dab; @@ -831,7 +837,9 @@ defm _B: mIU_RR_Eab ; defm _H: mIU_RR_Eab ; } -defm DIV : mI_U_RR_Eab<0x4B, 0x20, 0x4B, 0x21, "div">, Requires<[HasV160_UP]>; +defm DIV : mI_U_RR_Eab_n<0x4B, 0x20, 0x4B, 0x21, 0x1, "div">, Requires<[HasV160_UP]>; +defm DIV64 : mI_U_RR_Eab_n<0x4B, 0x20, 0x4B, 0x21, 0x2, "div64", "", RE, RE>, Requires<[HasV180_UP]>; +defm REM64 : mI_U_RR_Eab_n<0x4B, 0x34, 0x4B, 0x35, 0x2, "rem64", "", RE, RE>, Requires<[HasV180_UP]>; defm DVINIT : mI_DVINIT_<0x4F, 0x00, 0x01, 0x04, 0x05, 0x02, 0x03, "dvinit", "_v110">, NsRequires<[HasV110]>; defm DVINIT : mI_DVINIT_<0x4B, 0x1A, 0x0A, 0x5A, 0x4A, 0x3A, 0x2A, "dvinit">, Requires<[HasV120_UP]>;