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I noted in your pull request for OSVVM that you run tests by saying:
- name: Test Rand
run: orbit test --tb Demo_Rand --target gsim -- --std=08
Let me point out a couple of things:
this is quite verbose for running just one thing.
you have mixed your tool to run with a test case. You need to separate the simulator from the test case as this is awkward if you need to test against multiple simulators.
running a set of tests often requires additional files that must be compiled before this.
VHDL supports libraries. To keep different test harnesses separate, I recommend using libraries.
OSVVM requires conditionals based on tool, tool version, variable settings.
What do you do for test case artifact management - creating a simulator transcript, managing test output files? In particular some methodologies such as OSVVM produce yaml output files that get translated to HTML by the scripting.
how do you manage two test cases producing test output files that have the same name?
How do you support conditionals? OSVVM requires conditionals to support different tools, tool versions, and settings.
How do you handle grouping tests into test suites?
is building the design and/or running the test cases in any way hierarchical?
You can certainly solve some of this in YAML or other format, however, tests create output. Managing and post processing these may be methodology specific and likely require the methodologies runner.
Even building RTL designs is going to eventually require some sort of conditional support for variations of clock managers for the different FPGAs.
The text was updated successfully, but these errors were encountered:
I noted in your pull request for OSVVM that you run tests by saying:
Let me point out a couple of things:
You can certainly solve some of this in YAML or other format, however, tests create output. Managing and post processing these may be methodology specific and likely require the methodologies runner.
Even building RTL designs is going to eventually require some sort of conditional support for variations of clock managers for the different FPGAs.
The text was updated successfully, but these errors were encountered: