diff --git a/.github/scripts/utils.sh b/.github/scripts/utils.sh
index 24bd83242..05d8691df 100644
--- a/.github/scripts/utils.sh
+++ b/.github/scripts/utils.sh
@@ -32,8 +32,8 @@ wait_for_phrase () {
fi
# Wait for the phrase
- DEADLINE=$((${EPOCHSECONDS} + 30))
- while [ ${EPOCHSECONDS} -lt ${DEADLINE} ]
+ DEADLINE=$(($(date +%s) + 30))
+ while [ $(date +%s) -lt ${DEADLINE} ]
do
# Check for the phrase
grep "$2" "$1" >/dev/null
diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash
index 069318d80..ca18b5af7 100644
--- a/.github/workflow_metadata/pr_hash
+++ b/.github/workflow_metadata/pr_hash
@@ -1 +1 @@
-6104519ceefcd79a47c8c890b053f79f50e15d8213ab0685984df75f95b1273d5eff69ea0dc07cd2d53536d9ed52f88a
\ No newline at end of file
+d1f7aaef6d9d5747a0c833193c02f1ed0c01a5ae581d028e1c415520a50ea8573ad30c65b490d78f2ee4f797ecd9345e
\ No newline at end of file
diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp
index 6a7b5c155..a5f913756 100644
--- a/.github/workflow_metadata/pr_timestamp
+++ b/.github/workflow_metadata/pr_timestamp
@@ -1 +1 @@
-1732036724
\ No newline at end of file
+1732134556
\ No newline at end of file
diff --git a/docs/CaliptraIntegrationSpecification.md b/docs/CaliptraIntegrationSpecification.md
index a57c0c23c..0da6238e6 100644
--- a/docs/CaliptraIntegrationSpecification.md
+++ b/docs/CaliptraIntegrationSpecification.md
@@ -63,8 +63,7 @@ The following table describes integration parameters.
| **Defines** | **Defines file** | **Description** |
| :--------- | :--------- | :--------- |
| CALIPTRA_INTERNAL_TRNG | config_defines.svh | Defining this enables the internal TRNG source. |
-| CALIPTRA_INTERNAL_UART | config_defines.svh | Defining this enables the internal UART. |
-| CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. |
+| CALIPTRA_MODE_SUBSYSTEM | config_defines.svh | Defining this enables Caliptra to operate in subsystem mode. This includes features such as the debug unlock flow, AXI DMA (for recovery flow), subsystem level straps, among other capabilites. See [Caliptra Subsystem Architectural Flows](https://github.com/chipsalliance/Caliptra/blob/main/doc/Caliptra.md#caliptra-subsystem-architectural-flows) for more details |
| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). USER_ICG replaces the clock gating module, CALIPTRA_ICG, defined in [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. |
| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the USER_ICG macro) to be used in place of the native Caliptra clock gate module. |
| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in the RISC-V core. USER_EC_RV_ICG replaces the clock gating module, TEC_RV_ICG, defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. |
@@ -150,12 +149,25 @@ The following tables describe the interface signals.
| jtag_trst_n | 1 | input | Asynchronous assertion
Synchronous deassertion to jtag_tck | |
| jtag_tdo | 1 | output | Synchronous to jtag_tck | |
-*Table 10: UART interface*
-
-| Signal name | Width | Driver | Synchronous (as viewed from Caliptra’s boundary) | Description |
-| :--------- | :--------- | :--------- | :--------- | :--------- |
-| uart_tx | 1 | output | | UART transmit pin |
-| uart_rx | 1 | input | | UART receive pin |
+*Table 10: Subsystem Straps and Control*
+
+| Signal name | Width | Driver | Synchronous (as viewed from Caliptra’s boundary) | Description |
+| :---------- | :--------- | :--------- | :----------------------------------------------- | :--------- |
+| strap_ss_caliptra_base_addr | 64 | Input Strap | Synchronous to clk | |
+| strap_ss_mci_base_addr | 64 | Input Strap | Synchronous to clk | |
+| strap_ss_recovery_ifc_base_addr | 64 | Input Strap | Synchronous to clk | |
+| strap_ss_otp_fc_base_addr | 64 | Input Strap | Synchronous to clk | |
+| strap_ss_uds_seed_base_addr | 64 | Input Strap | Synchronous to clk | |
+| strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset | 32 | Input Strap | Synchronous to clk | |
+| strap_ss_num_of_prod_debug_unlock_auth_pk_hashes | 32 | Input Strap | Synchronous to clk | |
+| strap_ss_strap_generic_0 | 32 | Input Strap | Synchronous to clk | |
+| strap_ss_strap_generic_1 | 32 | Input Strap | Synchronous to clk | |
+| strap_ss_strap_generic_2 | 32 | Input Strap | Synchronous to clk | |
+| strap_ss_strap_generic_3 | 32 | Input Strap | Synchronous to clk | |
+| ss_debug_intent | 1 | Input Strap | Synchronous to clk | Sample on cold reset. Used in Subsystem mode only. Indicates that the SoC is in debug mode and a user intends to request unlock of debug mode through the TAP mailbox. In Passive mode, integrators shall tie this input to 0. |
+| ss_dbg_manuf_enable | 1 | Output | Synchronous to clk | |
+| ss_soc_dbg_unlock_level | 64 | Output | Synchronous to clk | |
+| ss_generic_fw_exec_ctrl | 128 | Output | Synchronous to clk | |
*Table 11: Security and miscellaneous*
@@ -228,6 +240,7 @@ Caliptra firmware internally has the capability to force release the mailbox bas
### Straps
Straps are signal inputs to Caliptra that are sampled once on reset exit, and the latched value persists throughout the remaining uptime of the system. Straps are sampled on either caliptra pwrgood signal deassertion or cptra\_noncore\_rst\_b deassertion – refer to interface table for list of straps.
+In 2.0, Caliptra adds support for numerous Subsystem-level straps. These straps are initialized on cold boot to the value from the external port, but may also be rewritten by the SoC firmware at any time prior to CPTRA_FUSE_WR_DONE being set. Once written and locked, the values of these straps persist until a cold reset.
### Obfuscation key
@@ -247,11 +260,11 @@ SoC must ensure that there are no SCAN cells on the flops that latch this key in
## Late binding interface signals
-The interface signals GENERIC\_INPUT\_WIRES and GENERIC\_OUTPUT\_WIRES are placeholders on the SoC interface reserved for late binding features. This may include any feature that is required for correct operation of the design in the final integrated SoC and that may not be accommodated through existing interface signaling (such as the mailbox).
+The interface signals GENERIC\_INPUT\_WIRES, GENERIC\_OUTPUT\_WIRES, and strap\_ss\_strap\_generic\_N are placeholders on the SoC interface reserved for late binding features. This may include any feature that is required for correct operation of the design in the final integrated SoC and that may not be accommodated through existing interface signaling (such as the mailbox).
-While these late binding interface pins are generic in nature until assigned a function, integrators must not define non-standard use cases for these pins. Defining standard use cases ensures that the security posture of Caliptra in the final implementation is not degraded relative to the consortium design intent. Bits in GENERIC\_INPUT\_WIRES that don't have a function defined in Caliptra must be tied to a 0-value. These undefined input bits shall not be connected to any flip flops (which would allow run-time transitions on the value).
+While these late binding interface pins are generic in nature until assigned a function, integrators must not define non-standard use cases for these pins. Defining standard use cases ensures that the security posture of Caliptra in the final implementation is not degraded relative to the consortium design intent. Bits in GENERIC\_INPUT\_WIRES and strap\_ss\_strap\_generic\_N that don't have a function defined in Caliptra must be tied to a 0-value. These undefined input bits shall not be connected to any flip flops (which would allow run-time transitions on the value).
-Each wire connects to a register in the SoC Interface register bank through which communication to the internal microprocessor may be facilitated. Each signal is 64 bits in size.
+Each wire connects to a register in the SoC Interface register bank through which communication to the internal microprocessor may be facilitated. Each of the generic wire signals is 64 bits in size. The size of the generic strap is indicated in Table 10.
Activity on any bit of the GENERIC\_INPUT\_WIRES triggers a notification interrupt to the microcontroller indicating a bit toggle.
@@ -514,7 +527,7 @@ The following memories are exported:
* Instruction Closely-Coupled Memory (ICCM)
* Data Closely Coupled Memory (DCCM)
-Table 4 indicates the signals contained in the memory interface. Direction is relative to the exported memory wrapper that is instantiated outside of the Caliptra subsystem (that is, from the testbench perspective).
+Table 8 indicates the signals contained in the memory interface. Direction is relative to the exported memory wrapper that is instantiated outside of the Caliptra subsystem (that is, from the testbench perspective).
## SRAM timing behavior
* [Writes] Input wren signal is asserted simultaneously with input data and address. Input data is stored at the input address 1 clock cycle later.
diff --git a/src/integration/rtl/caliptra_reg.h b/src/integration/rtl/caliptra_reg.h
index a7d0303db..293c4b42f 100644
--- a/src/integration/rtl/caliptra_reg.h
+++ b/src/integration/rtl/caliptra_reg.h
@@ -5075,6 +5075,10 @@
#define MBOX_CSR_MBOX_UNLOCK (0x20)
#define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0)
#define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (0x1)
+#define CLP_MBOX_CSR_TAP_MODE (0x30020024)
+#define MBOX_CSR_TAP_MODE (0x24)
+#define MBOX_CSR_TAP_MODE_ENABLED_LOW (0)
+#define MBOX_CSR_TAP_MODE_ENABLED_MASK (0x1)
#define CLP_SHA512_ACC_CSR_BASE_ADDR (0x30021000)
#define CLP_SHA512_ACC_CSR_LOCK (0x30021000)
#define SHA512_ACC_CSR_LOCK (0x0)
@@ -5478,6 +5482,8 @@
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (0x4)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3)
#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (0x8)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (0xfffffff0)
#define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (0x30030004)
#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (0x4)
#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0)
@@ -5486,6 +5492,8 @@
#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (0x2)
#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2)
#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (0x4)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3)
+#define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (0xfffffff8)
#define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (0x30030008)
#define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (0x8)
#define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (0x3003000c)
@@ -5520,8 +5528,8 @@
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (0x1000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (0xe000000)
-#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
-#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (0x10000000)
+#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
+#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (0x10000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (0x20000000)
#define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
@@ -5652,14 +5660,12 @@
#define SOC_IFC_REG_CPTRA_HW_CONFIG (0xe0)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (0x1)
-#define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW (1)
-#define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK (0x2)
-#define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_LOW (2)
-#define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (0x4)
-#define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3)
-#define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK (0x8)
+#define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1)
+#define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (0xe)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4)
#define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10)
+#define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5)
+#define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (0x20)
#define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0x300300e4)
#define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (0xe4)
#define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0)
@@ -5716,6 +5722,42 @@
#define SOC_IFC_REG_CPTRA_RSVD_REG_0 (0x120)
#define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1 (0x30030124)
#define SOC_IFC_REG_CPTRA_RSVD_REG_1 (0x124)
+#define CLP_SOC_IFC_REG_CPTRA_HW_CAPABILITIES (0x30030128)
+#define SOC_IFC_REG_CPTRA_HW_CAPABILITIES (0x128)
+#define CLP_SOC_IFC_REG_CPTRA_FW_CAPABILITIES (0x3003012c)
+#define SOC_IFC_REG_CPTRA_FW_CAPABILITIES (0x12c)
+#define CLP_SOC_IFC_REG_CPTRA_CAP_LOCK (0x30030130)
+#define SOC_IFC_REG_CPTRA_CAP_LOCK (0x130)
+#define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_LOW (0)
+#define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_MASK (0x1)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (0x30030140)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (0x140)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (0x30030144)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (0x144)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (0x30030148)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (0x148)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (0x3003014c)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (0x14c)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (0x30030150)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (0x150)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (0x30030154)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (0x154)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (0x30030158)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (0x158)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (0x3003015c)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (0x15c)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (0x30030160)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (0x160)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (0x30030164)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (0x164)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (0x30030168)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (0x168)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (0x3003016c)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (0x16c)
+#define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (0x30030170)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (0x170)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0)
+#define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (0x1)
#define CLP_SOC_IFC_REG_FUSE_UDS_SEED_0 (0x30030200)
#define SOC_IFC_REG_FUSE_UDS_SEED_0 (0x200)
#define CLP_SOC_IFC_REG_FUSE_UDS_SEED_1 (0x30030204)
@@ -5788,118 +5830,190 @@
#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x288)
#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x3003028c)
#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x28c)
-#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x30030290)
-#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x290)
-#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0)
-#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (0xf)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_0 (0x30030294)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_0 (0x294)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_1 (0x30030298)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_1 (0x298)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_2 (0x3003029c)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_2 (0x29c)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_3 (0x300302a0)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_3 (0x2a0)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_4 (0x300302a4)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_4 (0x2a4)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_5 (0x300302a8)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_5 (0x2a8)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_6 (0x300302ac)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_6 (0x2ac)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_7 (0x300302b0)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_7 (0x2b0)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_8 (0x300302b4)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_8 (0x2b4)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_9 (0x300302b8)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_9 (0x2b8)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_10 (0x300302bc)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_10 (0x2bc)
-#define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_11 (0x300302c0)
-#define SOC_IFC_REG_FUSE_OWNER_PK_HASH_11 (0x2c0)
-#define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x300302c4)
-#define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2c4)
-#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x300302c8)
-#define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x2c8)
-#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (0x300302cc)
-#define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (0x2cc)
-#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (0x300302d0)
-#define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (0x2d0)
-#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (0x300302d4)
-#define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (0x2d4)
-#define CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x300302d8)
-#define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x2d8)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x30030290)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x290)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x30030294)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x294)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x30030298)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x298)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x3003029c)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x29c)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x300302a0)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x2a0)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x300302a4)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x2a4)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x300302a8)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x2a8)
+#define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x300302ac)
+#define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x2ac)
+#define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x300302b4)
+#define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4)
+#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x300302b8)
+#define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (0x2b8)
+#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (0x300302bc)
+#define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (0x2bc)
+#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (0x300302c0)
+#define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (0x2c0)
+#define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (0x300302c4)
+#define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (0x2c4)
+#define CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x300302c8)
+#define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x2c8)
#define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0)
#define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (0x1)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (0x300302dc)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (0x2dc)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (0x300302e0)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (0x2e0)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (0x300302e4)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (0x2e4)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (0x300302e8)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (0x2e8)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (0x300302ec)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (0x2ec)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (0x300302f0)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (0x2f0)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (0x300302f4)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (0x2f4)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (0x300302f8)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (0x2f8)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (0x300302fc)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (0x2fc)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (0x30030300)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (0x300)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (0x30030304)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (0x304)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (0x30030308)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (0x308)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (0x3003030c)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (0x30c)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (0x30030310)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (0x310)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (0x30030314)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (0x314)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (0x30030318)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (0x318)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (0x3003031c)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (0x31c)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (0x30030320)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (0x320)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (0x30030324)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (0x324)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (0x30030328)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (0x328)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (0x3003032c)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (0x32c)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (0x30030330)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (0x330)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (0x30030334)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (0x334)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (0x30030338)
-#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (0x338)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x3003033c)
-#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x33c)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x30030340)
-#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x340)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x30030344)
-#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x344)
-#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x30030348)
-#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x348)
-#define CLP_SOC_IFC_REG_FUSE_LIFE_CYCLE (0x3003034c)
-#define SOC_IFC_REG_FUSE_LIFE_CYCLE (0x34c)
-#define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW (0)
-#define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK (0x3)
-#define CLP_SOC_IFC_REG_FUSE_LMS_VERIFY (0x30030350)
-#define SOC_IFC_REG_FUSE_LMS_VERIFY (0x350)
-#define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW (0)
-#define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK (0x1)
-#define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION (0x30030354)
-#define SOC_IFC_REG_FUSE_LMS_REVOCATION (0x354)
-#define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID (0x30030358)
-#define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (0x358)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (0x300302cc)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (0x2cc)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (0x300302d0)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (0x2d0)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (0x300302d4)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (0x2d4)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (0x300302d8)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (0x2d8)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (0x300302dc)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (0x2dc)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (0x300302e0)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (0x2e0)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (0x300302e4)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (0x2e4)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (0x300302e8)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (0x2e8)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (0x300302ec)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (0x2ec)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (0x300302f0)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (0x2f0)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (0x300302f4)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (0x2f4)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (0x300302f8)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (0x2f8)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (0x300302fc)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (0x2fc)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (0x30030300)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (0x300)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (0x30030304)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (0x304)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (0x30030308)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (0x308)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (0x3003030c)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (0x30c)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (0x30030310)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (0x310)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (0x30030314)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (0x314)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (0x30030318)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (0x318)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (0x3003031c)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (0x31c)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (0x30030320)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (0x320)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (0x30030324)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (0x324)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (0x30030328)
+#define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (0x328)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x3003032c)
+#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x32c)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x30030330)
+#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x330)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x30030334)
+#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x334)
+#define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x30030338)
+#define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x338)
+#define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION (0x30030340)
+#define SOC_IFC_REG_FUSE_LMS_REVOCATION (0x340)
+#define CLP_SOC_IFC_REG_FUSE_MLDSA_REVOCATION (0x30030344)
+#define SOC_IFC_REG_FUSE_MLDSA_REVOCATION (0x344)
+#define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0)
+#define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (0xf)
+#define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID (0x30030348)
+#define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (0x348)
#define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0)
#define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (0xffff)
+#define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x3003034c)
+#define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x34c)
+#define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x30030350)
+#define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x350)
+#define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x30030354)
+#define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x354)
+#define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x30030358)
+#define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x358)
+#define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (0x30030500)
+#define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (0x500)
+#define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (0x30030504)
+#define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (0x504)
+#define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_L (0x30030508)
+#define SOC_IFC_REG_SS_MCI_BASE_ADDR_L (0x508)
+#define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_H (0x3003050c)
+#define SOC_IFC_REG_SS_MCI_BASE_ADDR_H (0x50c)
+#define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x30030510)
+#define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x510)
+#define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x30030514)
+#define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x514)
+#define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (0x30030518)
+#define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (0x518)
+#define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (0x3003051c)
+#define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (0x51c)
+#define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (0x30030520)
+#define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (0x520)
+#define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (0x30030524)
+#define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (0x524)
+#define CLP_SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x30030528)
+#define SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x528)
+#define CLP_SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x3003052c)
+#define SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x52c)
+#define CLP_SOC_IFC_REG_SS_DEBUG_INTENT (0x30030530)
+#define SOC_IFC_REG_SS_DEBUG_INTENT (0x530)
+#define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0)
+#define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (0x1)
+#define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_0 (0x300305a0)
+#define SOC_IFC_REG_SS_STRAP_GENERIC_0 (0x5a0)
+#define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_1 (0x300305a4)
+#define SOC_IFC_REG_SS_STRAP_GENERIC_1 (0x5a4)
+#define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_2 (0x300305a8)
+#define SOC_IFC_REG_SS_STRAP_GENERIC_2 (0x5a8)
+#define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_3 (0x300305ac)
+#define SOC_IFC_REG_SS_STRAP_GENERIC_3 (0x5ac)
+#define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x300305c0)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x5c0)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (0x1)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (0x2)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (0x4)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (0xfffffff8)
+#define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x300305c4)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x5c4)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (0x1)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (0x2)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (0x4)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (0x8)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (0x10)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (0x20)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (0x40)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (0x80)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (0x100)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9)
+#define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (0xfffffe00)
+#define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x300305c8)
+#define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x5c8)
+#define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x300305cc)
+#define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x5cc)
+#define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x300305d0)
+#define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x5d0)
+#define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x300305d4)
+#define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x5d4)
+#define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x300305d8)
+#define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x5d8)
+#define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x300305dc)
+#define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x5dc)
#define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0 (0x30030600)
#define SOC_IFC_REG_INTERNAL_OBF_KEY_0 (0x600)
#define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1 (0x30030604)
diff --git a/src/integration/rtl/caliptra_reg_defines.svh b/src/integration/rtl/caliptra_reg_defines.svh
index cc1dfc47b..375ba5b99 100644
--- a/src/integration/rtl/caliptra_reg_defines.svh
+++ b/src/integration/rtl/caliptra_reg_defines.svh
@@ -5075,6 +5075,10 @@
`define MBOX_CSR_MBOX_UNLOCK (32'h20)
`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0)
`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1)
+`define CLP_MBOX_CSR_TAP_MODE (32'h30020024)
+`define MBOX_CSR_TAP_MODE (32'h24)
+`define MBOX_CSR_TAP_MODE_ENABLED_LOW (0)
+`define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1)
`define CLP_SHA512_ACC_CSR_BASE_ADDR (32'h30021000)
`define CLP_SHA512_ACC_CSR_LOCK (32'h30021000)
`define SHA512_ACC_CSR_LOCK (32'h0)
@@ -5478,6 +5482,8 @@
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (32'h4)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3)
`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0)
`define CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (32'h30030004)
`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4)
`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0)
@@ -5486,6 +5492,8 @@
`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (32'h2)
`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2)
`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3)
+`define SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8)
`define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (32'h30030008)
`define SOC_IFC_REG_CPTRA_FW_ERROR_FATAL (32'h8)
`define CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL (32'h3003000c)
@@ -5520,8 +5528,8 @@
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000)
-`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
-`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (32'h10000000)
+`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
+`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000)
`define SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
@@ -5652,14 +5660,12 @@
`define SOC_IFC_REG_CPTRA_HW_CONFIG (32'he0)
`define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0)
`define SOC_IFC_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1)
-`define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW (1)
-`define SOC_IFC_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK (32'h2)
-`define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_LOW (2)
-`define SOC_IFC_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (32'h4)
-`define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3)
-`define SOC_IFC_REG_CPTRA_HW_CONFIG_UART_EN_MASK (32'h8)
+`define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1)
+`define SOC_IFC_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (32'he)
`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4)
`define SOC_IFC_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10)
+`define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5)
+`define SOC_IFC_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20)
`define CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'h300300e4)
`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN (32'he4)
`define SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0)
@@ -5716,6 +5722,42 @@
`define SOC_IFC_REG_CPTRA_RSVD_REG_0 (32'h120)
`define CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1 (32'h30030124)
`define SOC_IFC_REG_CPTRA_RSVD_REG_1 (32'h124)
+`define CLP_SOC_IFC_REG_CPTRA_HW_CAPABILITIES (32'h30030128)
+`define SOC_IFC_REG_CPTRA_HW_CAPABILITIES (32'h128)
+`define CLP_SOC_IFC_REG_CPTRA_FW_CAPABILITIES (32'h3003012c)
+`define SOC_IFC_REG_CPTRA_FW_CAPABILITIES (32'h12c)
+`define CLP_SOC_IFC_REG_CPTRA_CAP_LOCK (32'h30030130)
+`define SOC_IFC_REG_CPTRA_CAP_LOCK (32'h130)
+`define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_LOW (0)
+`define SOC_IFC_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (32'h30030140)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0 (32'h140)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (32'h30030144)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1 (32'h144)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (32'h30030148)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2 (32'h148)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (32'h3003014c)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (32'h30030150)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4 (32'h150)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (32'h30030154)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5 (32'h154)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (32'h30030158)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6 (32'h158)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (32'h3003015c)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (32'h30030160)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8 (32'h160)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (32'h30030164)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9 (32'h164)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (32'h30030168)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10 (32'h168)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (32'h3003016c)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c)
+`define CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h30030170)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0)
+`define SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1)
`define CLP_SOC_IFC_REG_FUSE_UDS_SEED_0 (32'h30030200)
`define SOC_IFC_REG_FUSE_UDS_SEED_0 (32'h200)
`define CLP_SOC_IFC_REG_FUSE_UDS_SEED_1 (32'h30030204)
@@ -5788,118 +5830,190 @@
`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h288)
`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h3003028c)
`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h28c)
-`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h30030290)
-`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h290)
-`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0)
-`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (32'hf)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_0 (32'h30030294)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_0 (32'h294)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_1 (32'h30030298)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_1 (32'h298)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_2 (32'h3003029c)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_2 (32'h29c)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_3 (32'h300302a0)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_3 (32'h2a0)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_4 (32'h300302a4)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_4 (32'h2a4)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_5 (32'h300302a8)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_5 (32'h2a8)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_6 (32'h300302ac)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_6 (32'h2ac)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_7 (32'h300302b0)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_7 (32'h2b0)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_8 (32'h300302b4)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_8 (32'h2b4)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_9 (32'h300302b8)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_9 (32'h2b8)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_10 (32'h300302bc)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_10 (32'h2bc)
-`define CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_11 (32'h300302c0)
-`define SOC_IFC_REG_FUSE_OWNER_PK_HASH_11 (32'h2c0)
-`define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h300302c4)
-`define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2c4)
-`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h300302c8)
-`define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h2c8)
-`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h300302cc)
-`define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h2cc)
-`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h300302d0)
-`define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h2d0)
-`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h300302d4)
-`define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h2d4)
-`define CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h300302d8)
-`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2d8)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h30030290)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h290)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h30030294)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h294)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h30030298)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h298)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h3003029c)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h29c)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h300302a0)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h2a0)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h300302a4)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h2a4)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h300302a8)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h2a8)
+`define CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h300302ac)
+`define SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h2ac)
+`define CLP_SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h300302b4)
+`define SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4)
+`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h300302b8)
+`define SOC_IFC_REG_FUSE_RUNTIME_SVN_0 (32'h2b8)
+`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h300302bc)
+`define SOC_IFC_REG_FUSE_RUNTIME_SVN_1 (32'h2bc)
+`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h300302c0)
+`define SOC_IFC_REG_FUSE_RUNTIME_SVN_2 (32'h2c0)
+`define CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h300302c4)
+`define SOC_IFC_REG_FUSE_RUNTIME_SVN_3 (32'h2c4)
+`define CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h300302c8)
+`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8)
`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0)
`define SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h300302dc)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2dc)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h300302e0)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2e0)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h300302e4)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2e4)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h300302e8)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2e8)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h300302ec)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2ec)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h300302f0)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2f0)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h300302f4)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2f4)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h300302f8)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2f8)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h300302fc)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2fc)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h30030300)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h300)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h30030304)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h304)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h30030308)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h308)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h3003030c)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h30c)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h30030310)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h310)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h30030314)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h314)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h30030318)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h318)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h3003031c)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h31c)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h30030320)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h320)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h30030324)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h324)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h30030328)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h328)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h3003032c)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h32c)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h30030330)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h330)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h30030334)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h334)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h30030338)
-`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h338)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h3003033c)
-`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h33c)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h30030340)
-`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h340)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h30030344)
-`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h344)
-`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h30030348)
-`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h348)
-`define CLP_SOC_IFC_REG_FUSE_LIFE_CYCLE (32'h3003034c)
-`define SOC_IFC_REG_FUSE_LIFE_CYCLE (32'h34c)
-`define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW (0)
-`define SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK (32'h3)
-`define CLP_SOC_IFC_REG_FUSE_LMS_VERIFY (32'h30030350)
-`define SOC_IFC_REG_FUSE_LMS_VERIFY (32'h350)
-`define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW (0)
-`define SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK (32'h1)
-`define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h30030354)
-`define SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h354)
-`define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h30030358)
-`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h358)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h300302cc)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h300302d0)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h300302d4)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h300302d8)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h300302dc)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h300302e0)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h300302e4)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h300302e8)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h300302ec)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h300302f0)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h300302f4)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h300302f8)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h300302fc)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h30030300)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h30030304)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h30030308)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h3003030c)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h30030310)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h30030314)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h30030318)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h3003031c)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h30030320)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h30030324)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h30030328)
+`define SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h3003032c)
+`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h30030330)
+`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h30030334)
+`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334)
+`define CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h30030338)
+`define SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338)
+`define CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h30030340)
+`define SOC_IFC_REG_FUSE_LMS_REVOCATION (32'h340)
+`define CLP_SOC_IFC_REG_FUSE_MLDSA_REVOCATION (32'h30030344)
+`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION (32'h344)
+`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0)
+`define SOC_IFC_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf)
+`define CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h30030348)
+`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID (32'h348)
`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0)
`define SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff)
+`define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h3003034c)
+`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c)
+`define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h30030350)
+`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350)
+`define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h30030354)
+`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354)
+`define CLP_SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h30030358)
+`define SOC_IFC_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358)
+`define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h30030500)
+`define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500)
+`define CLP_SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (32'h30030504)
+`define SOC_IFC_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504)
+`define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_L (32'h30030508)
+`define SOC_IFC_REG_SS_MCI_BASE_ADDR_L (32'h508)
+`define CLP_SOC_IFC_REG_SS_MCI_BASE_ADDR_H (32'h3003050c)
+`define SOC_IFC_REG_SS_MCI_BASE_ADDR_H (32'h50c)
+`define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h30030510)
+`define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510)
+`define CLP_SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h30030514)
+`define SOC_IFC_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514)
+`define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (32'h30030518)
+`define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_L (32'h518)
+`define CLP_SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (32'h3003051c)
+`define SOC_IFC_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c)
+`define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (32'h30030520)
+`define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520)
+`define CLP_SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (32'h30030524)
+`define SOC_IFC_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524)
+`define CLP_SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h30030528)
+`define SOC_IFC_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528)
+`define CLP_SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h3003052c)
+`define SOC_IFC_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c)
+`define CLP_SOC_IFC_REG_SS_DEBUG_INTENT (32'h30030530)
+`define SOC_IFC_REG_SS_DEBUG_INTENT (32'h530)
+`define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0)
+`define SOC_IFC_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1)
+`define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_0 (32'h300305a0)
+`define SOC_IFC_REG_SS_STRAP_GENERIC_0 (32'h5a0)
+`define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_1 (32'h300305a4)
+`define SOC_IFC_REG_SS_STRAP_GENERIC_1 (32'h5a4)
+`define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_2 (32'h300305a8)
+`define SOC_IFC_REG_SS_STRAP_GENERIC_2 (32'h5a8)
+`define CLP_SOC_IFC_REG_SS_STRAP_GENERIC_3 (32'h300305ac)
+`define SOC_IFC_REG_SS_STRAP_GENERIC_3 (32'h5ac)
+`define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h300305c0)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (32'h2)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8)
+`define CLP_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h300305c4)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (32'h2)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (32'h4)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (32'h8)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (32'h10)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (32'h20)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (32'h40)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (32'h80)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9)
+`define SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00)
+`define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h300305c8)
+`define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8)
+`define CLP_SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h300305cc)
+`define SOC_IFC_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc)
+`define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h300305d0)
+`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0)
+`define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h300305d4)
+`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4)
+`define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h300305d8)
+`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8)
+`define CLP_SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h300305dc)
+`define SOC_IFC_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc)
`define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0 (32'h30030600)
`define SOC_IFC_REG_INTERNAL_OBF_KEY_0 (32'h600)
`define CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_1 (32'h30030604)
diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
index f1aef1c16..e4f1ff25b 100755
--- a/src/integration/rtl/caliptra_top.sv
+++ b/src/integration/rtl/caliptra_top.sv
@@ -69,7 +69,7 @@ module caliptra_top
input logic [`CALIPTRA_IMEM_DATA_WIDTH-1:0] imem_rdata,
output logic ready_for_fuses,
- output logic ready_for_fw_push,
+ output logic ready_for_mb_processing,
output logic ready_for_runtime,
output logic mailbox_data_avail,
@@ -90,6 +90,27 @@ module caliptra_top
input logic [3:0] itrng_data,
input logic itrng_valid,
+ // Subsystem mode straps
+ input logic [63:0] strap_ss_caliptra_base_addr,
+ input logic [63:0] strap_ss_mci_base_addr,
+ input logic [63:0] strap_ss_recovery_ifc_base_addr,
+ input logic [63:0] strap_ss_otp_fc_base_addr,
+ input logic [63:0] strap_ss_uds_seed_base_addr,
+ input logic [31:0] strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset,
+ input logic [31:0] strap_ss_num_of_prod_debug_unlock_auth_pk_hashes,
+ input logic [31:0] strap_ss_strap_generic_0,
+ input logic [31:0] strap_ss_strap_generic_1,
+ input logic [31:0] strap_ss_strap_generic_2,
+ input logic [31:0] strap_ss_strap_generic_3,
+ input logic ss_debug_intent,
+
+ // Subsystem mode debug outputs
+ output logic ss_dbg_manuf_enable,
+ output logic [63:0] ss_soc_dbg_unlock_level,
+
+ // Subsystem mode firmware execution control
+ output logic [127:0] ss_generic_fw_exec_ctrl,
+
input logic [63:0] generic_input_wires,
output logic [63:0] generic_output_wires,
@@ -178,6 +199,7 @@ module caliptra_top
logic [31:0] cptra_uncore_dmi_reg_rdata;
logic [6:0] cptra_uncore_dmi_reg_addr;
logic [31:0] cptra_uncore_dmi_reg_wdata;
+ logic unlock_caliptra_security_state;
security_state_t cptra_security_state_Latched;
security_state_t cptra_security_state_Latched_d;
security_state_t cptra_security_state_Latched_f;
@@ -185,6 +207,8 @@ module caliptra_top
logic fw_update_rst_window;
+ logic cptra_ss_debug_intent; //qualified debug intent
+
// Caliptra ECC status signals
rv_ecc_sts_t rv_ecc_sts;
@@ -231,11 +255,10 @@ module caliptra_top
mbox_sram_resp_t mbox_sram_resp;
logic clear_obf_secrets;
- logic clear_secrets;
-
- logic cptra_security_state_captured;
logic scan_mode_switch;
- logic debug_lock_or_scan_mode_switch, clear_obf_secrets_debugScanQ, debug_lock_switch;
+ logic debug_lock_switch;
+ logic device_lifecycle_switch;
+ logic debug_lock_or_scan_mode_switch, clear_obf_secrets_debugScanQ;
logic cptra_scan_mode_Latched, cptra_scan_mode_Latched_d, cptra_scan_mode_Latched_f;
logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key_dbg;
@@ -391,9 +414,12 @@ always_comb begin
intr[NUM_INTR-1:`VEER_INTR_VEC_MAX_ASSIGNED] = '0;
end
-always_comb cptra_core_dmi_enable = ~(cptra_security_state_Latched.debug_locked);
+//Open Core TAP only for debug unlocked
+always_comb cptra_core_dmi_enable = ~(cptra_security_state_Latched.debug_locked);
+//Open Uncore TAP for debug unlocked, or DEVICE_MANUFACTURING, or debug intent set
always_comb cptra_uncore_dmi_enable = ~(cptra_security_state_Latched.debug_locked) |
- ((cptra_security_state_Latched.debug_locked) & (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING));
+ (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING) |
+ cptra_ss_debug_intent;
el2_veer_wrapper rvtop (
`ifdef CALIPTRA_FORCE_CPU_RESET
@@ -590,18 +616,25 @@ el2_veer_wrapper rvtop (
.hrdata_i (initiator_inst.hrdata)
);
- // Security State value captured on a Caliptra reset deassertion (0->1 signal transition)
+ // Security State value captured on a Caliptra reset deassertion
+ // Security State can be unlocked by setting ss_dbg_manuf_enable or ss_soc_dbg_unlock_level[0]
+ always_ff @(posedge clk or negedge cptra_noncore_rst_b) begin
+ if (~cptra_noncore_rst_b) begin
+ unlock_caliptra_security_state <= 1;
+ end
+ else begin
+ unlock_caliptra_security_state <= ss_dbg_manuf_enable || ss_soc_dbg_unlock_level[0];
+ end
+ end
+
always_ff @(posedge clk or negedge cptra_noncore_rst_b) begin
if (~cptra_noncore_rst_b) begin
cptra_security_state_Latched_d <= '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1}; //Setting the default value to be debug locked and in production mode
cptra_security_state_Latched_f <= '{device_lifecycle: DEVICE_PRODUCTION, debug_locked: 1'b1};
-
- cptra_security_state_captured <= 0;
end
- else if(!cptra_security_state_captured) begin
+ else if (unlock_caliptra_security_state) begin
cptra_security_state_Latched_d <= security_state;
- cptra_security_state_captured <= 1;
- end
+ end
else begin
cptra_security_state_Latched_f <= cptra_security_state_Latched_d;
end
@@ -619,19 +652,23 @@ el2_veer_wrapper rvtop (
end
//Lock debug unless both flops are unlocked
- assign cptra_security_state_Latched.debug_locked = cptra_security_state_Latched_d.debug_locked | cptra_security_state_Latched_f.debug_locked;
+ always_comb cptra_security_state_Latched.debug_locked = cptra_security_state_Latched_d.debug_locked | cptra_security_state_Latched_f.debug_locked;
//Pass on the latched value of device lifecycle
- assign cptra_security_state_Latched.device_lifecycle = cptra_security_state_Latched_d.device_lifecycle;
+ always_comb cptra_security_state_Latched.device_lifecycle = cptra_security_state_Latched_f.device_lifecycle;
//Only assert scan mode once both flops have set
- assign cptra_scan_mode_Latched = cptra_scan_mode_Latched_d & cptra_scan_mode_Latched_f;
+ always_comb cptra_scan_mode_Latched = cptra_scan_mode_Latched_d & cptra_scan_mode_Latched_f;
// When scan mode goes from 0->1, generate a pulse to clear the assets
// Note that when scan goes to '1, Caliptra state as well as SOC state
// gets messed up. So switch to scan is destructive (obvious! Duh!)
- assign scan_mode_switch = cptra_scan_mode_Latched_d & ~cptra_scan_mode_Latched_f;
+ always_comb scan_mode_switch = cptra_scan_mode_Latched_d & ~cptra_scan_mode_Latched_f;
// Detect transition of debug mode
- assign debug_lock_switch = cptra_security_state_Latched_d.debug_locked ^ cptra_security_state_Latched_f.debug_locked;
- assign debug_lock_or_scan_mode_switch = debug_lock_switch | scan_mode_switch | cptra_error_fatal;
+ always_comb debug_lock_switch = cptra_security_state_Latched_d.debug_locked ^ cptra_security_state_Latched_f.debug_locked;
+ // Detect transition from valid lifecycle state to invalid
+ always_comb device_lifecycle_switch = (cptra_security_state_Latched_f.device_lifecycle inside {DEVICE_MANUFACTURING, DEVICE_PRODUCTION}) &
+ ~(cptra_security_state_Latched_d.device_lifecycle inside {DEVICE_MANUFACTURING, DEVICE_PRODUCTION});
+
+ assign debug_lock_or_scan_mode_switch = debug_lock_switch | scan_mode_switch | device_lifecycle_switch | cptra_error_fatal;
assign clear_obf_secrets_debugScanQ = clear_obf_secrets | cptra_in_debug_scan_mode | cptra_error_fatal;
@@ -642,7 +679,7 @@ el2_veer_wrapper rvtop (
cptra_csr_hmac_key_reg <= '0;
end
//Only latch the value during device manufacturing
- else if (cptra_security_state_Latched_f.device_lifecycle == DEVICE_MANUFACTURING) begin
+ else if (cptra_security_state_Latched.device_lifecycle == DEVICE_MANUFACTURING) begin
cptra_csr_hmac_key_reg <= cptra_csr_hmac_key;
end
end
@@ -831,8 +868,9 @@ sha256_ctrl #(
.debugUnlock_or_scan_mode_switch(debug_lock_or_scan_mode_switch)
);
-//override device secrets with debug values in Debug or Scan Mode
-always_comb cptra_in_debug_scan_mode = ~cptra_security_state_Latched.debug_locked | cptra_scan_mode_Latched;
+//override device secrets with debug values in Debug or Scan Mode or any device lifecycle other than PROD and MANUF
+always_comb cptra_in_debug_scan_mode = ~cptra_security_state_Latched.debug_locked | cptra_scan_mode_Latched |
+ ~(cptra_security_state_Latched.device_lifecycle inside {DEVICE_PRODUCTION, DEVICE_MANUFACTURING});
always_comb cptra_obf_key_dbg = cptra_in_debug_scan_mode ? `CLP_DEBUG_MODE_OBF_KEY : cptra_obf_key_reg;
always_comb obf_uds_seed_dbg = cptra_in_debug_scan_mode ? `CLP_DEBUG_MODE_UDS_SEED : obf_uds_seed;
always_comb obf_field_entropy_dbg = cptra_in_debug_scan_mode ? `CLP_DEBUG_MODE_FIELD_ENTROPY : obf_field_entropy;
@@ -1158,7 +1196,7 @@ soc_ifc_top1
.cptra_rst_b (cptra_rst_b ),
.ready_for_fuses(ready_for_fuses),
- .ready_for_fw_push(ready_for_fw_push),
+ .ready_for_mb_processing(ready_for_mb_processing),
.ready_for_runtime(ready_for_runtime),
.mailbox_data_avail(mailbox_data_avail),
.mailbox_flow_done(mailbox_flow_done),
@@ -1222,6 +1260,28 @@ soc_ifc_top1
.cptra_obf_key_reg(cptra_obf_key_reg),
.obf_field_entropy(obf_field_entropy),
.obf_uds_seed(obf_uds_seed),
+
+ // Subsystem mode straps
+ .strap_ss_caliptra_base_addr (strap_ss_caliptra_base_addr ),
+ .strap_ss_mci_base_addr (strap_ss_mci_base_addr ),
+ .strap_ss_recovery_ifc_base_addr (strap_ss_recovery_ifc_base_addr ),
+ .strap_ss_otp_fc_base_addr (strap_ss_otp_fc_base_addr ),
+ .strap_ss_uds_seed_base_addr (strap_ss_uds_seed_base_addr ),
+ .strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset(strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset),
+ .strap_ss_num_of_prod_debug_unlock_auth_pk_hashes (strap_ss_num_of_prod_debug_unlock_auth_pk_hashes ),
+ .strap_ss_strap_generic_0 (strap_ss_strap_generic_0 ),
+ .strap_ss_strap_generic_1 (strap_ss_strap_generic_1 ),
+ .strap_ss_strap_generic_2 (strap_ss_strap_generic_2 ),
+ .strap_ss_strap_generic_3 (strap_ss_strap_generic_3 ),
+ .ss_debug_intent (ss_debug_intent ),
+ .cptra_ss_debug_intent (cptra_ss_debug_intent ),
+ // Subsystem mode debug outputs
+ .ss_dbg_manuf_enable (ss_dbg_manuf_enable ),
+ .ss_soc_dbg_unlock_level(ss_soc_dbg_unlock_level),
+
+ // Subsystem mode firmware execution control
+ .ss_generic_fw_exec_ctrl(ss_generic_fw_exec_ctrl),
+
// NMI Vector
.nmi_vector(nmi_vector),
.nmi_intr(nmi_int),
@@ -1238,7 +1298,7 @@ soc_ifc_top1
//multiple cryptos operating at once, assert fatal error
.crypto_error(crypto_error),
//caliptra uncore jtag ports
- .cptra_uncore_dmi_reg_en ( cptra_uncore_dmi_reg_en ),
+ .cptra_uncore_dmi_reg_en( cptra_uncore_dmi_reg_en ),
.cptra_uncore_dmi_reg_wr_en( cptra_uncore_dmi_reg_wr_en ),
.cptra_uncore_dmi_reg_rdata( cptra_uncore_dmi_reg_rdata ),
.cptra_uncore_dmi_reg_addr ( cptra_uncore_dmi_reg_addr ),
diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv
index deae275d9..69a19184b 100755
--- a/src/integration/tb/caliptra_top_tb.sv
+++ b/src/integration/tb/caliptra_top_tb.sv
@@ -1,396 +1,417 @@
-// SPDX-License-Identifier: Apache-2.0
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-`default_nettype none
-
-`include "common_defines.sv"
-`include "config_defines.svh"
-`include "caliptra_reg_defines.svh"
-`include "caliptra_macros.svh"
-
-`ifndef VERILATOR
-module caliptra_top_tb;
-`else
-module caliptra_top_tb (
- input bit core_clk,
- input bit rst_l
- );
-`endif
-
- import axi_pkg::*;
- import soc_ifc_pkg::*;
- import caliptra_top_tb_pkg::*;
-
-`ifndef VERILATOR
- // Time formatting for %t in display tasks
- // -9 = ns units
- // 3 = 3 bits of precision (to the ps)
- // "ns" = nanosecond suffix for output time values
- // 15 = 15 bits minimum field width
- initial $timeformat(-9, 3, " ns", 15); // up to 99ms representable in this width
-`endif
-
-`ifndef VERILATOR
- bit core_clk;
-`endif
-
- int cycleCnt;
-
-
- logic cptra_pwrgood;
- logic cptra_rst_b;
- logic BootFSM_BrkPoint;
- logic scan_mode;
-
- logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key;
-
- logic [`CLP_CSR_HMAC_KEY_DWORDS-1:0][31:0] cptra_csr_hmac_key;
-
- logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] cptra_uds_rand;
- logic [0:`CLP_OBF_FE_DWORDS-1][31:0] cptra_fe_rand;
- logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] cptra_obf_key_tb;
-
- //jtag interface
- logic jtag_tck; // JTAG clk
- logic jtag_tms; // JTAG TMS
- logic jtag_tdi; // JTAG tdi
- logic jtag_trst_n; // JTAG Reset
- logic jtag_tdo; // JTAG TDO
- logic jtag_tdoEn; // JTAG TDO enable
-
- // AXI Interface
- axi_if #(
- .AW(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
- .DW(`CALIPTRA_AXI_DATA_WIDTH),
- .IW(`CALIPTRA_AXI_ID_WIDTH),
- .UW(`CALIPTRA_AXI_USER_WIDTH)
- ) m_axi_bfm_if (.clk(core_clk), .rst_n(cptra_rst_b));
- axi_if #(
- .AW(`CALIPTRA_AXI_DMA_ADDR_WIDTH),
- .DW(CPTRA_AXI_DMA_DATA_WIDTH),
- .IW(CPTRA_AXI_DMA_ID_WIDTH),
- .UW(CPTRA_AXI_DMA_USER_WIDTH)
- ) m_axi_if (.clk(core_clk), .rst_n(cptra_rst_b));
- axi_if #(
- .AW(AXI_SRAM_ADDR_WIDTH),
- .DW(CPTRA_AXI_DMA_DATA_WIDTH),
- .IW(CPTRA_AXI_DMA_ID_WIDTH),
- .UW(CPTRA_AXI_DMA_USER_WIDTH)
- ) axi_sram_if (.clk(core_clk), .rst_n(cptra_rst_b));
-
- logic ready_for_fuses;
- logic ready_for_fw_push;
- logic mailbox_data_avail;
- logic mbox_sram_cs;
- logic mbox_sram_we;
- logic [14:0] mbox_sram_addr;
- logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata;
- logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata;
-
- logic imem_cs;
- logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr;
- logic [`CALIPTRA_IMEM_DATA_WIDTH-1:0] imem_rdata;
-
- //device lifecycle
- security_state_t security_state;
-
- ras_test_ctrl_t ras_test_ctrl;
- logic [63:0] generic_input_wires;
- logic etrng_req;
- logic [3:0] itrng_data;
- logic itrng_valid;
-
- logic cptra_error_fatal;
- logic cptra_error_non_fatal;
-
- //Interrupt flags
- logic int_flag;
- logic cycleCnt_smpl_en;
-
- //Reset flags
- logic assert_hard_rst_flag;
- logic deassert_hard_rst_flag;
- logic assert_rst_flag_from_service;
- logic deassert_rst_flag_from_service;
-
- el2_mem_if el2_mem_export ();
-
-`ifndef VERILATOR
- always
- begin : clk_gen
- core_clk = #5ns ~core_clk;
- end // clk_gen
-`endif
-
-
-caliptra_top_tb_soc_bfm soc_bfm_inst (
- .core_clk (core_clk ),
-
- .cptra_pwrgood (cptra_pwrgood ),
- .cptra_rst_b (cptra_rst_b ),
-
- .BootFSM_BrkPoint(BootFSM_BrkPoint),
- .cycleCnt (cycleCnt ),
-
- .cptra_obf_key (cptra_obf_key ),
- .cptra_csr_hmac_key (cptra_csr_hmac_key),
-
- .cptra_uds_rand (cptra_uds_rand ),
- .cptra_fe_rand (cptra_fe_rand ),
- .cptra_obf_key_tb(cptra_obf_key_tb),
-
- .m_axi_bfm_if(m_axi_bfm_if),
-
- .ready_for_fuses (ready_for_fuses ),
- .ready_for_fw_push (ready_for_fw_push ),
- .mailbox_data_avail(mailbox_data_avail),
-
- .ras_test_ctrl(ras_test_ctrl),
-
- .generic_input_wires(generic_input_wires),
-
- .cptra_error_fatal(cptra_error_fatal),
- .cptra_error_non_fatal(cptra_error_non_fatal),
-
- //Interrupt flags
- .int_flag(int_flag),
- .cycleCnt_smpl_en(cycleCnt_smpl_en),
-
- .assert_hard_rst_flag(assert_hard_rst_flag),
- .deassert_hard_rst_flag(deassert_hard_rst_flag),
- .assert_rst_flag_from_service(assert_rst_flag_from_service),
- .deassert_rst_flag_from_service(deassert_rst_flag_from_service)
-
-);
-
-// JTAG DPI
-jtagdpi #(
- .Name ("jtag0"),
- .ListenPort (5000)
-) jtagdpi (
- .clk_i (core_clk),
- .rst_ni (cptra_rst_b),
- .jtag_tck (jtag_tck),
- .jtag_tms (jtag_tms),
- .jtag_tdi (jtag_tdi),
- .jtag_tdo (jtag_tdo),
- .jtag_trst_n (jtag_trst_n),
- .jtag_srst_n ()
-);
-
- //=========================================================================-
- // DUT instance
- //=========================================================================-
-caliptra_top caliptra_top_dut (
- .cptra_pwrgood (cptra_pwrgood),
- .cptra_rst_b (cptra_rst_b),
- .clk (core_clk),
-
- .cptra_obf_key (cptra_obf_key),
-
- .cptra_csr_hmac_key (cptra_csr_hmac_key),
-
- .jtag_tck(jtag_tck),
- .jtag_tdi(jtag_tdi),
- .jtag_tms(jtag_tms),
- .jtag_trst_n(jtag_trst_n),
- .jtag_tdo(jtag_tdo),
- .jtag_tdoEn(jtag_tdoEn),
-
- //SoC AXI Interface
- .s_axi_w_if(m_axi_bfm_if.w_sub),
- .s_axi_r_if(m_axi_bfm_if.r_sub),
-
- //AXI DMA Interface
- .m_axi_w_if(m_axi_if.w_mgr),
- .m_axi_r_if(m_axi_if.r_mgr),
-
- .el2_mem_export(el2_mem_export.veer_sram_src),
-
- .ready_for_fuses(ready_for_fuses),
- .ready_for_fw_push(ready_for_fw_push),
- .ready_for_runtime(),
-
- .mbox_sram_cs(mbox_sram_cs),
- .mbox_sram_we(mbox_sram_we),
- .mbox_sram_addr(mbox_sram_addr),
- .mbox_sram_wdata(mbox_sram_wdata),
- .mbox_sram_rdata(mbox_sram_rdata),
-
- .imem_cs(imem_cs),
- .imem_addr(imem_addr),
- .imem_rdata(imem_rdata),
-
- .mailbox_data_avail(mailbox_data_avail),
- .mailbox_flow_done(),
- .BootFSM_BrkPoint(BootFSM_BrkPoint),
-
- .recovery_data_avail(1'b1/*TODO*/),
-
- //SoC Interrupts
- .cptra_error_fatal (cptra_error_fatal ),
- .cptra_error_non_fatal(cptra_error_non_fatal),
-
-`ifdef CALIPTRA_INTERNAL_TRNG
- .etrng_req (etrng_req),
- .itrng_data (itrng_data),
- .itrng_valid (itrng_valid),
-`else
- .etrng_req (),
- .itrng_data (4'b0),
- .itrng_valid (1'b0),
-`endif
-
- .generic_input_wires(generic_input_wires),
- .generic_output_wires(),
-
- .security_state(security_state),
- .scan_mode (scan_mode)
-);
-
-
-`ifdef CALIPTRA_INTERNAL_TRNG
- //=========================================================================-
- // Physical RNG used for Internal TRNG
- //=========================================================================-
-physical_rng physical_rng (
- .clk (core_clk),
- .enable (etrng_req),
- .data (itrng_data),
- .valid (itrng_valid)
-);
-`endif
-
- //=========================================================================-
- // Services for SRAM exports, STDOUT, etc
- //=========================================================================-
-caliptra_top_tb_services #(
- .UVM_TB(0)
-) tb_services_i (
- .clk(core_clk),
-
- .cptra_rst_b(cptra_rst_b),
-
- // Caliptra Memory Export Interface
- .el2_mem_export (el2_mem_export.veer_sram_sink),
-
- //SRAM interface for mbox
- .mbox_sram_cs (mbox_sram_cs ),
- .mbox_sram_we (mbox_sram_we ),
- .mbox_sram_addr (mbox_sram_addr ),
- .mbox_sram_wdata(mbox_sram_wdata),
- .mbox_sram_rdata(mbox_sram_rdata),
-
- //SRAM interface for imem
- .imem_cs (imem_cs ),
- .imem_addr (imem_addr ),
- .imem_rdata(imem_rdata),
-
- // Security State
- .security_state(security_state),
-
- //Scan mode
- .scan_mode(scan_mode),
-
- // TB Controls
- .ras_test_ctrl(ras_test_ctrl),
- .cycleCnt(cycleCnt),
-
- //Interrupt flags
- .int_flag(int_flag),
- .cycleCnt_smpl_en(cycleCnt_smpl_en),
-
- //Reset flags
- .assert_hard_rst_flag(assert_hard_rst_flag),
- .deassert_hard_rst_flag(deassert_hard_rst_flag),
-
- .assert_rst_flag(assert_rst_flag_from_service),
- .deassert_rst_flag(deassert_rst_flag_from_service),
-
- .cptra_uds_tb(cptra_uds_rand),
- .cptra_fe_tb(cptra_fe_rand),
- .cptra_obf_key_tb(cptra_obf_key_tb)
-
-);
-
-// Dummy interconnect
-always_comb begin
- // AXI AR
- axi_sram_if.araddr = m_axi_if.araddr[AXI_SRAM_ADDR_WIDTH-1:0];
- axi_sram_if.arburst = m_axi_if.arburst;
- axi_sram_if.arsize = m_axi_if.arsize ;
- axi_sram_if.arlen = m_axi_if.arlen ;
- axi_sram_if.aruser = m_axi_if.aruser ;
- axi_sram_if.arid = m_axi_if.arid ;
- axi_sram_if.arlock = m_axi_if.arlock ;
- axi_sram_if.arvalid = m_axi_if.arvalid && m_axi_if.araddr[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH] == AXI_SRAM_BASE_ADDR[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH];
- m_axi_if.arready = axi_sram_if.arready;
-
- // AXI R
- m_axi_if.rdata = axi_sram_if.rdata ;
- m_axi_if.rresp = axi_sram_if.rresp ;
- m_axi_if.rid = axi_sram_if.rid ;
- m_axi_if.rlast = axi_sram_if.rlast ;
- m_axi_if.rvalid = axi_sram_if.rvalid;
- axi_sram_if.rready = m_axi_if.rready ;
-
- // AXI AW
- axi_sram_if.awaddr = m_axi_if.awaddr[AXI_SRAM_ADDR_WIDTH-1:0];
- axi_sram_if.awburst = m_axi_if.awburst;
- axi_sram_if.awsize = m_axi_if.awsize ;
- axi_sram_if.awlen = m_axi_if.awlen ;
- axi_sram_if.awuser = m_axi_if.awuser ;
- axi_sram_if.awid = m_axi_if.awid ;
- axi_sram_if.awlock = m_axi_if.awlock ;
- axi_sram_if.awvalid = m_axi_if.awvalid && m_axi_if.awaddr[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH] == AXI_SRAM_BASE_ADDR[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH];
- m_axi_if.awready = axi_sram_if.awready;
-
- // AXI W
- axi_sram_if.wdata = m_axi_if.wdata ;
- axi_sram_if.wstrb = m_axi_if.wstrb ;
- axi_sram_if.wvalid = m_axi_if.wvalid ;
- axi_sram_if.wlast = m_axi_if.wlast ;
- m_axi_if.wready = axi_sram_if.wready ;
-
- // AXI B
- m_axi_if.bresp = axi_sram_if.bresp ;
- m_axi_if.bid = axi_sram_if.bid ;
- m_axi_if.bvalid = axi_sram_if.bvalid ;
- axi_sram_if.bready = m_axi_if.bready ;
-end
-
-// Fake "MCU" SRAM block
-caliptra_axi_sram #(
- .AW(AXI_SRAM_ADDR_WIDTH),
- .DW(CPTRA_AXI_DMA_DATA_WIDTH),
- .UW(CPTRA_AXI_DMA_USER_WIDTH),
- .IW(CPTRA_AXI_DMA_ID_WIDTH),
- .EX_EN(0)
-) i_axi_sram (
- .clk(core_clk),
- .rst_n(cptra_rst_b),
-
- // AXI INF
- .s_axi_w_if(axi_sram_if.w_sub),
- .s_axi_r_if(axi_sram_if.r_sub)
-);
-`ifdef VERILATOR
-initial i_axi_sram.i_sram.ram = '{default:'{default:8'h00}};
-`else
-initial i_axi_sram.i_sram.ram = '{default:8'h00};
-`endif
-
-caliptra_top_sva sva();
-
-endmodule
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+`default_nettype none
+
+`include "common_defines.sv"
+`include "config_defines.svh"
+`include "caliptra_reg_defines.svh"
+`include "caliptra_macros.svh"
+
+`ifndef VERILATOR
+module caliptra_top_tb;
+`else
+module caliptra_top_tb (
+ input bit core_clk,
+ input bit rst_l
+ );
+`endif
+
+ import axi_pkg::*;
+ import soc_ifc_pkg::*;
+ import caliptra_top_tb_pkg::*;
+
+`ifndef VERILATOR
+ // Time formatting for %t in display tasks
+ // -9 = ns units
+ // 3 = 3 bits of precision (to the ps)
+ // "ns" = nanosecond suffix for output time values
+ // 15 = 15 bits minimum field width
+ initial $timeformat(-9, 3, " ns", 15); // up to 99ms representable in this width
+`endif
+
+`ifndef VERILATOR
+ bit core_clk;
+`endif
+
+ int cycleCnt;
+
+
+ logic cptra_pwrgood;
+ logic cptra_rst_b;
+ logic BootFSM_BrkPoint;
+ logic scan_mode;
+
+ logic [`CLP_OBF_KEY_DWORDS-1:0][31:0] cptra_obf_key;
+
+ logic [`CLP_CSR_HMAC_KEY_DWORDS-1:0][31:0] cptra_csr_hmac_key;
+
+ logic [0:`CLP_OBF_UDS_DWORDS-1][31:0] cptra_uds_rand;
+ logic [0:`CLP_OBF_FE_DWORDS-1][31:0] cptra_fe_rand;
+ logic [0:`CLP_OBF_KEY_DWORDS-1][31:0] cptra_obf_key_tb;
+
+ //jtag interface
+ logic jtag_tck; // JTAG clk
+ logic jtag_tms; // JTAG TMS
+ logic jtag_tdi; // JTAG tdi
+ logic jtag_trst_n; // JTAG Reset
+ logic jtag_tdo; // JTAG TDO
+ logic jtag_tdoEn; // JTAG TDO enable
+
+ // AXI Interface
+ axi_if #(
+ .AW(`CALIPTRA_SLAVE_ADDR_WIDTH(`CALIPTRA_SLAVE_SEL_SOC_IFC)),
+ .DW(`CALIPTRA_AXI_DATA_WIDTH),
+ .IW(`CALIPTRA_AXI_ID_WIDTH),
+ .UW(`CALIPTRA_AXI_USER_WIDTH)
+ ) m_axi_bfm_if (.clk(core_clk), .rst_n(cptra_rst_b));
+ axi_if #(
+ .AW(`CALIPTRA_AXI_DMA_ADDR_WIDTH),
+ .DW(CPTRA_AXI_DMA_DATA_WIDTH),
+ .IW(CPTRA_AXI_DMA_ID_WIDTH),
+ .UW(CPTRA_AXI_DMA_USER_WIDTH)
+ ) m_axi_if (.clk(core_clk), .rst_n(cptra_rst_b));
+ axi_if #(
+ .AW(AXI_SRAM_ADDR_WIDTH),
+ .DW(CPTRA_AXI_DMA_DATA_WIDTH),
+ .IW(CPTRA_AXI_DMA_ID_WIDTH),
+ .UW(CPTRA_AXI_DMA_USER_WIDTH)
+ ) axi_sram_if (.clk(core_clk), .rst_n(cptra_rst_b));
+
+ logic ready_for_fuses;
+ logic ready_for_mb_processing;
+ logic mailbox_data_avail;
+ logic mbox_sram_cs;
+ logic mbox_sram_we;
+ logic [14:0] mbox_sram_addr;
+ logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_wdata;
+ logic [MBOX_DATA_AND_ECC_W-1:0] mbox_sram_rdata;
+
+ logic imem_cs;
+ logic [`CALIPTRA_IMEM_ADDR_WIDTH-1:0] imem_addr;
+ logic [`CALIPTRA_IMEM_DATA_WIDTH-1:0] imem_rdata;
+
+ //device lifecycle
+ security_state_t security_state;
+
+ ras_test_ctrl_t ras_test_ctrl;
+ logic [63:0] generic_input_wires;
+ logic etrng_req;
+ logic [3:0] itrng_data;
+ logic itrng_valid;
+
+ logic cptra_error_fatal;
+ logic cptra_error_non_fatal;
+
+ //Interrupt flags
+ logic int_flag;
+ logic cycleCnt_smpl_en;
+
+ //Reset flags
+ logic assert_hard_rst_flag;
+ logic deassert_hard_rst_flag;
+ logic assert_rst_flag_from_service;
+ logic deassert_rst_flag_from_service;
+
+ el2_mem_if el2_mem_export ();
+
+`ifndef VERILATOR
+ always
+ begin : clk_gen
+ core_clk = #5ns ~core_clk;
+ end // clk_gen
+`endif
+
+
+caliptra_top_tb_soc_bfm soc_bfm_inst (
+ .core_clk (core_clk ),
+
+ .cptra_pwrgood (cptra_pwrgood ),
+ .cptra_rst_b (cptra_rst_b ),
+
+ .BootFSM_BrkPoint(BootFSM_BrkPoint),
+ .cycleCnt (cycleCnt ),
+
+ .cptra_obf_key (cptra_obf_key ),
+ .cptra_csr_hmac_key (cptra_csr_hmac_key),
+
+ .cptra_uds_rand (cptra_uds_rand ),
+ .cptra_fe_rand (cptra_fe_rand ),
+ .cptra_obf_key_tb(cptra_obf_key_tb),
+
+ .m_axi_bfm_if(m_axi_bfm_if),
+
+ .ready_for_fuses (ready_for_fuses ),
+ .ready_for_mb_processing (ready_for_mb_processing ),
+ .mailbox_data_avail(mailbox_data_avail),
+
+ .ras_test_ctrl(ras_test_ctrl),
+
+ .generic_input_wires(generic_input_wires),
+
+ .cptra_error_fatal(cptra_error_fatal),
+ .cptra_error_non_fatal(cptra_error_non_fatal),
+
+ //Interrupt flags
+ .int_flag(int_flag),
+ .cycleCnt_smpl_en(cycleCnt_smpl_en),
+
+ .assert_hard_rst_flag(assert_hard_rst_flag),
+ .deassert_hard_rst_flag(deassert_hard_rst_flag),
+ .assert_rst_flag_from_service(assert_rst_flag_from_service),
+ .deassert_rst_flag_from_service(deassert_rst_flag_from_service)
+
+);
+
+// JTAG DPI
+jtagdpi #(
+ .Name ("jtag0"),
+ .ListenPort (5000)
+) jtagdpi (
+ .clk_i (core_clk),
+ .rst_ni (cptra_rst_b),
+ .jtag_tck (jtag_tck),
+ .jtag_tms (jtag_tms),
+ .jtag_tdi (jtag_tdi),
+ .jtag_tdo (jtag_tdo),
+ .jtag_trst_n (jtag_trst_n),
+ .jtag_srst_n ()
+);
+
+ //=========================================================================-
+ // DUT instance
+ //=========================================================================-
+caliptra_top caliptra_top_dut (
+ .cptra_pwrgood (cptra_pwrgood),
+ .cptra_rst_b (cptra_rst_b),
+ .clk (core_clk),
+
+ .cptra_obf_key (cptra_obf_key),
+
+ .cptra_csr_hmac_key (cptra_csr_hmac_key),
+
+ .jtag_tck(jtag_tck),
+ .jtag_tdi(jtag_tdi),
+ .jtag_tms(jtag_tms),
+ .jtag_trst_n(jtag_trst_n),
+ .jtag_tdo(jtag_tdo),
+ .jtag_tdoEn(jtag_tdoEn),
+
+ //SoC AXI Interface
+ .s_axi_w_if(m_axi_bfm_if.w_sub),
+ .s_axi_r_if(m_axi_bfm_if.r_sub),
+
+ //AXI DMA Interface
+ .m_axi_w_if(m_axi_if.w_mgr),
+ .m_axi_r_if(m_axi_if.r_mgr),
+
+ .el2_mem_export(el2_mem_export.veer_sram_src),
+
+ .ready_for_fuses(ready_for_fuses),
+ .ready_for_mb_processing(ready_for_mb_processing),
+ .ready_for_runtime(),
+
+ .mbox_sram_cs(mbox_sram_cs),
+ .mbox_sram_we(mbox_sram_we),
+ .mbox_sram_addr(mbox_sram_addr),
+ .mbox_sram_wdata(mbox_sram_wdata),
+ .mbox_sram_rdata(mbox_sram_rdata),
+
+ .imem_cs(imem_cs),
+ .imem_addr(imem_addr),
+ .imem_rdata(imem_rdata),
+
+ .mailbox_data_avail(mailbox_data_avail),
+ .mailbox_flow_done(),
+ .BootFSM_BrkPoint(BootFSM_BrkPoint),
+
+ .recovery_data_avail(1'b1/*TODO*/),
+
+ //SoC Interrupts
+ .cptra_error_fatal (cptra_error_fatal ),
+ .cptra_error_non_fatal(cptra_error_non_fatal),
+
+`ifdef CALIPTRA_INTERNAL_TRNG
+ .etrng_req (etrng_req),
+ .itrng_data (itrng_data),
+ .itrng_valid (itrng_valid),
+`else
+ .etrng_req (),
+ .itrng_data (4'b0),
+ .itrng_valid (1'b0),
+`endif
+
+ // Subsystem mode straps TODO
+ .strap_ss_caliptra_base_addr (64'h0),
+ .strap_ss_mci_base_addr (64'h0),
+ .strap_ss_recovery_ifc_base_addr (64'h0),
+ .strap_ss_otp_fc_base_addr (64'h0),
+ .strap_ss_uds_seed_base_addr (64'h0),
+ .strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset(32'h0),
+ .strap_ss_num_of_prod_debug_unlock_auth_pk_hashes (32'h0),
+ .strap_ss_strap_generic_0 (32'h0),
+ .strap_ss_strap_generic_1 (32'h0),
+ .strap_ss_strap_generic_2 (32'h0),
+ .strap_ss_strap_generic_3 (32'h0),
+ .ss_debug_intent ( 1'b0),
+
+ // Subsystem mode debug outputs
+ .ss_dbg_manuf_enable (/*TODO*/),
+ .ss_soc_dbg_unlock_level(/*TODO*/),
+
+ // Subsystem mode firmware execution control
+ .ss_generic_fw_exec_ctrl(/*TODO*/),
+
+ .generic_input_wires (generic_input_wires),
+ .generic_output_wires( ),
+
+ .security_state(security_state),
+ .scan_mode (scan_mode)
+);
+
+
+`ifdef CALIPTRA_INTERNAL_TRNG
+ //=========================================================================-
+ // Physical RNG used for Internal TRNG
+ //=========================================================================-
+physical_rng physical_rng (
+ .clk (core_clk),
+ .enable (etrng_req),
+ .data (itrng_data),
+ .valid (itrng_valid)
+);
+`endif
+
+ //=========================================================================-
+ // Services for SRAM exports, STDOUT, etc
+ //=========================================================================-
+caliptra_top_tb_services #(
+ .UVM_TB(0)
+) tb_services_i (
+ .clk(core_clk),
+
+ .cptra_rst_b(cptra_rst_b),
+
+ // Caliptra Memory Export Interface
+ .el2_mem_export (el2_mem_export.veer_sram_sink),
+
+ //SRAM interface for mbox
+ .mbox_sram_cs (mbox_sram_cs ),
+ .mbox_sram_we (mbox_sram_we ),
+ .mbox_sram_addr (mbox_sram_addr ),
+ .mbox_sram_wdata(mbox_sram_wdata),
+ .mbox_sram_rdata(mbox_sram_rdata),
+
+ //SRAM interface for imem
+ .imem_cs (imem_cs ),
+ .imem_addr (imem_addr ),
+ .imem_rdata(imem_rdata),
+
+ // Security State
+ .security_state(security_state),
+
+ //Scan mode
+ .scan_mode(scan_mode),
+
+ // TB Controls
+ .ras_test_ctrl(ras_test_ctrl),
+ .cycleCnt(cycleCnt),
+
+ //Interrupt flags
+ .int_flag(int_flag),
+ .cycleCnt_smpl_en(cycleCnt_smpl_en),
+
+ //Reset flags
+ .assert_hard_rst_flag(assert_hard_rst_flag),
+ .deassert_hard_rst_flag(deassert_hard_rst_flag),
+
+ .assert_rst_flag(assert_rst_flag_from_service),
+ .deassert_rst_flag(deassert_rst_flag_from_service),
+
+ .cptra_uds_tb(cptra_uds_rand),
+ .cptra_fe_tb(cptra_fe_rand),
+ .cptra_obf_key_tb(cptra_obf_key_tb)
+
+);
+
+// Dummy interconnect
+always_comb begin
+ // AXI AR
+ axi_sram_if.araddr = m_axi_if.araddr[AXI_SRAM_ADDR_WIDTH-1:0];
+ axi_sram_if.arburst = m_axi_if.arburst;
+ axi_sram_if.arsize = m_axi_if.arsize ;
+ axi_sram_if.arlen = m_axi_if.arlen ;
+ axi_sram_if.aruser = m_axi_if.aruser ;
+ axi_sram_if.arid = m_axi_if.arid ;
+ axi_sram_if.arlock = m_axi_if.arlock ;
+ axi_sram_if.arvalid = m_axi_if.arvalid && m_axi_if.araddr[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH] == AXI_SRAM_BASE_ADDR[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH];
+ m_axi_if.arready = axi_sram_if.arready;
+
+ // AXI R
+ m_axi_if.rdata = axi_sram_if.rdata ;
+ m_axi_if.rresp = axi_sram_if.rresp ;
+ m_axi_if.rid = axi_sram_if.rid ;
+ m_axi_if.rlast = axi_sram_if.rlast ;
+ m_axi_if.rvalid = axi_sram_if.rvalid;
+ axi_sram_if.rready = m_axi_if.rready ;
+
+ // AXI AW
+ axi_sram_if.awaddr = m_axi_if.awaddr[AXI_SRAM_ADDR_WIDTH-1:0];
+ axi_sram_if.awburst = m_axi_if.awburst;
+ axi_sram_if.awsize = m_axi_if.awsize ;
+ axi_sram_if.awlen = m_axi_if.awlen ;
+ axi_sram_if.awuser = m_axi_if.awuser ;
+ axi_sram_if.awid = m_axi_if.awid ;
+ axi_sram_if.awlock = m_axi_if.awlock ;
+ axi_sram_if.awvalid = m_axi_if.awvalid && m_axi_if.awaddr[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH] == AXI_SRAM_BASE_ADDR[`CALIPTRA_AXI_DMA_ADDR_WIDTH-1:AXI_SRAM_ADDR_WIDTH];
+ m_axi_if.awready = axi_sram_if.awready;
+
+ // AXI W
+ axi_sram_if.wdata = m_axi_if.wdata ;
+ axi_sram_if.wstrb = m_axi_if.wstrb ;
+ axi_sram_if.wvalid = m_axi_if.wvalid ;
+ axi_sram_if.wlast = m_axi_if.wlast ;
+ m_axi_if.wready = axi_sram_if.wready ;
+
+ // AXI B
+ m_axi_if.bresp = axi_sram_if.bresp ;
+ m_axi_if.bid = axi_sram_if.bid ;
+ m_axi_if.bvalid = axi_sram_if.bvalid ;
+ axi_sram_if.bready = m_axi_if.bready ;
+end
+
+// Fake "MCU" SRAM block
+caliptra_axi_sram #(
+ .AW(AXI_SRAM_ADDR_WIDTH),
+ .DW(CPTRA_AXI_DMA_DATA_WIDTH),
+ .UW(CPTRA_AXI_DMA_USER_WIDTH),
+ .IW(CPTRA_AXI_DMA_ID_WIDTH),
+ .EX_EN(0)
+) i_axi_sram (
+ .clk(core_clk),
+ .rst_n(cptra_rst_b),
+
+ // AXI INF
+ .s_axi_w_if(axi_sram_if.w_sub),
+ .s_axi_r_if(axi_sram_if.r_sub)
+);
+`ifdef VERILATOR
+initial i_axi_sram.i_sram.ram = '{default:'{default:8'h00}};
+`else
+initial i_axi_sram.i_sram.ram = '{default:8'h00};
+`endif
+
+caliptra_top_sva sva();
+
+endmodule
diff --git a/src/integration/tb/caliptra_top_tb_soc_bfm.sv b/src/integration/tb/caliptra_top_tb_soc_bfm.sv
index ac6320927..2b9edd627 100644
--- a/src/integration/tb/caliptra_top_tb_soc_bfm.sv
+++ b/src/integration/tb/caliptra_top_tb_soc_bfm.sv
@@ -40,7 +40,7 @@ import caliptra_top_tb_pkg::*; #(
axi_if m_axi_bfm_if,
input logic ready_for_fuses,
- input logic ready_for_fw_push,
+ input logic ready_for_mb_processing,
input logic mailbox_data_avail,
input var ras_test_ctrl_t ras_test_ctrl,
@@ -240,10 +240,10 @@ import caliptra_top_tb_pkg::*; #(
$display ("CLP: ROM Flow in progress...\n");
// Test sequence (Mailbox or error handling)
- wait(ready_for_fw_push || ras_test_ctrl.error_injection_seen);
+ wait(ready_for_mb_processing || ras_test_ctrl.error_injection_seen);
// Mailbox flow
- if (ready_for_fw_push) begin
+ if (ready_for_mb_processing) begin
for (int rpt=0; rpt<5; rpt++) @(posedge core_clk);
$display ("CLP: Ready for firmware push\n");
diff --git a/src/integration/test_suites/caliptra_demo/caliptra_demo.c b/src/integration/test_suites/caliptra_demo/caliptra_demo.c
index 67b215aeb..3291b7dc9 100644
--- a/src/integration/test_suites/caliptra_demo/caliptra_demo.c
+++ b/src/integration/test_suites/caliptra_demo/caliptra_demo.c
@@ -267,7 +267,7 @@ void mbox_fw() {
uint32_t data;
//set ready for FW
- lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+ lsu_write_32(CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
// Roughly equivalent to .rept 99 "nop" since the loop requires 3 (5?) ops each iteration
// nop
diff --git a/src/integration/test_suites/caliptra_top/caliptra_top.c b/src/integration/test_suites/caliptra_top/caliptra_top.c
index 05991172c..4ff1a514e 100644
--- a/src/integration/test_suites/caliptra_top/caliptra_top.c
+++ b/src/integration/test_suites/caliptra_top/caliptra_top.c
@@ -81,7 +81,7 @@ void main() {
doe_init(iv_data_uds, iv_data_fe, 0x6); // TODO replace 0x6 with entry indicators
VPRINTF(LOW, "Setting Flow Status\n");
- soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+ soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
VPRINTF(LOW, "Unlocking SHA512-ACC\n");
// Clear SHA accelerator lock (FIPS requirement)
@@ -150,7 +150,7 @@ void main() {
}
// Clear 'ready for fw'
- soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+ soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
// Jump to ICCM (this is the FMC image, a.k.a. Section 0)
VPRINTF(LOW, "FMC FW loaded into ICCM - jumping there \n");
@@ -177,7 +177,7 @@ void main() {
// skip doe_init
// Ready for FW (need to reload the FMC)
- soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+ soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
// Clear SHA accelerator lock (FIPS requirement)
soc_ifc_w1clr_sha_lock_field(SHA512_ACC_CSR_LOCK_LOCK_MASK);
@@ -217,7 +217,7 @@ void main() {
}
// Clear 'ready for fw'
- soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+ soc_ifc_clr_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
// Jump to ICCM (this is the FMC image, a.k.a. Section 0)
iccm_fmc();
diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c
index 5fdb4a9aa..761d94de7 100644
--- a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c
+++ b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating.c
@@ -123,7 +123,7 @@ void main() {
: "i" (0x304), "r" (mie_machinetimer_en) /* input : immediate */ \
: /* clobbers: none */);
- *soc_ifc_flow_status = SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK;
+ *soc_ifc_flow_status = SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK;
//Halt the core
__asm__ volatile ("csrwi %0, %1" \
diff --git a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s
index 29fdaecfc..d508e8d3d 100644
--- a/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s
+++ b/src/integration/test_suites/smoke_test_clk_gating/smoke_test_clk_gating_asm.s
@@ -124,7 +124,7 @@ _start:
//TODO: how to write a dword in asm
//Trigger APB tx
li x3, CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS
- li x4, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK
+ li x4, SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK
//sb x5, 0(x3)
loop1:
diff --git a/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c b/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c
index 54cf50f46..571364869 100644
--- a/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c
+++ b/src/integration/test_suites/smoke_test_mbox/smoke_test_mbox.c
@@ -53,7 +53,7 @@ void main () {
VPRINTF(LOW, "----------------------------------\n");
//set ready for FW so tb will push FW
- soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+ soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
// Sleep
for (uint16_t slp = 0; slp < 33; slp++);
diff --git a/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c
index a31b2facc..159d355e5 100644
--- a/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c
+++ b/src/integration/test_suites/smoke_test_mbox_cg/smoke_test_mbox_cg.c
@@ -119,7 +119,7 @@ void main () {
SEND_STDOUT_CTRL(0xf2);
//set ready for FW so tb will push FW
- soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK);
+ soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK);
set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);
diff --git a/src/soc_ifc/coverage/soc_ifc_cov_if.sv b/src/soc_ifc/coverage/soc_ifc_cov_if.sv
index fec38befd..0d3702126 100644
--- a/src/soc_ifc/coverage/soc_ifc_cov_if.sv
+++ b/src/soc_ifc/coverage/soc_ifc_cov_if.sv
@@ -581,6 +581,38 @@ interface soc_ifc_cov_if
assign full_addr_CPTRA_RSVD_REG[0] = `CLP_SOC_IFC_REG_CPTRA_RSVD_REG_0;
assign full_addr_CPTRA_RSVD_REG[1] = `CLP_SOC_IFC_REG_CPTRA_RSVD_REG_1;
+ logic hit_CPTRA_HW_CAPABILITIES;
+ logic [3:0] bus_CPTRA_HW_CAPABILITIES;
+ logic [31:0] full_addr_CPTRA_HW_CAPABILITIES = `CLP_SOC_IFC_REG_CPTRA_HW_CAPABILITIES;
+
+ logic hit_CPTRA_FW_CAPABILITIES;
+ logic [3:0] bus_CPTRA_FW_CAPABILITIES;
+ logic [31:0] full_addr_CPTRA_FW_CAPABILITIES = `CLP_SOC_IFC_REG_CPTRA_FW_CAPABILITIES;
+
+ logic hit_CPTRA_CAP_LOCK;
+ logic [3:0] bus_CPTRA_CAP_LOCK;
+ logic [31:0] full_addr_CPTRA_CAP_LOCK = `CLP_SOC_IFC_REG_CPTRA_CAP_LOCK;
+
+ logic hit_CPTRA_OWNER_PK_HASH[0:11];
+ logic [3:0] bus_CPTRA_OWNER_PK_HASH[0:11];
+ logic [31:0] full_addr_CPTRA_OWNER_PK_HASH[0:11];
+ assign full_addr_CPTRA_OWNER_PK_HASH[0] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0;
+ assign full_addr_CPTRA_OWNER_PK_HASH[1] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_1;
+ assign full_addr_CPTRA_OWNER_PK_HASH[2] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_2;
+ assign full_addr_CPTRA_OWNER_PK_HASH[3] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_3;
+ assign full_addr_CPTRA_OWNER_PK_HASH[4] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_4;
+ assign full_addr_CPTRA_OWNER_PK_HASH[5] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_5;
+ assign full_addr_CPTRA_OWNER_PK_HASH[6] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_6;
+ assign full_addr_CPTRA_OWNER_PK_HASH[7] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_7;
+ assign full_addr_CPTRA_OWNER_PK_HASH[8] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_8;
+ assign full_addr_CPTRA_OWNER_PK_HASH[9] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_9;
+ assign full_addr_CPTRA_OWNER_PK_HASH[10] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_10;
+ assign full_addr_CPTRA_OWNER_PK_HASH[11] = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_11;
+
+ logic hit_CPTRA_OWNER_PK_HASH_LOCK;
+ logic [3:0] bus_CPTRA_OWNER_PK_HASH_LOCK;
+ logic [31:0] full_addr_CPTRA_OWNER_PK_HASH_LOCK = `CLP_SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK;
+
logic hit_fuse_uds_seed[0:11];
logic [3:0] bus_fuse_uds_seed[0:11];
logic [31:0] full_addr_fuse_uds_seed[0:11];
@@ -625,25 +657,17 @@ interface soc_ifc_cov_if
assign full_addr_fuse_key_manifest_pk_hash[10] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_10;
assign full_addr_fuse_key_manifest_pk_hash[11] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_11;
- logic hit_fuse_key_manifest_pk_hash_mask;
- logic [3:0] bus_fuse_key_manifest_pk_hash_mask;
- logic [31:0] full_addr_fuse_key_manifest_pk_hash_mask = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK;
-
- logic hit_fuse_owner_pk_hash[0:11];
- logic [3:0] bus_fuse_owner_pk_hash[0:11];
- logic [31:0] full_addr_fuse_owner_pk_hash[0:11];
- assign full_addr_fuse_owner_pk_hash[0] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_0;
- assign full_addr_fuse_owner_pk_hash[1] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_1;
- assign full_addr_fuse_owner_pk_hash[2] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_2;
- assign full_addr_fuse_owner_pk_hash[3] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_3;
- assign full_addr_fuse_owner_pk_hash[4] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_4;
- assign full_addr_fuse_owner_pk_hash[5] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_5;
- assign full_addr_fuse_owner_pk_hash[6] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_6;
- assign full_addr_fuse_owner_pk_hash[7] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_7;
- assign full_addr_fuse_owner_pk_hash[8] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_8;
- assign full_addr_fuse_owner_pk_hash[9] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_9;
- assign full_addr_fuse_owner_pk_hash[10] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_10;
- assign full_addr_fuse_owner_pk_hash[11] = `CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_11;
+ logic hit_fuse_key_manifest_pk_hash_mask[0:7];
+ logic [3:0] bus_fuse_key_manifest_pk_hash_mask[0:7];
+ logic [31:0] full_addr_fuse_key_manifest_pk_hash_mask[0:7];
+ assign full_addr_fuse_key_manifest_pk_hash_mask[0] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0;
+ assign full_addr_fuse_key_manifest_pk_hash_mask[1] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1;
+ assign full_addr_fuse_key_manifest_pk_hash_mask[2] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2;
+ assign full_addr_fuse_key_manifest_pk_hash_mask[3] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3;
+ assign full_addr_fuse_key_manifest_pk_hash_mask[4] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4;
+ assign full_addr_fuse_key_manifest_pk_hash_mask[5] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5;
+ assign full_addr_fuse_key_manifest_pk_hash_mask[6] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6;
+ assign full_addr_fuse_key_manifest_pk_hash_mask[7] = `CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7;
logic hit_fuse_fmc_key_manifest_svn;
logic [3:0] bus_fuse_fmc_key_manifest_svn;
@@ -697,18 +721,14 @@ interface soc_ifc_cov_if
assign full_addr_fuse_idevid_manuf_hsm_id[2] = `CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_2;
assign full_addr_fuse_idevid_manuf_hsm_id[3] = `CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_3;
- logic hit_fuse_life_cycle;
- logic [3:0] bus_fuse_life_cycle;
- logic [31:0] full_addr_fuse_life_cycle = `CLP_SOC_IFC_REG_FUSE_LIFE_CYCLE;
-
- logic hit_fuse_lms_verify;
- logic [3:0] bus_fuse_lms_verify;
- logic [31:0] full_addr_fuse_lms_verify = `CLP_SOC_IFC_REG_FUSE_LMS_VERIFY;
-
logic hit_fuse_lms_revocation;
logic [3:0] bus_fuse_lms_revocation;
logic [31:0] full_addr_fuse_lms_revocation = `CLP_SOC_IFC_REG_FUSE_LMS_REVOCATION;
+ logic hit_fuse_mldsa_revocation;
+ logic [3:0] bus_fuse_mldsa_revocation;
+ logic [31:0] full_addr_fuse_mldsa_revocation = `CLP_SOC_IFC_REG_FUSE_MLDSA_REVOCATION;
+
logic hit_fuse_soc_stepping_id;
logic [3:0] bus_fuse_soc_stepping_id;
logic [31:0] full_addr_fuse_soc_stepping_id = `CLP_SOC_IFC_REG_FUSE_SOC_STEPPING_ID;
@@ -1136,6 +1156,54 @@ interface soc_ifc_cov_if
assign hit_CPTRA_RSVD_REG[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_RSVD_REG[1][18-1:0]);
assign bus_CPTRA_RSVD_REG[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_RSVD_REG[1]}};
+ assign hit_CPTRA_HW_CAPABILITIES = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_HW_CAPABILITIES[AXI_ADDR_WIDTH-1:0]);
+ assign bus_CPTRA_HW_CAPABILITIES = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_HW_CAPABILITIES}};
+
+ assign hit_CPTRA_FW_CAPABILITIES = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_FW_CAPABILITIES[AXI_ADDR_WIDTH-1:0]);
+ assign bus_CPTRA_FW_CAPABILITIES = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_FW_CAPABILITIES}};
+
+ assign hit_CPTRA_CAP_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_CAP_LOCK[AXI_ADDR_WIDTH-1:0]);
+ assign bus_CPTRA_CAP_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_CAP_LOCK}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[0] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[0][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[0]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[1] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[1][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[1]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[2] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[2][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[2]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[3] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[3][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[3]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[4] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[4][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[4]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[5] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[5][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[5]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[6] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[6][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[6]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[7] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[7][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[7]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[8] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[8][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[8]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[9] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[9][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[9]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[10] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[10][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[10]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH[11] = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH[11][18-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH[11]}};
+
+ assign hit_CPTRA_OWNER_PK_HASH_LOCK = (soc_ifc_reg_req_data.addr == full_addr_CPTRA_OWNER_PK_HASH_LOCK[AXI_ADDR_WIDTH-1:0]);
+ assign bus_CPTRA_OWNER_PK_HASH_LOCK = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_CPTRA_OWNER_PK_HASH_LOCK}};
+
assign hit_fuse_uds_seed[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_uds_seed[0][18-1:0]);
assign bus_fuse_uds_seed[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_uds_seed[0]}};
@@ -1232,44 +1300,29 @@ interface soc_ifc_cov_if
assign hit_fuse_key_manifest_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash[11][18-1:0]);
assign bus_fuse_key_manifest_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash[11]}};
- assign hit_fuse_key_manifest_pk_hash_mask = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[AXI_ADDR_WIDTH-1:0]);
- assign bus_fuse_key_manifest_pk_hash_mask = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask}};
-
- assign hit_fuse_owner_pk_hash[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[0][18-1:0]);
- assign bus_fuse_owner_pk_hash[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[0]}};
-
- assign hit_fuse_owner_pk_hash[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[1][18-1:0]);
- assign bus_fuse_owner_pk_hash[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[1]}};
-
- assign hit_fuse_owner_pk_hash[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[2][18-1:0]);
- assign bus_fuse_owner_pk_hash[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[2]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[0] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[0][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[0] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[0]}};
- assign hit_fuse_owner_pk_hash[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[3][18-1:0]);
- assign bus_fuse_owner_pk_hash[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[3]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[1] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[1][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[1] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[1]}};
- assign hit_fuse_owner_pk_hash[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[4][18-1:0]);
- assign bus_fuse_owner_pk_hash[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[4]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[2] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[2][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[2] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[2]}};
- assign hit_fuse_owner_pk_hash[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[5][18-1:0]);
- assign bus_fuse_owner_pk_hash[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[5]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[3][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[3]}};
- assign hit_fuse_owner_pk_hash[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[6][18-1:0]);
- assign bus_fuse_owner_pk_hash[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[6]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[4] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[4][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[4] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[4]}};
- assign hit_fuse_owner_pk_hash[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[7][18-1:0]);
- assign bus_fuse_owner_pk_hash[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[7]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[5] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[5][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[5] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[5]}};
- assign hit_fuse_owner_pk_hash[8] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[8][18-1:0]);
- assign bus_fuse_owner_pk_hash[8] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[8]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[6] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[6][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[6] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[6]}};
- assign hit_fuse_owner_pk_hash[9] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[9][18-1:0]);
- assign bus_fuse_owner_pk_hash[9] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[9]}};
-
- assign hit_fuse_owner_pk_hash[10] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[10][18-1:0]);
- assign bus_fuse_owner_pk_hash[10] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[10]}};
-
- assign hit_fuse_owner_pk_hash[11] = (soc_ifc_reg_req_data.addr == full_addr_fuse_owner_pk_hash[11][18-1:0]);
- assign bus_fuse_owner_pk_hash[11] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_owner_pk_hash[11]}};
+ assign hit_fuse_key_manifest_pk_hash_mask[7] = (soc_ifc_reg_req_data.addr == full_addr_fuse_key_manifest_pk_hash_mask[7][AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_key_manifest_pk_hash_mask[7] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_key_manifest_pk_hash_mask[7]}};
assign hit_fuse_fmc_key_manifest_svn = (soc_ifc_reg_req_data.addr == full_addr_fuse_fmc_key_manifest_svn[AXI_ADDR_WIDTH-1:0]);
assign bus_fuse_fmc_key_manifest_svn = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_fmc_key_manifest_svn}};
@@ -1373,15 +1426,12 @@ interface soc_ifc_cov_if
assign hit_fuse_idevid_manuf_hsm_id[3] = (soc_ifc_reg_req_data.addr == full_addr_fuse_idevid_manuf_hsm_id[3][18-1:0]);
assign bus_fuse_idevid_manuf_hsm_id[3] = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_idevid_manuf_hsm_id[3]}};
- assign hit_fuse_life_cycle = (soc_ifc_reg_req_data.addr == full_addr_fuse_life_cycle[AXI_ADDR_WIDTH-1:0]);
- assign bus_fuse_life_cycle = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_life_cycle}};
-
- assign hit_fuse_lms_verify = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_verify[AXI_ADDR_WIDTH-1:0]);
- assign bus_fuse_lms_verify = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_verify}};
-
assign hit_fuse_lms_revocation = (soc_ifc_reg_req_data.addr == full_addr_fuse_lms_revocation[AXI_ADDR_WIDTH-1:0]);
assign bus_fuse_lms_revocation = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_lms_revocation}};
+ assign hit_fuse_mldsa_revocation = (soc_ifc_reg_req_data.addr == full_addr_fuse_mldsa_revocation[AXI_ADDR_WIDTH-1:0]);
+ assign bus_fuse_mldsa_revocation = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_mldsa_revocation}};
+
assign hit_fuse_soc_stepping_id = (soc_ifc_reg_req_data.addr == full_addr_fuse_soc_stepping_id[AXI_ADDR_WIDTH-1:0]);
assign bus_fuse_soc_stepping_id = {uc_rd, uc_wr, soc_rd, soc_wr} & {4{hit_fuse_soc_stepping_id}};
@@ -2084,6 +2134,106 @@ interface soc_ifc_cov_if
}
endgroup
+ // ----------------------- COVERGROUP CPTRA_HW_CAPABILITIES -----------------------
+ covergroup soc_ifc_CPTRA_HW_CAPABILITIES_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+ CPTRA_HW_CAPABILITIES_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_HW_CAPABILITIES;
+ bus_CPTRA_HW_CAPABILITIES_cp : coverpoint bus_event[0] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP CPTRA_FW_CAPABILITIES -----------------------
+ covergroup soc_ifc_CPTRA_FW_CAPABILITIES_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+ CPTRA_FW_CAPABILITIES_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_FW_CAPABILITIES;
+ bus_CPTRA_FW_CAPABILITIES_cp : coverpoint bus_event[0] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP CPTRA_CAP_LOCK -----------------------
+ covergroup soc_ifc_CPTRA_CAP_LOCK_cg (ref logic [3:0] bus_event[0:1]) @(posedge clk);
+ CPTRA_CAP_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_CAP_LOCK;
+ bus_CPTRA_CAP_LOCK_cp : coverpoint bus_event[0] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP CPTRA_OWNER_PK_HASH [0:11] -----------------------
+ covergroup soc_ifc_CPTRA_OWNER_PK_HASH_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
+ CPTRA_OWNER_PK_HASH0_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[0];
+ bus_CPTRA_OWNER_PK_HASH0_cp : coverpoint bus_event[0] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH1_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[1];
+ bus_CPTRA_OWNER_PK_HASH1_cp : coverpoint bus_event[1] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH2_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[2];
+ bus_CPTRA_OWNER_PK_HASH2_cp : coverpoint bus_event[2] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH3_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[3];
+ bus_CPTRA_OWNER_PK_HASH3_cp : coverpoint bus_event[3] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH4_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[4];
+ bus_CPTRA_OWNER_PK_HASH4_cp : coverpoint bus_event[4] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH5_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[5];
+ bus_CPTRA_OWNER_PK_HASH5_cp : coverpoint bus_event[5] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH6_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[6];
+ bus_CPTRA_OWNER_PK_HASH6_cp : coverpoint bus_event[6] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH7_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[7];
+ bus_CPTRA_OWNER_PK_HASH7_cp : coverpoint bus_event[7] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH8_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[8];
+ bus_CPTRA_OWNER_PK_HASH8_cp : coverpoint bus_event[8] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH9_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[9];
+ bus_CPTRA_OWNER_PK_HASH9_cp : coverpoint bus_event[9] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH10_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[10];
+ bus_CPTRA_OWNER_PK_HASH10_cp : coverpoint bus_event[10] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ CPTRA_OWNER_PK_HASH11_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH[11];
+ bus_CPTRA_OWNER_PK_HASH11_cp : coverpoint bus_event[11] {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
+ // ----------------------- COVERGROUP CPTRA_OWNER_PK_HASH_LOCK -----------------------
+ covergroup soc_ifc_CPTRA_OWNER_PK_HASH_LOCK_cg (ref logic [3:0] bus_event) @(posedge clk);
+ CPTRA_OWNER_PK_HASH_LOCK_cp : coverpoint i_soc_ifc_reg.field_storage.CPTRA_OWNER_PK_HASH_LOCK;
+ bus_CPTRA_OWNER_PK_HASH_LOCK_cp : coverpoint bus_event {
+ bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
+ ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
+ }
+ endgroup
+
// ----------------------- COVERGROUP fuse_uds_seed [0:11] -----------------------
covergroup soc_ifc_fuse_uds_seed_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
fuse_uds_seed0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_uds_seed[0];
@@ -2265,70 +2415,6 @@ interface soc_ifc_cov_if
}
endgroup
- // ----------------------- COVERGROUP fuse_owner_pk_hash [0:11] -----------------------
- covergroup soc_ifc_fuse_owner_pk_hash_cg (ref logic [3:0] bus_event[0:11]) @(posedge clk);
- fuse_owner_pk_hash0_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[0];
- bus_fuse_owner_pk_hash0_cp : coverpoint bus_event[0] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash1_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[1];
- bus_fuse_owner_pk_hash1_cp : coverpoint bus_event[1] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash2_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[2];
- bus_fuse_owner_pk_hash2_cp : coverpoint bus_event[2] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash3_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[3];
- bus_fuse_owner_pk_hash3_cp : coverpoint bus_event[3] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash4_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[4];
- bus_fuse_owner_pk_hash4_cp : coverpoint bus_event[4] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash5_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[5];
- bus_fuse_owner_pk_hash5_cp : coverpoint bus_event[5] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash6_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[6];
- bus_fuse_owner_pk_hash6_cp : coverpoint bus_event[6] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash7_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[7];
- bus_fuse_owner_pk_hash7_cp : coverpoint bus_event[7] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash8_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[8];
- bus_fuse_owner_pk_hash8_cp : coverpoint bus_event[8] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash9_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[9];
- bus_fuse_owner_pk_hash9_cp : coverpoint bus_event[9] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash10_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[10];
- bus_fuse_owner_pk_hash10_cp : coverpoint bus_event[10] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- fuse_owner_pk_hash11_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_owner_pk_hash[11];
- bus_fuse_owner_pk_hash11_cp : coverpoint bus_event[11] {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- endgroup
-
// ----------------------- COVERGROUP fuse_fmc_key_manifest_svn -----------------------
covergroup soc_ifc_fuse_fmc_key_manifest_svn_cg (ref logic [3:0] bus_event) @(posedge clk);
fuse_fmc_key_manifest_svn_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_fmc_key_manifest_svn;
@@ -2519,28 +2605,19 @@ interface soc_ifc_cov_if
}
endgroup
- // ----------------------- COVERGROUP fuse_life_cycle -----------------------
- covergroup soc_ifc_fuse_life_cycle_cg (ref logic [3:0] bus_event) @(posedge clk);
- fuse_life_cycle_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_life_cycle;
- bus_fuse_life_cycle_cp : coverpoint bus_event {
- bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
- ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
- }
- endgroup
-
- // ----------------------- COVERGROUP fuse_lms_verify -----------------------
- covergroup soc_ifc_fuse_lms_verify_cg (ref logic [3:0] bus_event) @(posedge clk);
- fuse_lms_verify_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_verify;
- bus_fuse_lms_verify_cp : coverpoint bus_event {
+ // ----------------------- COVERGROUP fuse_lms_revocation -----------------------
+ covergroup soc_ifc_fuse_lms_revocation_cg (ref logic [3:0] bus_event) @(posedge clk);
+ fuse_lms_revocation_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_revocation;
+ bus_fuse_lms_revocation_cp : coverpoint bus_event {
bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
}
endgroup
- // ----------------------- COVERGROUP fuse_lms_revocation -----------------------
- covergroup soc_ifc_fuse_lms_revocation_cg (ref logic [3:0] bus_event) @(posedge clk);
- fuse_lms_revocation_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_lms_revocation;
- bus_fuse_lms_revocation_cp : coverpoint bus_event {
+ // ----------------------- COVERGROUP fuse_mldsa_revocation -----------------------
+ covergroup soc_ifc_fuse_mldsa_revocation_cg (ref logic [3:0] bus_event) @(posedge clk);
+ fuse_mldsa_revocation_cp : coverpoint i_soc_ifc_reg.field_storage.fuse_mldsa_revocation;
+ bus_fuse_mldsa_revocation_cp : coverpoint bus_event {
bins wr_rd[] = (AHB_WR, AXI_WR => IDLE [*1:1000] => AHB_RD, AXI_RD);
ignore_bins dont_care = {IDLE, 4'hf, (AXI_RD | AXI_WR), (AHB_RD | AHB_WR)};
}
@@ -3066,19 +3143,22 @@ interface soc_ifc_cov_if
soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_0_cg CPTRA_iTRNG_ENTROPY_CONFIG_0_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_0);
soc_ifc_CPTRA_iTRNG_ENTROPY_CONFIG_1_cg CPTRA_iTRNG_ENTROPY_CONFIG_1_cg = new(bus_CPTRA_iTRNG_ENTROPY_CONFIG_1);
soc_ifc_CPTRA_RSVD_REG_cg CPTRA_RSVD_REG_cg = new(bus_CPTRA_RSVD_REG);
+ soc_ifc_CPTRA_HW_CAPABILITIES_cg CPTRA_HW_CAPABILITIES_cg = new(bus_CPTRA_HW_CAPABILITIES);
+ soc_ifc_CPTRA_FW_CAPABILITIES_cg CPTRA_FW_CAPABILITIES_cg = new(bus_CPTRA_FW_CAPABILITIES);
+ soc_ifc_CPTRA_CAP_LOCK_cg CPTRA_CAP_LOCK_cg = new(bus_CPTRA_CAP_LOCK);
+ soc_ifc_CPTRA_OWNER_PK_HASH_cg CPTRA_OWNER_PK_HASH_cg = new(bus_CPTRA_OWNER_PK_HASH);
+ soc_ifc_CPTRA_OWNER_PK_HASH_LOCK_cg CPTRA_OWNER_PK_HASH_LOCK_cg = new(bus_CPTRA_OWNER_PK_HASH_LOCK);
soc_ifc_fuse_uds_seed_cg fuse_uds_seed_cg = new(bus_fuse_uds_seed);
soc_ifc_fuse_field_entropy_cg fuse_field_entropy_cg = new(bus_fuse_field_entropy);
soc_ifc_fuse_key_manifest_pk_hash_cg fuse_key_manifest_pk_hash_cg = new(bus_fuse_key_manifest_pk_hash);
soc_ifc_fuse_key_manifest_pk_hash_mask_cg fuse_key_manifest_pk_hash_mask_cg = new(bus_fuse_key_manifest_pk_hash_mask);
- soc_ifc_fuse_owner_pk_hash_cg fuse_owner_pk_hash_cg = new(bus_fuse_owner_pk_hash);
soc_ifc_fuse_fmc_key_manifest_svn_cg fuse_fmc_key_manifest_svn_cg = new(bus_fuse_fmc_key_manifest_svn);
soc_ifc_fuse_runtime_svn_cg fuse_runtime_svn_cg = new(bus_fuse_runtime_svn);
soc_ifc_fuse_anti_rollback_disable_cg fuse_anti_rollback_disable_cg = new(bus_fuse_anti_rollback_disable);
soc_ifc_fuse_idevid_cert_attr_cg fuse_idevid_cert_attr_cg = new(bus_fuse_idevid_cert_attr);
soc_ifc_fuse_idevid_manuf_hsm_id_cg fuse_idevid_manuf_hsm_id_cg = new(bus_fuse_idevid_manuf_hsm_id);
- soc_ifc_fuse_life_cycle_cg fuse_life_cycle_cg = new(bus_fuse_life_cycle);
- soc_ifc_fuse_lms_verify_cg fuse_lms_verify_cg = new(bus_fuse_lms_verify);
soc_ifc_fuse_lms_revocation_cg fuse_lms_revocation_cg = new(bus_fuse_lms_revocation);
+ soc_ifc_fuse_mldsa_revocation_cg fuse_mldsa_revocation_cg = new(bus_fuse_mldsa_revocation);
soc_ifc_fuse_soc_stepping_id_cg fuse_soc_stepping_id_cg = new(bus_fuse_soc_stepping_id);
soc_ifc_internal_obf_key_cg internal_obf_key_cg = new(bus_internal_obf_key);
soc_ifc_internal_iccm_lock_cg internal_iccm_lock_cg = new(bus_internal_iccm_lock);
diff --git a/src/soc_ifc/rtl/caliptra_top_reg.h b/src/soc_ifc/rtl/caliptra_top_reg.h
index 758457eb6..9edf50d39 100644
--- a/src/soc_ifc/rtl/caliptra_top_reg.h
+++ b/src/soc_ifc/rtl/caliptra_top_reg.h
@@ -54,71 +54,10 @@
#define MBOX_CSR_MBOX_UNLOCK (0x20)
#define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0)
#define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (0x1)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_BASE_ADDR (0x30021000)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_LOCK (0x30021000)
-#define SHA512_ACC_CSR_LOCK (0x0)
-#define SHA512_ACC_CSR_LOCK_LOCK_LOW (0)
-#define SHA512_ACC_CSR_LOCK_LOCK_MASK (0x1)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_ID (0x30021004)
-#define SHA512_ACC_CSR_ID (0x4)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_MODE (0x30021008)
-#define SHA512_ACC_CSR_MODE (0x8)
-#define SHA512_ACC_CSR_MODE_MODE_LOW (0)
-#define SHA512_ACC_CSR_MODE_MODE_MASK (0x3)
-#define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_LOW (2)
-#define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_MASK (0x4)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_START_ADDRESS (0x3002100c)
-#define SHA512_ACC_CSR_START_ADDRESS (0xc)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DLEN (0x30021010)
-#define SHA512_ACC_CSR_DLEN (0x10)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DATAIN (0x30021014)
-#define SHA512_ACC_CSR_DATAIN (0x14)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_EXECUTE (0x30021018)
-#define SHA512_ACC_CSR_EXECUTE (0x18)
-#define SHA512_ACC_CSR_EXECUTE_EXECUTE_LOW (0)
-#define SHA512_ACC_CSR_EXECUTE_EXECUTE_MASK (0x1)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_STATUS (0x3002101c)
-#define SHA512_ACC_CSR_STATUS (0x1c)
-#define SHA512_ACC_CSR_STATUS_VALID_LOW (0)
-#define SHA512_ACC_CSR_STATUS_VALID_MASK (0x1)
-#define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW (1)
-#define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK (0x2)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_0 (0x30021020)
-#define SHA512_ACC_CSR_DIGEST_0 (0x20)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_1 (0x30021024)
-#define SHA512_ACC_CSR_DIGEST_1 (0x24)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_2 (0x30021028)
-#define SHA512_ACC_CSR_DIGEST_2 (0x28)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_3 (0x3002102c)
-#define SHA512_ACC_CSR_DIGEST_3 (0x2c)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_4 (0x30021030)
-#define SHA512_ACC_CSR_DIGEST_4 (0x30)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_5 (0x30021034)
-#define SHA512_ACC_CSR_DIGEST_5 (0x34)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_6 (0x30021038)
-#define SHA512_ACC_CSR_DIGEST_6 (0x38)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_7 (0x3002103c)
-#define SHA512_ACC_CSR_DIGEST_7 (0x3c)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_8 (0x30021040)
-#define SHA512_ACC_CSR_DIGEST_8 (0x40)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_9 (0x30021044)
-#define SHA512_ACC_CSR_DIGEST_9 (0x44)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_10 (0x30021048)
-#define SHA512_ACC_CSR_DIGEST_10 (0x48)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_11 (0x3002104c)
-#define SHA512_ACC_CSR_DIGEST_11 (0x4c)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_12 (0x30021050)
-#define SHA512_ACC_CSR_DIGEST_12 (0x50)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_13 (0x30021054)
-#define SHA512_ACC_CSR_DIGEST_13 (0x54)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_14 (0x30021058)
-#define SHA512_ACC_CSR_DIGEST_14 (0x58)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_15 (0x3002105c)
-#define SHA512_ACC_CSR_DIGEST_15 (0x5c)
-#define CALIPTRA_TOP_REG_SHA512_ACC_CSR_CONTROL (0x30021060)
-#define SHA512_ACC_CSR_CONTROL (0x60)
-#define SHA512_ACC_CSR_CONTROL_ZEROIZE_LOW (0)
-#define SHA512_ACC_CSR_CONTROL_ZEROIZE_MASK (0x1)
+#define CALIPTRA_TOP_REG_MBOX_CSR_TAP_MODE (0x30020024)
+#define MBOX_CSR_TAP_MODE (0x24)
+#define MBOX_CSR_TAP_MODE_ENABLED_LOW (0)
+#define MBOX_CSR_TAP_MODE_ENABLED_MASK (0x1)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR (0x30030000)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (0x30030000)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (0x0)
@@ -130,6 +69,8 @@
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (0x4)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (0x8)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (0xfffffff0)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (0x30030004)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (0x4)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0)
@@ -138,6 +79,8 @@
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (0x2)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (0x4)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (0xfffffff8)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (0x30030008)
#define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (0x8)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (0x3003000c)
@@ -172,8 +115,8 @@
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (0x1000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (0xe000000)
-#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
-#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (0x10000000)
+#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
+#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (0x10000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (0x20000000)
#define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
@@ -304,14 +247,12 @@
#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (0xe0)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (0x1)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW (1)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK (0x2)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_LOW (2)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (0x4)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3)
-#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK (0x8)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (0xe)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4)
#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (0x10)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (0x20)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0x300300e4)
#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (0xe4)
#define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0)
@@ -368,6 +309,42 @@
#define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (0x120)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (0x30030124)
#define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (0x124)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (0x30030128)
+#define GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (0x128)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (0x3003012c)
+#define GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (0x12c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (0x30030130)
+#define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (0x130)
+#define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_LOW (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_MASK (0x1)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (0x30030140)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (0x140)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (0x30030144)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (0x144)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (0x30030148)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (0x148)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (0x3003014c)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (0x14c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (0x30030150)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (0x150)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (0x30030154)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (0x154)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (0x30030158)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (0x158)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (0x3003015c)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (0x15c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (0x30030160)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (0x160)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (0x30030164)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (0x164)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (0x30030168)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (0x168)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (0x3003016c)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (0x16c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (0x30030170)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (0x170)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0)
+#define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (0x1)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (0x30030200)
#define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (0x200)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (0x30030204)
@@ -440,118 +417,190 @@
#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (0x288)
#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x3003028c)
#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (0x28c)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x30030290)
-#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (0x290)
-#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0)
-#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (0xf)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_0 (0x30030294)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_0 (0x294)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_1 (0x30030298)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_1 (0x298)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_2 (0x3003029c)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_2 (0x29c)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_3 (0x300302a0)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_3 (0x2a0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_4 (0x300302a4)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_4 (0x2a4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_5 (0x300302a8)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_5 (0x2a8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_6 (0x300302ac)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_6 (0x2ac)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_7 (0x300302b0)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_7 (0x2b0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_8 (0x300302b4)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_8 (0x2b4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_9 (0x300302b8)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_9 (0x2b8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_10 (0x300302bc)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_10 (0x2bc)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_11 (0x300302c0)
-#define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_11 (0x2c0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x300302c4)
-#define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2c4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x300302c8)
-#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x2c8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (0x300302cc)
-#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (0x2cc)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (0x300302d0)
-#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (0x2d0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (0x300302d4)
-#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (0x2d4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x300302d8)
-#define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x2d8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x30030290)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (0x290)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x30030294)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (0x294)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x30030298)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (0x298)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x3003029c)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (0x29c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x300302a0)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (0x2a0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x300302a4)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (0x2a4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x300302a8)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (0x2a8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x300302ac)
+#define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (0x2ac)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x300302b4)
+#define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (0x2b4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x300302b8)
+#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (0x2b8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (0x300302bc)
+#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (0x2bc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (0x300302c0)
+#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (0x2c0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (0x300302c4)
+#define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (0x2c4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x300302c8)
+#define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (0x2c8)
#define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0)
#define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (0x300302dc)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (0x2dc)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (0x300302e0)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (0x2e0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (0x300302e4)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (0x2e4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (0x300302e8)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (0x2e8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (0x300302ec)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (0x2ec)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (0x300302f0)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (0x2f0)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (0x300302f4)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (0x2f4)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (0x300302f8)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (0x2f8)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (0x300302fc)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (0x2fc)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (0x30030300)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (0x300)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (0x30030304)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (0x304)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (0x30030308)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (0x308)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (0x3003030c)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (0x30c)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (0x30030310)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (0x310)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (0x30030314)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (0x314)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (0x30030318)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (0x318)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (0x3003031c)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (0x31c)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (0x30030320)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (0x320)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (0x30030324)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (0x324)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (0x30030328)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (0x328)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (0x3003032c)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (0x32c)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (0x30030330)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (0x330)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (0x30030334)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (0x334)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (0x30030338)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (0x338)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x3003033c)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x33c)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x30030340)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x340)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x30030344)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x344)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x30030348)
-#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x348)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE (0x3003034c)
-#define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE (0x34c)
-#define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW (0)
-#define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK (0x3)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY (0x30030350)
-#define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY (0x350)
-#define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW (0)
-#define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK (0x1)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (0x30030354)
-#define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (0x354)
-#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (0x30030358)
-#define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (0x358)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (0x300302cc)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (0x2cc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (0x300302d0)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (0x2d0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (0x300302d4)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (0x2d4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (0x300302d8)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (0x2d8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (0x300302dc)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (0x2dc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (0x300302e0)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (0x2e0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (0x300302e4)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (0x2e4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (0x300302e8)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (0x2e8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (0x300302ec)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (0x2ec)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (0x300302f0)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (0x2f0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (0x300302f4)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (0x2f4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (0x300302f8)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (0x2f8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (0x300302fc)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (0x2fc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (0x30030300)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (0x300)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (0x30030304)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (0x304)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (0x30030308)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (0x308)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (0x3003030c)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (0x30c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (0x30030310)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (0x310)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (0x30030314)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (0x314)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (0x30030318)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (0x318)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (0x3003031c)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (0x31c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (0x30030320)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (0x320)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (0x30030324)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (0x324)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (0x30030328)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (0x328)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x3003032c)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (0x32c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x30030330)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (0x330)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x30030334)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (0x334)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x30030338)
+#define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (0x338)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (0x30030340)
+#define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (0x340)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (0x30030344)
+#define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (0x344)
+#define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0)
+#define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (0xf)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (0x30030348)
+#define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (0x348)
#define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0)
#define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (0xffff)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x3003034c)
+#define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (0x34c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x30030350)
+#define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (0x350)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x30030354)
+#define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (0x354)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x30030358)
+#define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (0x358)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (0x30030500)
+#define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (0x500)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (0x30030504)
+#define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (0x504)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (0x30030508)
+#define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (0x508)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (0x3003050c)
+#define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (0x50c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x30030510)
+#define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (0x510)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x30030514)
+#define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (0x514)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (0x30030518)
+#define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (0x518)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (0x3003051c)
+#define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (0x51c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (0x30030520)
+#define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (0x520)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (0x30030524)
+#define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (0x524)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x30030528)
+#define GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (0x528)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x3003052c)
+#define GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (0x52c)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (0x30030530)
+#define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (0x530)
+#define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0)
+#define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (0x1)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (0x300305a0)
+#define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (0x5a0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (0x300305a4)
+#define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (0x5a4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (0x300305a8)
+#define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (0x5a8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (0x300305ac)
+#define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (0x5ac)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x300305c0)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (0x5c0)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (0x1)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (0x2)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (0x4)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (0xfffffff8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x300305c4)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (0x5c4)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (0x1)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (0x2)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (0x4)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (0x8)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (0x10)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (0x20)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (0x40)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (0x80)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (0x100)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9)
+#define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (0xfffffe00)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x300305c8)
+#define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (0x5c8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x300305cc)
+#define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (0x5cc)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x300305d0)
+#define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (0x5d0)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x300305d4)
+#define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (0x5d4)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x300305d8)
+#define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (0x5d8)
+#define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x300305dc)
+#define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (0x5dc)
#endif
\ No newline at end of file
diff --git a/src/soc_ifc/rtl/caliptra_top_reg.rdl b/src/soc_ifc/rtl/caliptra_top_reg.rdl
index bc4169cc9..3c37bb1d1 100644
--- a/src/soc_ifc/rtl/caliptra_top_reg.rdl
+++ b/src/soc_ifc/rtl/caliptra_top_reg.rdl
@@ -15,7 +15,5 @@
addrmap caliptra_top_reg {
mbox_csr mbox_csr @ 0x3002_0000; //FIXME: Making these address constants as parameters to keep multiple files updated at the same time!
- sha512_acc_csr sha512_acc_csr @ 0x3002_1000;
-
soc_ifc_reg generic_and_fuse_reg @ 0x3003_0000;
};
diff --git a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh
index 399cc4237..d9582c109 100644
--- a/src/soc_ifc/rtl/caliptra_top_reg_defines.svh
+++ b/src/soc_ifc/rtl/caliptra_top_reg_defines.svh
@@ -54,71 +54,10 @@
`define MBOX_CSR_MBOX_UNLOCK (32'h20)
`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_LOW (0)
`define MBOX_CSR_MBOX_UNLOCK_UNLOCK_MASK (32'h1)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_BASE_ADDR (32'h30021000)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_LOCK (32'h30021000)
-`define SHA512_ACC_CSR_LOCK (32'h0)
-`define SHA512_ACC_CSR_LOCK_LOCK_LOW (0)
-`define SHA512_ACC_CSR_LOCK_LOCK_MASK (32'h1)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_ID (32'h30021004)
-`define SHA512_ACC_CSR_ID (32'h4)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_MODE (32'h30021008)
-`define SHA512_ACC_CSR_MODE (32'h8)
-`define SHA512_ACC_CSR_MODE_MODE_LOW (0)
-`define SHA512_ACC_CSR_MODE_MODE_MASK (32'h3)
-`define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_LOW (2)
-`define SHA512_ACC_CSR_MODE_ENDIAN_TOGGLE_MASK (32'h4)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_START_ADDRESS (32'h3002100c)
-`define SHA512_ACC_CSR_START_ADDRESS (32'hc)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DLEN (32'h30021010)
-`define SHA512_ACC_CSR_DLEN (32'h10)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DATAIN (32'h30021014)
-`define SHA512_ACC_CSR_DATAIN (32'h14)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_EXECUTE (32'h30021018)
-`define SHA512_ACC_CSR_EXECUTE (32'h18)
-`define SHA512_ACC_CSR_EXECUTE_EXECUTE_LOW (0)
-`define SHA512_ACC_CSR_EXECUTE_EXECUTE_MASK (32'h1)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_STATUS (32'h3002101c)
-`define SHA512_ACC_CSR_STATUS (32'h1c)
-`define SHA512_ACC_CSR_STATUS_VALID_LOW (0)
-`define SHA512_ACC_CSR_STATUS_VALID_MASK (32'h1)
-`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_LOW (1)
-`define SHA512_ACC_CSR_STATUS_SOC_HAS_LOCK_MASK (32'h2)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_0 (32'h30021020)
-`define SHA512_ACC_CSR_DIGEST_0 (32'h20)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_1 (32'h30021024)
-`define SHA512_ACC_CSR_DIGEST_1 (32'h24)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_2 (32'h30021028)
-`define SHA512_ACC_CSR_DIGEST_2 (32'h28)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_3 (32'h3002102c)
-`define SHA512_ACC_CSR_DIGEST_3 (32'h2c)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_4 (32'h30021030)
-`define SHA512_ACC_CSR_DIGEST_4 (32'h30)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_5 (32'h30021034)
-`define SHA512_ACC_CSR_DIGEST_5 (32'h34)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_6 (32'h30021038)
-`define SHA512_ACC_CSR_DIGEST_6 (32'h38)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_7 (32'h3002103c)
-`define SHA512_ACC_CSR_DIGEST_7 (32'h3c)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_8 (32'h30021040)
-`define SHA512_ACC_CSR_DIGEST_8 (32'h40)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_9 (32'h30021044)
-`define SHA512_ACC_CSR_DIGEST_9 (32'h44)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_10 (32'h30021048)
-`define SHA512_ACC_CSR_DIGEST_10 (32'h48)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_11 (32'h3002104c)
-`define SHA512_ACC_CSR_DIGEST_11 (32'h4c)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_12 (32'h30021050)
-`define SHA512_ACC_CSR_DIGEST_12 (32'h50)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_13 (32'h30021054)
-`define SHA512_ACC_CSR_DIGEST_13 (32'h54)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_14 (32'h30021058)
-`define SHA512_ACC_CSR_DIGEST_14 (32'h58)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_DIGEST_15 (32'h3002105c)
-`define SHA512_ACC_CSR_DIGEST_15 (32'h5c)
-`define CALIPTRA_TOP_REG_SHA512_ACC_CSR_CONTROL (32'h30021060)
-`define SHA512_ACC_CSR_CONTROL (32'h60)
-`define SHA512_ACC_CSR_CONTROL_ZEROIZE_LOW (0)
-`define SHA512_ACC_CSR_CONTROL_ZEROIZE_MASK (32'h1)
+`define CALIPTRA_TOP_REG_MBOX_CSR_TAP_MODE (32'h30020024)
+`define MBOX_CSR_TAP_MODE (32'h24)
+`define MBOX_CSR_TAP_MODE_ENABLED_LOW (0)
+`define MBOX_CSR_TAP_MODE_ENABLED_MASK (32'h1)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_BASE_ADDR (32'h30030000)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (32'h30030000)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL (32'h0)
@@ -130,6 +69,8 @@
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_NMI_PIN_MASK (32'h4)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_LOW (3)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_CRYPTO_ERR_MASK (32'h8)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_LOW (4)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_FATAL_RSVD_MASK (32'hfffffff0)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (32'h30030004)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL (32'h4)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_NO_LOCK_LOW (0)
@@ -138,6 +79,8 @@
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_PROT_OOO_MASK (32'h2)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_LOW (2)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_MBOX_ECC_UNC_MASK (32'h4)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_LOW (3)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_ERROR_NON_FATAL_RSVD_MASK (32'hfffffff8)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (32'h30030008)
`define GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_FATAL (32'h8)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_ERROR_NON_FATAL (32'h3003000c)
@@ -172,8 +115,8 @@
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_IDEVID_CSR_READY_MASK (32'h1000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_LOW (25)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_BOOT_FSM_PS_MASK (32'he000000)
-`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_LOW (28)
-`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FW_MASK (32'h10000000)
+`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_LOW (28)
+`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_MB_PROCESSING_MASK (32'h10000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_LOW (29)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK (32'h20000000)
`define GENERIC_AND_FUSE_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_LOW (30)
@@ -304,14 +247,12 @@
`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG (32'he0)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_LOW (0)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ITRNG_EN_MASK (32'h1)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_QSPI_EN_LOW (1)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_QSPI_EN_MASK (32'h2)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_LOW (2)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_I3C_EN_MASK (32'h4)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_LOW (3)
-`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_UART_EN_MASK (32'h8)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_LOW (1)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_RSVD_EN_MASK (32'he)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_LOW (4)
`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_LMS_ACC_EN_MASK (32'h10)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_LOW (5)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_CONFIG_ACTIVE_MODE_EN_MASK (32'h20)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'h300300e4)
`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN (32'he4)
`define GENERIC_AND_FUSE_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_LOW (0)
@@ -368,6 +309,42 @@
`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_0 (32'h120)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (32'h30030124)
`define GENERIC_AND_FUSE_REG_CPTRA_RSVD_REG_1 (32'h124)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (32'h30030128)
+`define GENERIC_AND_FUSE_REG_CPTRA_HW_CAPABILITIES (32'h128)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (32'h3003012c)
+`define GENERIC_AND_FUSE_REG_CPTRA_FW_CAPABILITIES (32'h12c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (32'h30030130)
+`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK (32'h130)
+`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_LOW (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_CAP_LOCK_LOCK_MASK (32'h1)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (32'h30030140)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_0 (32'h140)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (32'h30030144)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_1 (32'h144)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (32'h30030148)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_2 (32'h148)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (32'h3003014c)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_3 (32'h14c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (32'h30030150)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_4 (32'h150)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (32'h30030154)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_5 (32'h154)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (32'h30030158)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_6 (32'h158)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (32'h3003015c)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_7 (32'h15c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (32'h30030160)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_8 (32'h160)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (32'h30030164)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_9 (32'h164)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (32'h30030168)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_10 (32'h168)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (32'h3003016c)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_11 (32'h16c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h30030170)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK (32'h170)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_LOW (0)
+`define GENERIC_AND_FUSE_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK (32'h1)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (32'h30030200)
`define GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_0 (32'h200)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_UDS_SEED_1 (32'h30030204)
@@ -440,118 +417,190 @@
`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_10 (32'h288)
`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h3003028c)
`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_11 (32'h28c)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h30030290)
-`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK (32'h290)
-`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_LOW (0)
-`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK (32'hf)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_0 (32'h30030294)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_0 (32'h294)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_1 (32'h30030298)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_1 (32'h298)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_2 (32'h3003029c)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_2 (32'h29c)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_3 (32'h300302a0)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_3 (32'h2a0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_4 (32'h300302a4)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_4 (32'h2a4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_5 (32'h300302a8)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_5 (32'h2a8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_6 (32'h300302ac)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_6 (32'h2ac)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_7 (32'h300302b0)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_7 (32'h2b0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_8 (32'h300302b4)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_8 (32'h2b4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_9 (32'h300302b8)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_9 (32'h2b8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_10 (32'h300302bc)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_10 (32'h2bc)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_11 (32'h300302c0)
-`define GENERIC_AND_FUSE_REG_FUSE_OWNER_PK_HASH_11 (32'h2c0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h300302c4)
-`define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2c4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h300302c8)
-`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h2c8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h300302cc)
-`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h2cc)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h300302d0)
-`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h2d0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h300302d4)
-`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h2d4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h300302d8)
-`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2d8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h30030290)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0 (32'h290)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h30030294)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_1 (32'h294)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h30030298)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_2 (32'h298)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h3003029c)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_3 (32'h29c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h300302a0)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_4 (32'h2a0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h300302a4)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_5 (32'h2a4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h300302a8)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_6 (32'h2a8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h300302ac)
+`define GENERIC_AND_FUSE_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_7 (32'h2ac)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h300302b4)
+`define GENERIC_AND_FUSE_REG_FUSE_FMC_KEY_MANIFEST_SVN (32'h2b4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h300302b8)
+`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_0 (32'h2b8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h300302bc)
+`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_1 (32'h2bc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h300302c0)
+`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_2 (32'h2c0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h300302c4)
+`define GENERIC_AND_FUSE_REG_FUSE_RUNTIME_SVN_3 (32'h2c4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h300302c8)
+`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE (32'h2c8)
`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_LOW (0)
`define GENERIC_AND_FUSE_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h300302dc)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2dc)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h300302e0)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2e0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h300302e4)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2e4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h300302e8)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2e8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h300302ec)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2ec)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h300302f0)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2f0)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h300302f4)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2f4)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h300302f8)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2f8)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h300302fc)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2fc)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h30030300)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h300)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h30030304)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h304)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h30030308)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h308)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h3003030c)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h30c)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h30030310)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h310)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h30030314)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h314)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h30030318)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h318)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h3003031c)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h31c)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h30030320)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h320)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h30030324)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h324)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h30030328)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h328)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h3003032c)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h32c)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h30030330)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h330)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h30030334)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h334)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h30030338)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h338)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h3003033c)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h33c)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h30030340)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h340)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h30030344)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h344)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h30030348)
-`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h348)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE (32'h3003034c)
-`define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE (32'h34c)
-`define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_LOW (0)
-`define GENERIC_AND_FUSE_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK (32'h3)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY (32'h30030350)
-`define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY (32'h350)
-`define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_LOW (0)
-`define GENERIC_AND_FUSE_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK (32'h1)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h30030354)
-`define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h354)
-`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h30030358)
-`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h358)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h300302cc)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_0 (32'h2cc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h300302d0)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_1 (32'h2d0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h300302d4)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_2 (32'h2d4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h300302d8)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_3 (32'h2d8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h300302dc)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_4 (32'h2dc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h300302e0)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_5 (32'h2e0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h300302e4)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_6 (32'h2e4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h300302e8)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_7 (32'h2e8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h300302ec)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_8 (32'h2ec)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h300302f0)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_9 (32'h2f0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h300302f4)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_10 (32'h2f4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h300302f8)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_11 (32'h2f8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h300302fc)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_12 (32'h2fc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h30030300)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_13 (32'h300)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h30030304)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_14 (32'h304)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h30030308)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_15 (32'h308)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h3003030c)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_16 (32'h30c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h30030310)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_17 (32'h310)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h30030314)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_18 (32'h314)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h30030318)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_19 (32'h318)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h3003031c)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_20 (32'h31c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h30030320)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_21 (32'h320)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h30030324)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_22 (32'h324)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h30030328)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_CERT_ATTR_23 (32'h328)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h3003032c)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_0 (32'h32c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h30030330)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_1 (32'h330)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h30030334)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_2 (32'h334)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h30030338)
+`define GENERIC_AND_FUSE_REG_FUSE_IDEVID_MANUF_HSM_ID_3 (32'h338)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h30030340)
+`define GENERIC_AND_FUSE_REG_FUSE_LMS_REVOCATION (32'h340)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (32'h30030344)
+`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION (32'h344)
+`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_LOW (0)
+`define GENERIC_AND_FUSE_REG_FUSE_MLDSA_REVOCATION_MLDSA_REVOCATION_MASK (32'hf)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h30030348)
+`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID (32'h348)
`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_LOW (0)
`define GENERIC_AND_FUSE_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK (32'hffff)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h3003034c)
+`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_0 (32'h34c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h30030350)
+`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_1 (32'h350)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h30030354)
+`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_2 (32'h354)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h30030358)
+`define GENERIC_AND_FUSE_REG_FUSE_MANUF_DBG_UNLOCK_TOKEN_3 (32'h358)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h30030500)
+`define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_L (32'h500)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (32'h30030504)
+`define GENERIC_AND_FUSE_REG_SS_CALIPTRA_BASE_ADDR_H (32'h504)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (32'h30030508)
+`define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_L (32'h508)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (32'h3003050c)
+`define GENERIC_AND_FUSE_REG_SS_MCI_BASE_ADDR_H (32'h50c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h30030510)
+`define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_L (32'h510)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h30030514)
+`define GENERIC_AND_FUSE_REG_SS_RECOVERY_IFC_BASE_ADDR_H (32'h514)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (32'h30030518)
+`define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_L (32'h518)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (32'h3003051c)
+`define GENERIC_AND_FUSE_REG_SS_OTP_FC_BASE_ADDR_H (32'h51c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (32'h30030520)
+`define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_L (32'h520)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (32'h30030524)
+`define GENERIC_AND_FUSE_REG_SS_UDS_SEED_BASE_ADDR_H (32'h524)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h30030528)
+`define GENERIC_AND_FUSE_REG_SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET (32'h528)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h3003052c)
+`define GENERIC_AND_FUSE_REG_SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES (32'h52c)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (32'h30030530)
+`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT (32'h530)
+`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_LOW (0)
+`define GENERIC_AND_FUSE_REG_SS_DEBUG_INTENT_DEBUG_INTENT_MASK (32'h1)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (32'h300305a0)
+`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_0 (32'h5a0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (32'h300305a4)
+`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_1 (32'h5a4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (32'h300305a8)
+`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_2 (32'h5a8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (32'h300305ac)
+`define GENERIC_AND_FUSE_REG_SS_STRAP_GENERIC_3 (32'h5ac)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h300305c0)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ (32'h5c0)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_LOW (0)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_MANUF_DBG_UNLOCK_REQ_MASK (32'h1)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_LOW (1)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_PROD_DBG_UNLOCK_REQ_MASK (32'h2)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_LOW (2)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_UDS_PROGRAM_REQ_MASK (32'h4)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_LOW (3)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_REQ_RSVD_MASK (32'hfffffff8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h300305c4)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP (32'h5c4)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_LOW (0)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_SUCCESS_MASK (32'h1)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_LOW (1)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_FAIL_MASK (32'h2)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_LOW (2)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_MANUF_DBG_UNLOCK_IN_PROGRESS_MASK (32'h4)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_LOW (3)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_SUCCESS_MASK (32'h8)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_LOW (4)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_FAIL_MASK (32'h10)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_LOW (5)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_PROD_DBG_UNLOCK_IN_PROGRESS_MASK (32'h20)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_LOW (6)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK (32'h40)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_LOW (7)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_FAIL_MASK (32'h80)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_LOW (8)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_IN_PROGRESS_MASK (32'h100)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_LOW (9)
+`define GENERIC_AND_FUSE_REG_SS_DBG_MANUF_SERVICE_REG_RSP_RSVD_MASK (32'hfffffe00)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h300305c8)
+`define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_0 (32'h5c8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h300305cc)
+`define GENERIC_AND_FUSE_REG_SS_SOC_DBG_UNLOCK_LEVEL_1 (32'h5cc)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h300305d0)
+`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_0 (32'h5d0)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h300305d4)
+`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_1 (32'h5d4)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h300305d8)
+`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_2 (32'h5d8)
+`define CALIPTRA_TOP_REG_GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h300305dc)
+`define GENERIC_AND_FUSE_REG_SS_GENERIC_FW_EXEC_CTRL_3 (32'h5dc)
`endif
\ No newline at end of file
diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv
index db77658f3..1044d9bc0 100644
--- a/src/soc_ifc/rtl/mbox.sv
+++ b/src/soc_ifc/rtl/mbox.sv
@@ -66,6 +66,10 @@ module mbox
//DMI reg access
input logic dmi_inc_rdptr,
+ input logic dmi_inc_wrptr,
+ input logic dmi_reg_wen,
+ input logic [31:0] dmi_reg_wdata,
+ input logic [6:0] dmi_reg_addr,
output mbox_dmi_reg_t dmi_reg
);
@@ -96,14 +100,17 @@ logic arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC;
logic arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC;
logic arc_MBOX_EXECUTE_UC_MBOX_IDLE;
logic arc_MBOX_EXECUTE_SOC_MBOX_IDLE;
+logic arc_MBOX_EXECUTE_TAP_MBOX_IDLE;
logic arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC;
+logic arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_TAP;
logic arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC;
+logic arc_MBOX_EXECUTE_TAP_MBOX_EXECUTE_UC;
logic arc_MBOX_RDY_FOR_CMD_MBOX_ERROR;
logic arc_MBOX_RDY_FOR_DLEN_MBOX_ERROR;
logic arc_MBOX_RDY_FOR_DATA_MBOX_ERROR;
logic arc_MBOX_EXECUTE_UC_MBOX_ERROR;
logic arc_MBOX_EXECUTE_SOC_MBOX_ERROR;
-
+logic arc_MBOX_EXECUTE_TAP_MBOX_ERROR;
//sram
logic [DATA_W-1:0] sram_wdata;
logic [MBOX_ECC_DATA_W-1:0] sram_wdata_ecc;
@@ -144,6 +151,9 @@ logic wrptr_inc_valid;
mbox_protocol_error_t mbox_protocol_error_nxt;
+logic tap_mode;
+logic tap_mbox_data_avail;
+
//csr
logic [DATA_W-1:0] csr_rdata;
logic read_error;
@@ -154,6 +164,8 @@ mbox_csr__out_t hwif_out;
assign mbox_error = read_error | write_error;
+assign tap_mode = hwif_out.tap_mode.enabled.value;
+
//Determine if this is a valid request from the requester side
//1) uC requests are valid if uc has lock
//2) SoC requests are valid if soc has lock and it's the AXI ID that locked it
@@ -188,10 +200,14 @@ always_comb arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC = (mbox_fsm_ps == MBOX_RDY_FOR
always_comb arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC = (mbox_fsm_ps == MBOX_RDY_FOR_DATA) & hwif_out.mbox_execute.execute.value & ~soc_has_lock;
//move from rdy to execute to idle when uc resets execute
always_comb arc_MBOX_EXECUTE_UC_MBOX_IDLE = (mbox_fsm_ps == MBOX_EXECUTE_UC) & ~hwif_out.mbox_execute.execute.value;
-always_comb arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC = (mbox_fsm_ps == MBOX_EXECUTE_UC) & soc_has_lock & (hwif_out.mbox_status.status.value != CMD_BUSY);
+always_comb arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC = (mbox_fsm_ps == MBOX_EXECUTE_UC) & soc_has_lock & ~tap_mode & (hwif_out.mbox_status.status.value != CMD_BUSY);
+always_comb arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_TAP = (mbox_fsm_ps == MBOX_EXECUTE_UC) & soc_has_lock & tap_mode & (hwif_out.mbox_status.status.value != CMD_BUSY);
//move from rdy to execute to idle when SoC resets execute
always_comb arc_MBOX_EXECUTE_SOC_MBOX_IDLE = (mbox_fsm_ps == MBOX_EXECUTE_SOC) & ~hwif_out.mbox_execute.execute.value;
-always_comb arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC = (mbox_fsm_ps == MBOX_EXECUTE_SOC) & ~soc_has_lock & (hwif_out.mbox_status.status.value != CMD_BUSY);
+always_comb arc_MBOX_EXECUTE_SOC_MBOX_EXECUTE_UC = (mbox_fsm_ps == MBOX_EXECUTE_SOC) & ~soc_has_lock & ~tap_mode & (hwif_out.mbox_status.status.value != CMD_BUSY);
+//move from rdy to execute to idle when uc resets execute
+always_comb arc_MBOX_EXECUTE_TAP_MBOX_IDLE = (mbox_fsm_ps == MBOX_EXECUTE_TAP) & ~hwif_out.mbox_execute.execute.value;
+always_comb arc_MBOX_EXECUTE_TAP_MBOX_EXECUTE_UC = (mbox_fsm_ps == MBOX_EXECUTE_TAP) & ~soc_has_lock & tap_mode & (hwif_out.mbox_status.status.value != CMD_BUSY);
//move back to IDLE and unlock when force unlock is set
always_comb arc_FORCE_MBOX_UNLOCK = hwif_out.mbox_unlock.unlock.value;
// Detect error conditions and peg to the error state until serviced.
@@ -225,11 +241,13 @@ always_comb arc_MBOX_EXECUTE_SOC_MBOX_ERROR = (mbox_fsm_ps == MBOX_EXECUTE_SOC)
(req_data.write ? ((valid_requester && !(hwif_out.mbox_execute.execute.swmod)) ||
(~soc_has_lock && !(hwif_out.mbox_status.status.swmod))) :
(1'b0 /* any read allowed by SoC during this stage; dataout consumption is expected */));
+always_comb arc_MBOX_EXECUTE_TAP_MBOX_ERROR = 1'b0;
//capture the dlen when we change to execute states, this ensures that only the dlen programmed
//by the client filling the mailbox is used for masking the data
//Store the dlen as a ptr to the last entry
-always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC;
+always_comb latch_dlen_in_dws = arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_UC | arc_MBOX_RDY_FOR_DATA_MBOX_EXECUTE_SOC | arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_SOC |
+ arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_TAP | arc_MBOX_EXECUTE_TAP_MBOX_EXECUTE_UC;
always_comb mbox_dlen_in_dws = (hwif_out.mbox_dlen.length.value >= MBOX_SIZE_IN_BYTES) ? MBOX_SIZE_IN_DW[DEPTH_LOG2:0] :
(hwif_out.mbox_dlen.length.value[DEPTH_LOG2+2:2]) + (hwif_out.mbox_dlen.length.value[0] | hwif_out.mbox_dlen.length.value[1]);
//latched dlen is the smaller of the programmed dlen or the current wrptr
@@ -255,6 +273,7 @@ always_comb begin : mbox_fsm_combo
inc_wrptr = 0;
uc_mbox_data_avail = 0;
soc_mbox_data_avail = 0;
+ tap_mbox_data_avail = 0;
mbox_protocol_error_nxt = '{default: 0};
mbox_fsm_ns = mbox_fsm_ps;
@@ -338,6 +357,11 @@ always_comb begin : mbox_fsm_combo
rst_mbox_wrptr = 1;
rst_mbox_rdptr = 1;
end
+ else if (arc_MBOX_EXECUTE_UC_MBOX_EXECUTE_TAP) begin
+ mbox_fsm_ns = MBOX_EXECUTE_TAP;
+ rst_mbox_wrptr = 1;
+ rst_mbox_rdptr = 1;
+ end
else if (arc_MBOX_EXECUTE_UC_MBOX_ERROR) begin
mbox_fsm_ns = MBOX_ERROR;
mbox_protocol_error_nxt.axs_incorrect_order = 1'b1;
@@ -375,6 +399,29 @@ always_comb begin : mbox_fsm_combo
mbox_protocol_error_nxt = '{default: 0};
end
end
+ MBOX_EXECUTE_TAP: begin
+ tap_mbox_data_avail = 1;
+ inc_rdptr = (dmi_inc_rdptr);
+ inc_wrptr = (dmi_inc_wrptr);
+ if (arc_MBOX_EXECUTE_TAP_MBOX_IDLE) begin
+ mbox_fsm_ns = MBOX_IDLE;
+ end
+ else if (arc_MBOX_EXECUTE_TAP_MBOX_EXECUTE_UC) begin
+ mbox_fsm_ns = MBOX_EXECUTE_UC;
+ rst_mbox_wrptr = 1;
+ rst_mbox_rdptr = 1;
+ end
+ else if (arc_MBOX_EXECUTE_TAP_MBOX_ERROR) begin
+ mbox_fsm_ns = MBOX_ERROR;
+ mbox_protocol_error_nxt.axs_incorrect_order = 1'b1;
+ end
+ if (arc_FORCE_MBOX_UNLOCK) begin
+ mbox_fsm_ns = MBOX_IDLE;
+ inc_wrptr = 0;
+ inc_rdptr = 0;
+ mbox_protocol_error_nxt = '{default: 0};
+ end
+ end
MBOX_ERROR: begin
mbox_protocol_error_nxt = '{default: 0};
if (arc_FORCE_MBOX_UNLOCK) begin
@@ -526,7 +573,8 @@ rvecc_decode ecc_decode (
//control for sram write and read pointer
//SoC access is controlled by mailbox, each subsequent read or write increments the pointer
//uC accesses can specify the specific read or write address, or rely on mailbox to control
-always_comb sram_wdata = (dma_sram_req_dv_q && dma_sram_req_data.write ) ? dma_sram_req_data.wdata : req_data.wdata;
+always_comb sram_wdata = (dma_sram_req_dv_q && dma_sram_req_data.write ) ? dma_sram_req_data.wdata :
+ dmi_inc_wrptr ? dmi_reg_wdata : req_data.wdata;
//in ready for data state we increment the pointer each time we write
always_comb mbox_wrptr_nxt = rst_mbox_wrptr ? '0 :
@@ -579,6 +627,9 @@ always_comb hwif_in.mbox_status.ecc_double_error.hwset = sram_double_ecc_error;
always_comb hwif_in.mbox_status.soc_has_lock.next = soc_has_lock;
always_comb hwif_in.mbox_status.mbox_rdptr.next = mbox_rdptr;
+always_comb hwif_in.mbox_dlen.length.we = dmi_reg_wen & (dmi_reg_addr == DMI_REG_MBOX_DLEN);
+always_comb hwif_in.mbox_dlen.length.next = dmi_reg_wdata;
+
always_comb dmi_reg.MBOX_DLEN = hwif_out.mbox_dlen.length.value;
always_comb dmi_reg.MBOX_DOUT = hwif_out.mbox_dataout.dataout.value;
always_comb dmi_reg.MBOX_STATUS = {7'd0, /* [31:25] */
diff --git a/src/soc_ifc/rtl/mbox_csr.rdl b/src/soc_ifc/rtl/mbox_csr.rdl
index 20db8a635..6878be2d9 100644
--- a/src/soc_ifc/rtl/mbox_csr.rdl
+++ b/src/soc_ifc/rtl/mbox_csr.rdl
@@ -62,15 +62,16 @@ addrmap mbox_csr {
desc="Data length for mailbox access in bytes
[br]Caliptra Access: RW
[br]SOC Access: RW
- [br]TAP Access [in debug/manuf mode]: RO";
- field {sw=rw; hw=r; swwe=valid_requester; swmod=true;} length[32]=0;
+ [br]TAP Access [in debug/manuf mode]: RW";
+ field {sw=rw; hw=rw; we; swwe=valid_requester; swmod=true;} length[32]=0;
} mbox_dlen;
reg {
name="Mailbox DataIn";
desc="Data in register, write the next data to mailbox
[br]Caliptra Access: RW
- [br]SOC Access: RW";
+ [br]SOC Access: RW
+ [br]TAP Access [in debug/manuf mode]: WO";
field {sw=rw; hw=na; swwe=valid_requester; swmod=true;} datain[32]=0;
} mbox_datain;
@@ -194,6 +195,14 @@ addrmap mbox_csr {
field {sw=rw; hw=r; singlepulse; swwel = soc_req;} unlock=0;
} mbox_unlock;
+ reg {
+ name="Mailbox TAP Mode";
+ desc="Capability for uC to enable TAP logic to respond to mailbox commands.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RO";
+ field {sw=rw; hw=r; swwel = soc_req;} enabled=0;
+ } tap_mode;
+
// This will auto clear the status register whenever a mailbox transfer
// is not in progress. 1-cycle delayed from when the Receiver clears
// the execute field.
diff --git a/src/soc_ifc/rtl/mbox_csr.sv b/src/soc_ifc/rtl/mbox_csr.sv
index c58f79ea2..3fdb1d920 100644
--- a/src/soc_ifc/rtl/mbox_csr.sv
+++ b/src/soc_ifc/rtl/mbox_csr.sv
@@ -75,6 +75,7 @@ module mbox_csr (
logic mbox_execute;
logic mbox_status;
logic mbox_unlock;
+ logic tap_mode;
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_req;
@@ -92,6 +93,7 @@ module mbox_csr (
decoded_reg_strb.mbox_execute = cpuif_req_masked & (cpuif_addr == 6'h18);
decoded_reg_strb.mbox_status = cpuif_req_masked & (cpuif_addr == 6'h1c);
decoded_reg_strb.mbox_unlock = cpuif_req_masked & (cpuif_addr == 6'h20);
+ decoded_reg_strb.tap_mode = cpuif_req_masked & (cpuif_addr == 6'h24);
end
// Pass down signals to next stage
@@ -178,6 +180,12 @@ module mbox_csr (
logic load_next;
} unlock;
} mbox_unlock;
+ struct packed{
+ struct packed{
+ logic next;
+ logic load_next;
+ } enabled;
+ } tap_mode;
} field_combo_t;
field_combo_t field_combo;
@@ -242,6 +250,11 @@ module mbox_csr (
logic value;
} unlock;
} mbox_unlock;
+ struct packed{
+ struct packed{
+ logic value;
+ } enabled;
+ } tap_mode;
} field_storage_t;
field_storage_t field_storage;
@@ -321,6 +334,9 @@ module mbox_csr (
if(decoded_reg_strb.mbox_dlen && decoded_req_is_wr && hwif_in.valid_requester) begin // SW write
next_c = (field_storage.mbox_dlen.length.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
+ end else if(hwif_in.mbox_dlen.length.we) begin // HW Write - we
+ next_c = hwif_in.mbox_dlen.length.next;
+ load_next_c = '1;
end
field_combo.mbox_dlen.length.next = next_c;
field_combo.mbox_dlen.length.load_next = load_next_c;
@@ -565,6 +581,27 @@ module mbox_csr (
end
end
assign hwif_out.mbox_unlock.unlock.value = field_storage.mbox_unlock.unlock.value;
+ // Field: mbox_csr.tap_mode.enabled
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.tap_mode.enabled.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.tap_mode && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+ next_c = (field_storage.tap_mode.enabled.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end
+ field_combo.tap_mode.enabled.next = next_c;
+ field_combo.tap_mode.enabled.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.tap_mode.enabled.value <= 1'h0;
+ end else if(field_combo.tap_mode.enabled.load_next) begin
+ field_storage.tap_mode.enabled.value <= field_combo.tap_mode.enabled.next;
+ end
+ end
+ assign hwif_out.tap_mode.enabled.value = field_storage.tap_mode.enabled.value;
//--------------------------------------------------------------------------
// Write response
@@ -582,7 +619,7 @@ module mbox_csr (
logic [31:0] readback_data;
// Assign readback values to a flattened array
- logic [9-1:0][31:0] readback_array;
+ logic [10-1:0][31:0] readback_array;
assign readback_array[0][0:0] = (decoded_reg_strb.mbox_lock && !decoded_req_is_wr) ? field_storage.mbox_lock.lock.value : '0;
assign readback_array[0][31:1] = '0;
assign readback_array[1][31:0] = (decoded_reg_strb.mbox_user && !decoded_req_is_wr) ? field_storage.mbox_user.user.value : '0;
@@ -601,6 +638,8 @@ module mbox_csr (
assign readback_array[7][31:25] = '0;
assign readback_array[8][0:0] = (decoded_reg_strb.mbox_unlock && !decoded_req_is_wr) ? field_storage.mbox_unlock.unlock.value : '0;
assign readback_array[8][31:1] = '0;
+ assign readback_array[9][0:0] = (decoded_reg_strb.tap_mode && !decoded_req_is_wr) ? field_storage.tap_mode.enabled.value : '0;
+ assign readback_array[9][31:1] = '0;
// Reduce the array
always_comb begin
@@ -608,7 +647,7 @@ module mbox_csr (
readback_done = decoded_req & ~decoded_req_is_wr;
readback_err = '0;
readback_data_var = '0;
- for(int i=0; i<9; i++) readback_data_var |= readback_array[i];
+ for(int i=0; i<10; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
diff --git a/src/soc_ifc/rtl/mbox_csr_pkg.sv b/src/soc_ifc/rtl/mbox_csr_pkg.sv
index 39f775c03..18ac6cbf1 100644
--- a/src/soc_ifc/rtl/mbox_csr_pkg.sv
+++ b/src/soc_ifc/rtl/mbox_csr_pkg.sv
@@ -22,6 +22,15 @@ package mbox_csr_pkg;
mbox_csr__mbox_user__user__in_t user;
} mbox_csr__mbox_user__in_t;
+ typedef struct packed{
+ logic [31:0] next;
+ logic we;
+ } mbox_csr__mbox_dlen__length__in_t;
+
+ typedef struct packed{
+ mbox_csr__mbox_dlen__length__in_t length;
+ } mbox_csr__mbox_dlen__in_t;
+
typedef struct packed{
logic [31:0] next;
logic we;
@@ -81,6 +90,7 @@ package mbox_csr_pkg;
logic valid_receiver;
mbox_csr__mbox_lock__in_t mbox_lock;
mbox_csr__mbox_user__in_t mbox_user;
+ mbox_csr__mbox_dlen__in_t mbox_dlen;
mbox_csr__mbox_dataout__in_t mbox_dataout;
mbox_csr__mbox_execute__in_t mbox_execute;
mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__in_t mbox_status;
@@ -188,6 +198,14 @@ package mbox_csr_pkg;
mbox_csr__mbox_unlock__unlock__out_t unlock;
} mbox_csr__mbox_unlock__out_t;
+ typedef struct packed{
+ logic value;
+ } mbox_csr__tap_mode__enabled__out_t;
+
+ typedef struct packed{
+ mbox_csr__tap_mode__enabled__out_t enabled;
+ } mbox_csr__tap_mode__out_t;
+
typedef struct packed{
mbox_csr__mbox_lock__out_t mbox_lock;
mbox_csr__mbox_user__out_t mbox_user;
@@ -198,6 +216,7 @@ package mbox_csr_pkg;
mbox_csr__mbox_execute__out_t mbox_execute;
mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760__out_t mbox_status;
mbox_csr__mbox_unlock__out_t mbox_unlock;
+ mbox_csr__tap_mode__out_t tap_mode;
} mbox_csr__out_t;
typedef enum logic [31:0] {
diff --git a/src/soc_ifc/rtl/mbox_csr_uvm.sv b/src/soc_ifc/rtl/mbox_csr_uvm.sv
index 760853a1a..d5302eb3b 100644
--- a/src/soc_ifc/rtl/mbox_csr_uvm.sv
+++ b/src/soc_ifc/rtl/mbox_csr_uvm.sv
@@ -115,7 +115,7 @@ package mbox_csr_uvm;
virtual function void build();
this.length = new("length");
- this.length.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.length.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
foreach(length_bit_cg[bt]) length_bit_cg[bt] = new();
end
@@ -299,6 +299,36 @@ package mbox_csr_uvm;
endfunction : build
endclass : mbox_csr__mbox_unlock
+ // Reg - mbox_csr::tap_mode
+ class mbox_csr__tap_mode extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ mbox_csr__tap_mode_bit_cg enabled_bit_cg[1];
+ mbox_csr__tap_mode_fld_cg fld_cg;
+ rand uvm_reg_field enabled;
+
+ function new(string name = "mbox_csr__tap_mode");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.enabled = new("enabled");
+ this.enabled.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(enabled_bit_cg[bt]) enabled_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : mbox_csr__tap_mode
+
// Addrmap - mbox_csr
class mbox_csr extends uvm_reg_block;
rand mbox_csr__mbox_lock mbox_lock;
@@ -310,6 +340,7 @@ package mbox_csr_uvm;
rand mbox_csr__mbox_execute mbox_execute;
rand mbox_csr__mbox_status_ecc_double_error_38cec4b0_ecc_single_error_9c62b760 mbox_status;
rand mbox_csr__mbox_unlock mbox_unlock;
+ rand mbox_csr__tap_mode tap_mode;
function new(string name = "mbox_csr");
super.new(name);
@@ -362,6 +393,11 @@ package mbox_csr_uvm;
this.mbox_unlock.build();
this.default_map.add_reg(this.mbox_unlock, 'h20);
+ this.tap_mode = new("tap_mode");
+ this.tap_mode.configure(this);
+
+ this.tap_mode.build();
+ this.default_map.add_reg(this.tap_mode, 'h24);
endfunction : build
endclass : mbox_csr
diff --git a/src/soc_ifc/rtl/soc_ifc_doc.rdl b/src/soc_ifc/rtl/soc_ifc_doc.rdl
index 55153989e..93e6bbc8e 100644
--- a/src/soc_ifc/rtl/soc_ifc_doc.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_doc.rdl
@@ -16,4 +16,5 @@ addrmap soc_ifc_reg {
`include "soc_ifc_reg_properties.rdl"
`include "soc_ifc_external_reg.rdl"
`include "soc_ifc_fuse_reg.rdl"
+ `include "soc_ifc_subsystem_reg.rdl"
};
diff --git a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl
index 8c8de8d95..14d0ffe46 100644
--- a/src/soc_ifc/rtl/soc_ifc_external_reg.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_external_reg.rdl
@@ -28,6 +28,7 @@ reg {
rw_rw_sticky_hw dccm_ecc_unc=0; /* Uncorrectable double-bit error in DCCM */
rw_rw_sticky_hw nmi_pin=0; /* Non-Maskable Interrupt due to WDT timeout */
rw_rw_sticky_hw crypto_err=0; /* Crypto parallel operation error No Mask */
+ field {sw=r; hw=w;} rsvd[28]=28'h0;
} CPTRA_HW_ERROR_FATAL;
reg {
name = "Hardware Error Non-Fatal";
@@ -51,6 +52,7 @@ reg {
rw_rw_sticky_hw mbox_prot_no_lock=0; /* SOC access while not locked */
rw_rw_sticky_hw mbox_prot_ooo=0; /* Register access out-of-order */
rw_rw_sticky_hw mbox_ecc_unc=0; /* Uncorrectable double-bit error in DCCM */
+ field {sw=r; hw=w;} rsvd[29]=29'h0;
} CPTRA_HW_ERROR_NON_FATAL;
reg {
name = "Firmware Error Fatal";
@@ -124,7 +126,7 @@ reg {
rw_ro status[24]=0;
field {desc="DEV ID CSR ready"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} idevid_csr_ready[1]=0;
field {desc="Boot FSM State"; sw=r; hw=w ; /* no storage, no reset */} boot_fsm_ps[3];
- field {desc="Indicates Caliptra is ready for Firmware Download"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_fw[1]=0;
+ field {desc="Indicates Caliptra is ready for Mailbox operations"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_mb_processing[1]=0;
field {desc="Indicates Caliptra is ready for RT flows"; sw=rw; swwel = soc_req; hw=r ; resetsignal = cptra_rst_b;} ready_for_runtime[1]=0;
field {desc="Indicates Caliptra is ready for Fuses to be programmed.
Read-only to both Caliptra and SOC."; sw=r; hw=w ; /* no storage, no reset */} ready_for_fuses[1];
@@ -175,7 +177,7 @@ reg {
//FIXME: Should LOCK be W1 here?
reg {
- name = "Valid ID Register Lock";
+ name = "Valid USER Register Lock";
desc = "Valid AXI_USER attributes for requests from SoC AXI Interface.
[br]Each bit corresponds to locking the associated MBOX_VALID_AXI_USER register.
[br]Associated MBOX_VALID_AXI_USER register is only valid once locked by this bit.
@@ -195,7 +197,7 @@ reg {
} CPTRA_TRNG_VALID_AXI_USER;
reg {
- name = "Valid ID for TRNG AXI_USER Lock";
+ name = "Valid USER for TRNG AXI_USER Lock";
desc = "Valid AXI USER attributes for requests from SoC AXI Interface.
[br]Each bit corresponds to locking the associated TRNG_VALID_AXI_USER register.
[br]Associated TRNG_VALID_AXI_USER register is only valid once locked by this bit.
@@ -329,10 +331,9 @@ reg {
[br]SOC Access: RO";
// No storage, i.e. no resetsignal
field {sw=r; hw=w;} iTRNG_en;
- field {sw=r; hw=w;} QSPI_en;
- field {sw=r; hw=w;} I3C_en;
- field {sw=r; hw=w;} UART_en;
+ field {sw=r; hw=w;} RSVD_en[3];
field {sw=r; hw=w;} LMS_acc_en;
+ field {sw=r; hw=w;} ACTIVE_MODE_en;
} CPTRA_HW_CONFIG;
//Timer1
@@ -450,3 +451,46 @@ reg {
[br]SOC Access: RW";
field {sw=rw; resetsignal=cptra_rst_b;} RSVD[32]=0;
} CPTRA_RSVD_REG[2];
+
+reg {
+ name = "Caliptra HW Capabilities";
+ desc = "Caliptra HW Capabilities. Initialized with reset values, rewritable by Caliptra firmware.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RO
+ [br]Read-only once locked.";
+ field {sw=rw; swwel; resetsignal=cptra_rst_b;} cap[32]=32'h0;
+} CPTRA_HW_CAPABILITIES;
+
+reg {
+ name = "Caliptra FW Capabilities";
+ desc = "Caliptra FW Capabilities. Initialized with reset values, rewritable by Caliptra firmware.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RO
+ [br]Read-only once locked.";
+ field {sw=rw; swwel; resetsignal=cptra_rst_b;} cap[32]=32'h0;
+} CPTRA_FW_CAPABILITIES;
+
+reg {
+ name = "Caliptra Capabilities Lock";
+ desc = "Lock register to disable further firmware modifications to capabilities registers.
+ [br]Once set, this register may not be cleared until a warm reset. If set, the values in CPTRA_HW_CAPABILITIES and CPTRA_FW_CAPABILITIES may not be modified.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RO
+ [br]Read-only once locked.";
+ field {sw=rw; hw=r; swwel; resetsignal=cptra_rst_b;} lock = 1'b0;
+} CPTRA_CAP_LOCK;
+
+reg {
+ desc = "Owner PK hash lockable register.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ field {sw = rw; hw = r; swwel; resetsignal = cptra_pwrgood;} hash[32]=0;
+} CPTRA_OWNER_PK_HASH[12] @0x140;
+
+reg {
+ name = "Owner PK hash register lock";
+ desc = "Owner PK hash register lock. Locks further writes to Owner PK hash register. Reset only by power cycle.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RW1-S";
+ field {sw=rw; hw=r; swwe; resetsignal=cptra_pwrgood;} lock=0;
+} CPTRA_OWNER_PK_HASH_LOCK;
diff --git a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl
index 93fa6c27f..c7ae8f405 100644
--- a/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_fuse_reg.rdl
@@ -41,23 +41,18 @@ reg {
Fuse hash[32]=0;
} fuse_key_manifest_pk_hash[12];
reg {
- desc = "Key Manifest Mask Fuse.
+ desc = "Key Manifest Mask Fuse (ECC Revocation).
[br]Caliptra Access: RO
[br]SOC Access: RWL-S";
- Fuse mask[4]=0;
-} fuse_key_manifest_pk_hash_mask;
-reg {
- desc = "Owner PK hash Fuse.
- [br]Caliptra Access: RO
- [br]SOC Access: RWL-S";
- Fuse hash[32]=0;
-} fuse_owner_pk_hash[12];
+ Fuse mask[32]=0;
+} fuse_key_manifest_pk_hash_mask[8];
+
reg {
desc = "FMC Security Version Number.
[br]Caliptra Access: RO
[br]SOC Access: RWL-S";
Fuse svn[32]=0;
-} fuse_fmc_key_manifest_svn;
+} fuse_fmc_key_manifest_svn @0x2b4;
reg {
desc = "Runtime SVN Fuse.
[br]Caliptra Access: RO
@@ -82,28 +77,28 @@ reg {
[br]SOC Access: RWL-S";
Fuse hsm_id[32]=0;
} fuse_idevid_manuf_hsm_id[4];
+
reg {
- desc = " Caliptra Boot Media Integrated mode usage only. SOCs that build with a Boot Media Independent profile don’t have to account for these fuses.
- [br]Caliptra Access: RO
- [br]SOC Access: RWL-S";
- Fuse life_cycle[2]=0;
-} fuse_life_cycle;
-reg {
- desc = "0 - Verify Caliptra firmware images with ECDSA-only; 1 - Verify Caliptra firmware images with both ECDSA and LMS
+ desc = "One-hot encoded list of revoked Vendor LMS Public Keys (up to 32 keys)
[br]Caliptra Access: RO
[br]SOC Access: RWL-S";
- Fuse lms_verify[1]=0;
-} fuse_lms_verify;
+ Fuse lms_revocation[32]=0;
+} fuse_lms_revocation @0x340;
reg {
- desc = "Bits for revoking LMS public keys in the key manifest
+ desc = "One-hot encoded list of revoked Vendor MLDSA Public Keys (up to 4 keys)
[br]Caliptra Access: RO
[br]SOC Access: RWL-S";
- Fuse lms_revocation[32]=0;
-} fuse_lms_revocation;
+ Fuse mldsa_revocation[4]=0;
+} fuse_mldsa_revocation;
reg {
desc = "SOC stepping ID
[br]Caliptra Access: RO
[br]SOC Access: RWL-S";
Fuse soc_stepping_id[16]=0;
} fuse_soc_stepping_id;
-
+reg {
+ desc = "Manufacturing debug unlock token
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ Fuse token[32]=0;
+} fuse_manuf_dbg_unlock_token[4];
diff --git a/src/soc_ifc/rtl/soc_ifc_pkg.sv b/src/soc_ifc/rtl/soc_ifc_pkg.sv
index 11a548638..c037d13a4 100644
--- a/src/soc_ifc/rtl/soc_ifc_pkg.sv
+++ b/src/soc_ifc/rtl/soc_ifc_pkg.sv
@@ -74,9 +74,34 @@ package soc_ifc_pkg;
parameter DMI_REG_BOOT_STATUS = 7'h53;
parameter DMI_REG_CPTRA_HW_ERRROR_ENC = 7'h54;
parameter DMI_REG_CPTRA_FW_ERROR_ENC = 7'h55;
+ parameter DMI_REG_SS_UDS_SEED_BASE_ADDR_L = 7'h56;
+ parameter DMI_REG_SS_UDS_SEED_BASE_ADDR_H = 7'h57;
+ parameter DMI_REG_HW_FATAL_ERROR = 7'h58;
+ parameter DMI_REG_FW_FATAL_ERROR = 7'h59;
+ parameter DMI_REG_HW_NON_FATAL_ERROR = 7'h5a;
+ parameter DMI_REG_FW_NON_FATAL_ERROR = 7'h5b;
//RW registers
parameter DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG = 7'h60;
parameter DMI_REG_BOOTFSM_GO = 7'h61;
+ parameter DMI_REG_MBOX_DIN = 7'h62;
+ parameter DMI_REG_SS_DEBUG_INTENT = 7'h63;
+ parameter DMI_REG_SS_CALIPTRA_BASE_ADDR_L = 7'h64;
+ parameter DMI_REG_SS_CALIPTRA_BASE_ADDR_H = 7'h65;
+ parameter DMI_REG_SS_MCI_BASE_ADDR_L = 7'h66;
+ parameter DMI_REG_SS_MCI_BASE_ADDR_H = 7'h67;
+ parameter DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_L = 7'h68;
+ parameter DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_H = 7'h69;
+ parameter DMI_REG_SS_OTP_FC_BASE_ADDR_L = 7'h6A;
+ parameter DMI_REG_SS_OTP_FC_BASE_ADDR_H = 7'h6B;
+ parameter DMI_REG_SS_STRAP_GENERIC_0 = 7'h6C;
+ parameter DMI_REG_SS_STRAP_GENERIC_1 = 7'h6D;
+ parameter DMI_REG_SS_STRAP_GENERIC_2 = 7'h6E;
+ parameter DMI_REG_SS_STRAP_GENERIC_3 = 7'h6F;
+ parameter DMI_REG_SS_DBG_MANUF_SERVICE_REG_REQ = 7'h70;
+ parameter DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP = 7'h71;
+ parameter DMI_REG_SS_DBG_UNLOCK_LEVEL0 = 7'h72;
+ parameter DMI_REG_SS_DBG_UNLOCK_LEVEL1 = 7'h73;
+
// This parameter describes the hard-coded implementation in the BOOT FSM
// that results in noncore reset assertion being delayed from the soft reset
@@ -103,6 +128,7 @@ package soc_ifc_pkg;
MBOX_RDY_FOR_DATA = 3'b010,
MBOX_EXECUTE_UC = 3'b110,
MBOX_EXECUTE_SOC = 3'b100,
+ MBOX_EXECUTE_TAP = 3'b101,
MBOX_ERROR = 3'b111
} mbox_fsm_state_e;
diff --git a/src/soc_ifc/rtl/soc_ifc_reg.rdl b/src/soc_ifc/rtl/soc_ifc_reg.rdl
index 13ef4891c..af27a982b 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg.rdl
+++ b/src/soc_ifc/rtl/soc_ifc_reg.rdl
@@ -16,5 +16,6 @@ addrmap soc_ifc_reg {
`include "soc_ifc_reg_properties.rdl"
`include "soc_ifc_external_reg.rdl"
`include "soc_ifc_fuse_reg.rdl"
+ `include "soc_ifc_subsystem_reg.rdl"
`include "soc_ifc_internal_reg.rdl"
};
diff --git a/src/soc_ifc/rtl/soc_ifc_reg.sv b/src/soc_ifc/rtl/soc_ifc_reg.sv
index c8abb9e7c..1df823f23 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg.sv
+++ b/src/soc_ifc/rtl/soc_ifc_reg.sv
@@ -107,20 +107,42 @@ module soc_ifc_reg (
logic CPTRA_iTRNG_ENTROPY_CONFIG_0;
logic CPTRA_iTRNG_ENTROPY_CONFIG_1;
logic [2-1:0]CPTRA_RSVD_REG;
+ logic CPTRA_HW_CAPABILITIES;
+ logic CPTRA_FW_CAPABILITIES;
+ logic CPTRA_CAP_LOCK;
+ logic [12-1:0]CPTRA_OWNER_PK_HASH;
+ logic CPTRA_OWNER_PK_HASH_LOCK;
logic [16-1:0]fuse_uds_seed;
logic [8-1:0]fuse_field_entropy;
logic [12-1:0]fuse_key_manifest_pk_hash;
- logic fuse_key_manifest_pk_hash_mask;
- logic [12-1:0]fuse_owner_pk_hash;
+ logic [8-1:0]fuse_key_manifest_pk_hash_mask;
logic fuse_fmc_key_manifest_svn;
logic [4-1:0]fuse_runtime_svn;
logic fuse_anti_rollback_disable;
logic [24-1:0]fuse_idevid_cert_attr;
logic [4-1:0]fuse_idevid_manuf_hsm_id;
- logic fuse_life_cycle;
- logic fuse_lms_verify;
logic fuse_lms_revocation;
+ logic fuse_mldsa_revocation;
logic fuse_soc_stepping_id;
+ logic [4-1:0]fuse_manuf_dbg_unlock_token;
+ logic SS_CALIPTRA_BASE_ADDR_L;
+ logic SS_CALIPTRA_BASE_ADDR_H;
+ logic SS_MCI_BASE_ADDR_L;
+ logic SS_MCI_BASE_ADDR_H;
+ logic SS_RECOVERY_IFC_BASE_ADDR_L;
+ logic SS_RECOVERY_IFC_BASE_ADDR_H;
+ logic SS_OTP_FC_BASE_ADDR_L;
+ logic SS_OTP_FC_BASE_ADDR_H;
+ logic SS_UDS_SEED_BASE_ADDR_L;
+ logic SS_UDS_SEED_BASE_ADDR_H;
+ logic SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET;
+ logic SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES;
+ logic SS_DEBUG_INTENT;
+ logic [4-1:0]SS_STRAP_GENERIC;
+ logic SS_DBG_MANUF_SERVICE_REG_REQ;
+ logic SS_DBG_MANUF_SERVICE_REG_RSP;
+ logic [2-1:0]SS_SOC_DBG_UNLOCK_LEVEL;
+ logic [4-1:0]SS_GENERIC_FW_EXEC_CTRL;
logic [8-1:0]internal_obf_key;
logic internal_iccm_lock;
logic internal_fw_update_reset;
@@ -244,6 +266,13 @@ module soc_ifc_reg (
for(int i0=0; i0<2; i0++) begin
decoded_reg_strb.CPTRA_RSVD_REG[i0] = cpuif_req_masked & (cpuif_addr == 12'h120 + i0*12'h4);
end
+ decoded_reg_strb.CPTRA_HW_CAPABILITIES = cpuif_req_masked & (cpuif_addr == 12'h128);
+ decoded_reg_strb.CPTRA_FW_CAPABILITIES = cpuif_req_masked & (cpuif_addr == 12'h12c);
+ decoded_reg_strb.CPTRA_CAP_LOCK = cpuif_req_masked & (cpuif_addr == 12'h130);
+ for(int i0=0; i0<12; i0++) begin
+ decoded_reg_strb.CPTRA_OWNER_PK_HASH[i0] = cpuif_req_masked & (cpuif_addr == 12'h140 + i0*12'h4);
+ end
+ decoded_reg_strb.CPTRA_OWNER_PK_HASH_LOCK = cpuif_req_masked & (cpuif_addr == 12'h170);
for(int i0=0; i0<16; i0++) begin
decoded_reg_strb.fuse_uds_seed[i0] = cpuif_req_masked & (cpuif_addr == 12'h200 + i0*12'h4);
end
@@ -253,25 +282,50 @@ module soc_ifc_reg (
for(int i0=0; i0<12; i0++) begin
decoded_reg_strb.fuse_key_manifest_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h260 + i0*12'h4);
end
- decoded_reg_strb.fuse_key_manifest_pk_hash_mask = cpuif_req_masked & (cpuif_addr == 12'h290);
- for(int i0=0; i0<12; i0++) begin
- decoded_reg_strb.fuse_owner_pk_hash[i0] = cpuif_req_masked & (cpuif_addr == 12'h294 + i0*12'h4);
+ for(int i0=0; i0<8; i0++) begin
+ decoded_reg_strb.fuse_key_manifest_pk_hash_mask[i0] = cpuif_req_masked & (cpuif_addr == 12'h290 + i0*12'h4);
end
- decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 12'h2c4);
+ decoded_reg_strb.fuse_fmc_key_manifest_svn = cpuif_req_masked & (cpuif_addr == 12'h2b4);
for(int i0=0; i0<4; i0++) begin
- decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 12'h2c8 + i0*12'h4);
+ decoded_reg_strb.fuse_runtime_svn[i0] = cpuif_req_masked & (cpuif_addr == 12'h2b8 + i0*12'h4);
end
- decoded_reg_strb.fuse_anti_rollback_disable = cpuif_req_masked & (cpuif_addr == 12'h2d8);
+ decoded_reg_strb.fuse_anti_rollback_disable = cpuif_req_masked & (cpuif_addr == 12'h2c8);
for(int i0=0; i0<24; i0++) begin
- decoded_reg_strb.fuse_idevid_cert_attr[i0] = cpuif_req_masked & (cpuif_addr == 12'h2dc + i0*12'h4);
+ decoded_reg_strb.fuse_idevid_cert_attr[i0] = cpuif_req_masked & (cpuif_addr == 12'h2cc + i0*12'h4);
+ end
+ for(int i0=0; i0<4; i0++) begin
+ decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] = cpuif_req_masked & (cpuif_addr == 12'h32c + i0*12'h4);
+ end
+ decoded_reg_strb.fuse_lms_revocation = cpuif_req_masked & (cpuif_addr == 12'h340);
+ decoded_reg_strb.fuse_mldsa_revocation = cpuif_req_masked & (cpuif_addr == 12'h344);
+ decoded_reg_strb.fuse_soc_stepping_id = cpuif_req_masked & (cpuif_addr == 12'h348);
+ for(int i0=0; i0<4; i0++) begin
+ decoded_reg_strb.fuse_manuf_dbg_unlock_token[i0] = cpuif_req_masked & (cpuif_addr == 12'h34c + i0*12'h4);
+ end
+ decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L = cpuif_req_masked & (cpuif_addr == 12'h500);
+ decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H = cpuif_req_masked & (cpuif_addr == 12'h504);
+ decoded_reg_strb.SS_MCI_BASE_ADDR_L = cpuif_req_masked & (cpuif_addr == 12'h508);
+ decoded_reg_strb.SS_MCI_BASE_ADDR_H = cpuif_req_masked & (cpuif_addr == 12'h50c);
+ decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_L = cpuif_req_masked & (cpuif_addr == 12'h510);
+ decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_H = cpuif_req_masked & (cpuif_addr == 12'h514);
+ decoded_reg_strb.SS_OTP_FC_BASE_ADDR_L = cpuif_req_masked & (cpuif_addr == 12'h518);
+ decoded_reg_strb.SS_OTP_FC_BASE_ADDR_H = cpuif_req_masked & (cpuif_addr == 12'h51c);
+ decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_L = cpuif_req_masked & (cpuif_addr == 12'h520);
+ decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_H = cpuif_req_masked & (cpuif_addr == 12'h524);
+ decoded_reg_strb.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET = cpuif_req_masked & (cpuif_addr == 12'h528);
+ decoded_reg_strb.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES = cpuif_req_masked & (cpuif_addr == 12'h52c);
+ decoded_reg_strb.SS_DEBUG_INTENT = cpuif_req_masked & (cpuif_addr == 12'h530);
+ for(int i0=0; i0<4; i0++) begin
+ decoded_reg_strb.SS_STRAP_GENERIC[i0] = cpuif_req_masked & (cpuif_addr == 12'h5a0 + i0*12'h4);
+ end
+ decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ = cpuif_req_masked & (cpuif_addr == 12'h5c0);
+ decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP = cpuif_req_masked & (cpuif_addr == 12'h5c4);
+ for(int i0=0; i0<2; i0++) begin
+ decoded_reg_strb.SS_SOC_DBG_UNLOCK_LEVEL[i0] = cpuif_req_masked & (cpuif_addr == 12'h5c8 + i0*12'h4);
end
for(int i0=0; i0<4; i0++) begin
- decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] = cpuif_req_masked & (cpuif_addr == 12'h33c + i0*12'h4);
+ decoded_reg_strb.SS_GENERIC_FW_EXEC_CTRL[i0] = cpuif_req_masked & (cpuif_addr == 12'h5d0 + i0*12'h4);
end
- decoded_reg_strb.fuse_life_cycle = cpuif_req_masked & (cpuif_addr == 12'h34c);
- decoded_reg_strb.fuse_lms_verify = cpuif_req_masked & (cpuif_addr == 12'h350);
- decoded_reg_strb.fuse_lms_revocation = cpuif_req_masked & (cpuif_addr == 12'h354);
- decoded_reg_strb.fuse_soc_stepping_id = cpuif_req_masked & (cpuif_addr == 12'h358);
for(int i0=0; i0<8; i0++) begin
decoded_reg_strb.internal_obf_key[i0] = cpuif_req_masked & (cpuif_addr == 12'h600 + i0*12'h4);
end
@@ -416,7 +470,7 @@ module soc_ifc_reg (
struct packed{
logic next;
logic load_next;
- } ready_for_fw;
+ } ready_for_mb_processing;
struct packed{
logic next;
logic load_next;
@@ -620,6 +674,36 @@ module soc_ifc_reg (
logic load_next;
} RSVD;
} [2-1:0]CPTRA_RSVD_REG;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } cap;
+ } CPTRA_HW_CAPABILITIES;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } cap;
+ } CPTRA_FW_CAPABILITIES;
+ struct packed{
+ struct packed{
+ logic next;
+ logic load_next;
+ } lock;
+ } CPTRA_CAP_LOCK;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } hash;
+ } [12-1:0]CPTRA_OWNER_PK_HASH;
+ struct packed{
+ struct packed{
+ logic next;
+ logic load_next;
+ } lock;
+ } CPTRA_OWNER_PK_HASH_LOCK;
struct packed{
struct packed{
logic [31:0] next;
@@ -638,18 +722,12 @@ module soc_ifc_reg (
logic load_next;
} hash;
} [12-1:0]fuse_key_manifest_pk_hash;
- struct packed{
- struct packed{
- logic [3:0] next;
- logic load_next;
- } mask;
- } fuse_key_manifest_pk_hash_mask;
struct packed{
struct packed{
logic [31:0] next;
logic load_next;
- } hash;
- } [12-1:0]fuse_owner_pk_hash;
+ } mask;
+ } [8-1:0]fuse_key_manifest_pk_hash_mask;
struct packed{
struct packed{
logic [31:0] next;
@@ -682,28 +760,176 @@ module soc_ifc_reg (
} [4-1:0]fuse_idevid_manuf_hsm_id;
struct packed{
struct packed{
- logic [1:0] next;
+ logic [31:0] next;
+ logic load_next;
+ } lms_revocation;
+ } fuse_lms_revocation;
+ struct packed{
+ struct packed{
+ logic [3:0] next;
+ logic load_next;
+ } mldsa_revocation;
+ } fuse_mldsa_revocation;
+ struct packed{
+ struct packed{
+ logic [15:0] next;
+ logic load_next;
+ } soc_stepping_id;
+ } fuse_soc_stepping_id;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } token;
+ } [4-1:0]fuse_manuf_dbg_unlock_token;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_l;
+ } SS_CALIPTRA_BASE_ADDR_L;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_h;
+ } SS_CALIPTRA_BASE_ADDR_H;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_l;
+ } SS_MCI_BASE_ADDR_L;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_h;
+ } SS_MCI_BASE_ADDR_H;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_l;
+ } SS_RECOVERY_IFC_BASE_ADDR_L;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_h;
+ } SS_RECOVERY_IFC_BASE_ADDR_H;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_l;
+ } SS_OTP_FC_BASE_ADDR_L;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_h;
+ } SS_OTP_FC_BASE_ADDR_H;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_l;
+ } SS_UDS_SEED_BASE_ADDR_L;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } addr_h;
+ } SS_UDS_SEED_BASE_ADDR_H;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } offset;
+ } SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
logic load_next;
- } life_cycle;
- } fuse_life_cycle;
+ } num;
+ } SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES;
struct packed{
struct packed{
logic next;
logic load_next;
- } lms_verify;
- } fuse_lms_verify;
+ } debug_intent;
+ } SS_DEBUG_INTENT;
struct packed{
struct packed{
logic [31:0] next;
logic load_next;
- } lms_revocation;
- } fuse_lms_revocation;
+ } data;
+ } [4-1:0]SS_STRAP_GENERIC;
struct packed{
struct packed{
- logic [15:0] next;
+ logic next;
logic load_next;
- } soc_stepping_id;
- } fuse_soc_stepping_id;
+ } MANUF_DBG_UNLOCK_REQ;
+ struct packed{
+ logic next;
+ logic load_next;
+ } PROD_DBG_UNLOCK_REQ;
+ struct packed{
+ logic next;
+ logic load_next;
+ } UDS_PROGRAM_REQ;
+ } SS_DBG_MANUF_SERVICE_REG_REQ;
+ struct packed{
+ struct packed{
+ logic next;
+ logic load_next;
+ } MANUF_DBG_UNLOCK_SUCCESS;
+ struct packed{
+ logic next;
+ logic load_next;
+ } MANUF_DBG_UNLOCK_FAIL;
+ struct packed{
+ logic next;
+ logic load_next;
+ } MANUF_DBG_UNLOCK_IN_PROGRESS;
+ struct packed{
+ logic next;
+ logic load_next;
+ } PROD_DBG_UNLOCK_SUCCESS;
+ struct packed{
+ logic next;
+ logic load_next;
+ } PROD_DBG_UNLOCK_FAIL;
+ struct packed{
+ logic next;
+ logic load_next;
+ } PROD_DBG_UNLOCK_IN_PROGRESS;
+ struct packed{
+ logic next;
+ logic load_next;
+ } UDS_PROGRAM_SUCCESS;
+ struct packed{
+ logic next;
+ logic load_next;
+ } UDS_PROGRAM_FAIL;
+ struct packed{
+ logic next;
+ logic load_next;
+ } UDS_PROGRAM_IN_PROGRESS;
+ } SS_DBG_MANUF_SERVICE_REG_RSP;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } LEVEL;
+ } [2-1:0]SS_SOC_DBG_UNLOCK_LEVEL;
+ struct packed{
+ struct packed{
+ logic [31:0] next;
+ logic load_next;
+ } go;
+ } [4-1:0]SS_GENERIC_FW_EXEC_CTRL;
struct packed{
struct packed{
logic [31:0] next;
@@ -1298,7 +1524,7 @@ module soc_ifc_reg (
} idevid_csr_ready;
struct packed{
logic value;
- } ready_for_fw;
+ } ready_for_mb_processing;
struct packed{
logic value;
} ready_for_runtime;
@@ -1466,6 +1692,31 @@ module soc_ifc_reg (
logic [31:0] value;
} RSVD;
} [2-1:0]CPTRA_RSVD_REG;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } cap;
+ } CPTRA_HW_CAPABILITIES;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } cap;
+ } CPTRA_FW_CAPABILITIES;
+ struct packed{
+ struct packed{
+ logic value;
+ } lock;
+ } CPTRA_CAP_LOCK;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } hash;
+ } [12-1:0]CPTRA_OWNER_PK_HASH;
+ struct packed{
+ struct packed{
+ logic value;
+ } lock;
+ } CPTRA_OWNER_PK_HASH_LOCK;
struct packed{
struct packed{
logic [31:0] value;
@@ -1481,16 +1732,11 @@ module soc_ifc_reg (
logic [31:0] value;
} hash;
} [12-1:0]fuse_key_manifest_pk_hash;
- struct packed{
- struct packed{
- logic [3:0] value;
- } mask;
- } fuse_key_manifest_pk_hash_mask;
struct packed{
struct packed{
logic [31:0] value;
- } hash;
- } [12-1:0]fuse_owner_pk_hash;
+ } mask;
+ } [8-1:0]fuse_key_manifest_pk_hash_mask;
struct packed{
struct packed{
logic [31:0] value;
@@ -1516,21 +1762,16 @@ module soc_ifc_reg (
logic [31:0] value;
} hsm_id;
} [4-1:0]fuse_idevid_manuf_hsm_id;
- struct packed{
- struct packed{
- logic [1:0] value;
- } life_cycle;
- } fuse_life_cycle;
- struct packed{
- struct packed{
- logic value;
- } lms_verify;
- } fuse_lms_verify;
struct packed{
struct packed{
logic [31:0] value;
} lms_revocation;
} fuse_lms_revocation;
+ struct packed{
+ struct packed{
+ logic [3:0] value;
+ } mldsa_revocation;
+ } fuse_mldsa_revocation;
struct packed{
struct packed{
logic [15:0] value;
@@ -1539,100 +1780,225 @@ module soc_ifc_reg (
struct packed{
struct packed{
logic [31:0] value;
- } key;
- } [8-1:0]internal_obf_key;
+ } token;
+ } [4-1:0]fuse_manuf_dbg_unlock_token;
struct packed{
struct packed{
- logic value;
- } lock;
- } internal_iccm_lock;
+ logic [31:0] value;
+ } addr_l;
+ } SS_CALIPTRA_BASE_ADDR_L;
struct packed{
struct packed{
- logic value;
- } core_rst;
- } internal_fw_update_reset;
+ logic [31:0] value;
+ } addr_h;
+ } SS_CALIPTRA_BASE_ADDR_H;
struct packed{
struct packed{
- logic [7:0] value;
- } wait_cycles;
- } internal_fw_update_reset_wait_cycles;
+ logic [31:0] value;
+ } addr_l;
+ } SS_MCI_BASE_ADDR_L;
struct packed{
struct packed{
logic [31:0] value;
- } vec;
- } internal_nmi_vector;
+ } addr_h;
+ } SS_MCI_BASE_ADDR_H;
struct packed{
struct packed{
- logic value;
- } mask_iccm_ecc_unc;
- struct packed{
- logic value;
- } mask_dccm_ecc_unc;
- struct packed{
- logic value;
- } mask_nmi_pin;
- } internal_hw_error_fatal_mask;
+ logic [31:0] value;
+ } addr_l;
+ } SS_RECOVERY_IFC_BASE_ADDR_L;
struct packed{
struct packed{
- logic value;
- } mask_mbox_prot_no_lock;
- struct packed{
- logic value;
- } mask_mbox_prot_ooo;
+ logic [31:0] value;
+ } addr_h;
+ } SS_RECOVERY_IFC_BASE_ADDR_H;
+ struct packed{
struct packed{
- logic value;
- } mask_mbox_ecc_unc;
- } internal_hw_error_non_fatal_mask;
+ logic [31:0] value;
+ } addr_l;
+ } SS_OTP_FC_BASE_ADDR_L;
struct packed{
struct packed{
logic [31:0] value;
- } mask;
- } internal_fw_error_fatal_mask;
+ } addr_h;
+ } SS_OTP_FC_BASE_ADDR_H;
struct packed{
struct packed{
logic [31:0] value;
- } mask;
- } internal_fw_error_non_fatal_mask;
+ } addr_l;
+ } SS_UDS_SEED_BASE_ADDR_L;
struct packed{
struct packed{
logic [31:0] value;
- } count_l;
- } internal_rv_mtime_l;
+ } addr_h;
+ } SS_UDS_SEED_BASE_ADDR_H;
struct packed{
struct packed{
logic [31:0] value;
- } count_h;
- } internal_rv_mtime_h;
+ } offset;
+ } SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET;
struct packed{
struct packed{
logic [31:0] value;
- } compare_l;
- } internal_rv_mtimecmp_l;
+ } num;
+ } SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES;
+ struct packed{
+ struct packed{
+ logic value;
+ } debug_intent;
+ } SS_DEBUG_INTENT;
struct packed{
struct packed{
logic [31:0] value;
- } compare_h;
- } internal_rv_mtimecmp_h;
+ } data;
+ } [4-1:0]SS_STRAP_GENERIC;
struct packed{
struct packed{
- struct packed{
- logic value;
- } error_en;
- struct packed{
- logic value;
- } notif_en;
- } global_intr_en_r;
+ logic value;
+ } MANUF_DBG_UNLOCK_REQ;
struct packed{
- struct packed{
- logic value;
- } error_internal_en;
- struct packed{
- logic value;
- } error_inv_dev_en;
- struct packed{
- logic value;
- } error_cmd_fail_en;
- struct packed{
+ logic value;
+ } PROD_DBG_UNLOCK_REQ;
+ struct packed{
+ logic value;
+ } UDS_PROGRAM_REQ;
+ } SS_DBG_MANUF_SERVICE_REG_REQ;
+ struct packed{
+ struct packed{
+ logic value;
+ } MANUF_DBG_UNLOCK_SUCCESS;
+ struct packed{
+ logic value;
+ } MANUF_DBG_UNLOCK_FAIL;
+ struct packed{
+ logic value;
+ } MANUF_DBG_UNLOCK_IN_PROGRESS;
+ struct packed{
+ logic value;
+ } PROD_DBG_UNLOCK_SUCCESS;
+ struct packed{
+ logic value;
+ } PROD_DBG_UNLOCK_FAIL;
+ struct packed{
+ logic value;
+ } PROD_DBG_UNLOCK_IN_PROGRESS;
+ struct packed{
+ logic value;
+ } UDS_PROGRAM_SUCCESS;
+ struct packed{
+ logic value;
+ } UDS_PROGRAM_FAIL;
+ struct packed{
+ logic value;
+ } UDS_PROGRAM_IN_PROGRESS;
+ } SS_DBG_MANUF_SERVICE_REG_RSP;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } LEVEL;
+ } [2-1:0]SS_SOC_DBG_UNLOCK_LEVEL;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } go;
+ } [4-1:0]SS_GENERIC_FW_EXEC_CTRL;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } key;
+ } [8-1:0]internal_obf_key;
+ struct packed{
+ struct packed{
+ logic value;
+ } lock;
+ } internal_iccm_lock;
+ struct packed{
+ struct packed{
+ logic value;
+ } core_rst;
+ } internal_fw_update_reset;
+ struct packed{
+ struct packed{
+ logic [7:0] value;
+ } wait_cycles;
+ } internal_fw_update_reset_wait_cycles;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } vec;
+ } internal_nmi_vector;
+ struct packed{
+ struct packed{
+ logic value;
+ } mask_iccm_ecc_unc;
+ struct packed{
+ logic value;
+ } mask_dccm_ecc_unc;
+ struct packed{
+ logic value;
+ } mask_nmi_pin;
+ } internal_hw_error_fatal_mask;
+ struct packed{
+ struct packed{
+ logic value;
+ } mask_mbox_prot_no_lock;
+ struct packed{
+ logic value;
+ } mask_mbox_prot_ooo;
+ struct packed{
+ logic value;
+ } mask_mbox_ecc_unc;
+ } internal_hw_error_non_fatal_mask;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } mask;
+ } internal_fw_error_fatal_mask;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } mask;
+ } internal_fw_error_non_fatal_mask;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } count_l;
+ } internal_rv_mtime_l;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } count_h;
+ } internal_rv_mtime_h;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } compare_l;
+ } internal_rv_mtimecmp_l;
+ struct packed{
+ struct packed{
+ logic [31:0] value;
+ } compare_h;
+ } internal_rv_mtimecmp_h;
+ struct packed{
+ struct packed{
+ struct packed{
+ logic value;
+ } error_en;
+ struct packed{
+ logic value;
+ } notif_en;
+ } global_intr_en_r;
+ struct packed{
+ struct packed{
+ logic value;
+ } error_internal_en;
+ struct packed{
+ logic value;
+ } error_inv_dev_en;
+ struct packed{
+ logic value;
+ } error_cmd_fail_en;
+ struct packed{
logic value;
} error_bad_fuse_en;
struct packed{
@@ -2259,27 +2625,27 @@ module soc_ifc_reg (
end
end
assign hwif_out.CPTRA_FLOW_STATUS.idevid_csr_ready.value = field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value;
- // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_fw
+ // Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_mb_processing
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value;
+ next_c = field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value;
load_next_c = '0;
if(decoded_reg_strb.CPTRA_FLOW_STATUS && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
- next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value & ~decoded_wr_biten[28:28]) | (decoded_wr_data[28:28] & decoded_wr_biten[28:28]);
+ next_c = (field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value & ~decoded_wr_biten[28:28]) | (decoded_wr_data[28:28] & decoded_wr_biten[28:28]);
load_next_c = '1;
end
- field_combo.CPTRA_FLOW_STATUS.ready_for_fw.next = next_c;
- field_combo.CPTRA_FLOW_STATUS.ready_for_fw.load_next = load_next_c;
+ field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.next = next_c;
+ field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.load_next = load_next_c;
end
always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
if(~hwif_in.cptra_rst_b) begin
- field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= 1'h0;
- end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_fw.load_next) begin
- field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_fw.next;
+ field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value <= 1'h0;
+ end else if(field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.load_next) begin
+ field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value <= field_combo.CPTRA_FLOW_STATUS.ready_for_mb_processing.next;
end
end
- assign hwif_out.CPTRA_FLOW_STATUS.ready_for_fw.value = field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value;
+ assign hwif_out.CPTRA_FLOW_STATUS.ready_for_mb_processing.value = field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value;
// Field: soc_ifc_reg.CPTRA_FLOW_STATUS.ready_for_runtime
always_comb begin
automatic logic [0:0] next_c;
@@ -3076,6 +3442,111 @@ module soc_ifc_reg (
end
end
end
+ // Field: soc_ifc_reg.CPTRA_HW_CAPABILITIES.cap
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.CPTRA_HW_CAPABILITIES.cap.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.CPTRA_HW_CAPABILITIES && decoded_req_is_wr && !(hwif_in.CPTRA_HW_CAPABILITIES.cap.swwel)) begin // SW write
+ next_c = (field_storage.CPTRA_HW_CAPABILITIES.cap.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.CPTRA_HW_CAPABILITIES.cap.next = next_c;
+ field_combo.CPTRA_HW_CAPABILITIES.cap.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.CPTRA_HW_CAPABILITIES.cap.value <= 32'h0;
+ end else if(field_combo.CPTRA_HW_CAPABILITIES.cap.load_next) begin
+ field_storage.CPTRA_HW_CAPABILITIES.cap.value <= field_combo.CPTRA_HW_CAPABILITIES.cap.next;
+ end
+ end
+ // Field: soc_ifc_reg.CPTRA_FW_CAPABILITIES.cap
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.CPTRA_FW_CAPABILITIES.cap.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.CPTRA_FW_CAPABILITIES && decoded_req_is_wr && !(hwif_in.CPTRA_FW_CAPABILITIES.cap.swwel)) begin // SW write
+ next_c = (field_storage.CPTRA_FW_CAPABILITIES.cap.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.CPTRA_FW_CAPABILITIES.cap.next = next_c;
+ field_combo.CPTRA_FW_CAPABILITIES.cap.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.CPTRA_FW_CAPABILITIES.cap.value <= 32'h0;
+ end else if(field_combo.CPTRA_FW_CAPABILITIES.cap.load_next) begin
+ field_storage.CPTRA_FW_CAPABILITIES.cap.value <= field_combo.CPTRA_FW_CAPABILITIES.cap.next;
+ end
+ end
+ // Field: soc_ifc_reg.CPTRA_CAP_LOCK.lock
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.CPTRA_CAP_LOCK.lock.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.CPTRA_CAP_LOCK && decoded_req_is_wr && !(hwif_in.CPTRA_CAP_LOCK.lock.swwel)) begin // SW write
+ next_c = (field_storage.CPTRA_CAP_LOCK.lock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end
+ field_combo.CPTRA_CAP_LOCK.lock.next = next_c;
+ field_combo.CPTRA_CAP_LOCK.lock.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.CPTRA_CAP_LOCK.lock.value <= 1'h0;
+ end else if(field_combo.CPTRA_CAP_LOCK.lock.load_next) begin
+ field_storage.CPTRA_CAP_LOCK.lock.value <= field_combo.CPTRA_CAP_LOCK.lock.next;
+ end
+ end
+ assign hwif_out.CPTRA_CAP_LOCK.lock.value = field_storage.CPTRA_CAP_LOCK.lock.value;
+ for(genvar i0=0; i0<12; i0++) begin
+ // Field: soc_ifc_reg.CPTRA_OWNER_PK_HASH[].hash
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.CPTRA_OWNER_PK_HASH[i0].hash.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.CPTRA_OWNER_PK_HASH[i0] && decoded_req_is_wr && !(hwif_in.CPTRA_OWNER_PK_HASH[i0].hash.swwel)) begin // SW write
+ next_c = (field_storage.CPTRA_OWNER_PK_HASH[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.CPTRA_OWNER_PK_HASH[i0].hash.next = next_c;
+ field_combo.CPTRA_OWNER_PK_HASH[i0].hash.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.CPTRA_OWNER_PK_HASH[i0].hash.value <= 32'h0;
+ end else if(field_combo.CPTRA_OWNER_PK_HASH[i0].hash.load_next) begin
+ field_storage.CPTRA_OWNER_PK_HASH[i0].hash.value <= field_combo.CPTRA_OWNER_PK_HASH[i0].hash.next;
+ end
+ end
+ assign hwif_out.CPTRA_OWNER_PK_HASH[i0].hash.value = field_storage.CPTRA_OWNER_PK_HASH[i0].hash.value;
+ end
+ // Field: soc_ifc_reg.CPTRA_OWNER_PK_HASH_LOCK.lock
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.CPTRA_OWNER_PK_HASH_LOCK.lock.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.CPTRA_OWNER_PK_HASH_LOCK && decoded_req_is_wr && hwif_in.CPTRA_OWNER_PK_HASH_LOCK.lock.swwe) begin // SW write
+ next_c = (field_storage.CPTRA_OWNER_PK_HASH_LOCK.lock.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end
+ field_combo.CPTRA_OWNER_PK_HASH_LOCK.lock.next = next_c;
+ field_combo.CPTRA_OWNER_PK_HASH_LOCK.lock.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.CPTRA_OWNER_PK_HASH_LOCK.lock.value <= 1'h0;
+ end else if(field_combo.CPTRA_OWNER_PK_HASH_LOCK.lock.load_next) begin
+ field_storage.CPTRA_OWNER_PK_HASH_LOCK.lock.value <= field_combo.CPTRA_OWNER_PK_HASH_LOCK.lock.next;
+ end
+ end
+ assign hwif_out.CPTRA_OWNER_PK_HASH_LOCK.lock.value = field_storage.CPTRA_OWNER_PK_HASH_LOCK.lock.value;
for(genvar i0=0; i0<16; i0++) begin
// Field: soc_ifc_reg.fuse_uds_seed[].seed
always_comb begin
@@ -3142,254 +3613,907 @@ module soc_ifc_reg (
field_combo.fuse_key_manifest_pk_hash[i0].hash.next = next_c;
field_combo.fuse_key_manifest_pk_hash[i0].hash.load_next = load_next_c;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= 32'h0;
- end else if(field_combo.fuse_key_manifest_pk_hash[i0].hash.load_next) begin
- field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= field_combo.fuse_key_manifest_pk_hash[i0].hash.next;
- end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= 32'h0;
+ end else if(field_combo.fuse_key_manifest_pk_hash[i0].hash.load_next) begin
+ field_storage.fuse_key_manifest_pk_hash[i0].hash.value <= field_combo.fuse_key_manifest_pk_hash[i0].hash.next;
+ end
+ end
+ assign hwif_out.fuse_key_manifest_pk_hash[i0].hash.value = field_storage.fuse_key_manifest_pk_hash[i0].hash.value;
+ end
+ for(genvar i0=0; i0<8; i0++) begin
+ // Field: soc_ifc_reg.fuse_key_manifest_pk_hash_mask[].mask
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_key_manifest_pk_hash_mask[i0] && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash_mask[i0].mask.swwel)) begin // SW write
+ next_c = (field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.next = next_c;
+ field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value <= 32'h0;
+ end else if(field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.load_next) begin
+ field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value <= field_combo.fuse_key_manifest_pk_hash_mask[i0].mask.next;
+ end
+ end
+ assign hwif_out.fuse_key_manifest_pk_hash_mask[i0].mask.value = field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value;
+ end
+ // Field: soc_ifc_reg.fuse_fmc_key_manifest_svn.svn
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_fmc_key_manifest_svn.svn.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_fmc_key_manifest_svn && decoded_req_is_wr && !(hwif_in.fuse_fmc_key_manifest_svn.svn.swwel)) begin // SW write
+ next_c = (field_storage.fuse_fmc_key_manifest_svn.svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_fmc_key_manifest_svn.svn.next = next_c;
+ field_combo.fuse_fmc_key_manifest_svn.svn.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_fmc_key_manifest_svn.svn.value <= 32'h0;
+ end else if(field_combo.fuse_fmc_key_manifest_svn.svn.load_next) begin
+ field_storage.fuse_fmc_key_manifest_svn.svn.value <= field_combo.fuse_fmc_key_manifest_svn.svn.next;
+ end
+ end
+ assign hwif_out.fuse_fmc_key_manifest_svn.svn.value = field_storage.fuse_fmc_key_manifest_svn.svn.value;
+ for(genvar i0=0; i0<4; i0++) begin
+ // Field: soc_ifc_reg.fuse_runtime_svn[].svn
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_runtime_svn[i0].svn.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_runtime_svn[i0] && decoded_req_is_wr && !(hwif_in.fuse_runtime_svn[i0].svn.swwel)) begin // SW write
+ next_c = (field_storage.fuse_runtime_svn[i0].svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_runtime_svn[i0].svn.next = next_c;
+ field_combo.fuse_runtime_svn[i0].svn.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_runtime_svn[i0].svn.value <= 32'h0;
+ end else if(field_combo.fuse_runtime_svn[i0].svn.load_next) begin
+ field_storage.fuse_runtime_svn[i0].svn.value <= field_combo.fuse_runtime_svn[i0].svn.next;
+ end
+ end
+ assign hwif_out.fuse_runtime_svn[i0].svn.value = field_storage.fuse_runtime_svn[i0].svn.value;
+ end
+ // Field: soc_ifc_reg.fuse_anti_rollback_disable.dis
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_anti_rollback_disable.dis.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_anti_rollback_disable && decoded_req_is_wr && !(hwif_in.fuse_anti_rollback_disable.dis.swwel)) begin // SW write
+ next_c = (field_storage.fuse_anti_rollback_disable.dis.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_anti_rollback_disable.dis.next = next_c;
+ field_combo.fuse_anti_rollback_disable.dis.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_anti_rollback_disable.dis.value <= 1'h0;
+ end else if(field_combo.fuse_anti_rollback_disable.dis.load_next) begin
+ field_storage.fuse_anti_rollback_disable.dis.value <= field_combo.fuse_anti_rollback_disable.dis.next;
+ end
+ end
+ assign hwif_out.fuse_anti_rollback_disable.dis.value = field_storage.fuse_anti_rollback_disable.dis.value;
+ for(genvar i0=0; i0<24; i0++) begin
+ // Field: soc_ifc_reg.fuse_idevid_cert_attr[].cert
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_idevid_cert_attr[i0].cert.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_idevid_cert_attr[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_cert_attr[i0].cert.swwel)) begin // SW write
+ next_c = (field_storage.fuse_idevid_cert_attr[i0].cert.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_idevid_cert_attr[i0].cert.next = next_c;
+ field_combo.fuse_idevid_cert_attr[i0].cert.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_idevid_cert_attr[i0].cert.value <= 32'h0;
+ end else if(field_combo.fuse_idevid_cert_attr[i0].cert.load_next) begin
+ field_storage.fuse_idevid_cert_attr[i0].cert.value <= field_combo.fuse_idevid_cert_attr[i0].cert.next;
+ end
+ end
+ assign hwif_out.fuse_idevid_cert_attr[i0].cert.value = field_storage.fuse_idevid_cert_attr[i0].cert.value;
+ end
+ for(genvar i0=0; i0<4; i0++) begin
+ // Field: soc_ifc_reg.fuse_idevid_manuf_hsm_id[].hsm_id
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_manuf_hsm_id[i0].hsm_id.swwel)) begin // SW write
+ next_c = (field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.next = next_c;
+ field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= 32'h0;
+ end else if(field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.load_next) begin
+ field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.next;
+ end
+ end
+ assign hwif_out.fuse_idevid_manuf_hsm_id[i0].hsm_id.value = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value;
+ end
+ // Field: soc_ifc_reg.fuse_lms_revocation.lms_revocation
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_lms_revocation.lms_revocation.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_lms_revocation && decoded_req_is_wr && !(hwif_in.fuse_lms_revocation.lms_revocation.swwel)) begin // SW write
+ next_c = (field_storage.fuse_lms_revocation.lms_revocation.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_lms_revocation.lms_revocation.next = next_c;
+ field_combo.fuse_lms_revocation.lms_revocation.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_lms_revocation.lms_revocation.value <= 32'h0;
+ end else if(field_combo.fuse_lms_revocation.lms_revocation.load_next) begin
+ field_storage.fuse_lms_revocation.lms_revocation.value <= field_combo.fuse_lms_revocation.lms_revocation.next;
+ end
+ end
+ assign hwif_out.fuse_lms_revocation.lms_revocation.value = field_storage.fuse_lms_revocation.lms_revocation.value;
+ // Field: soc_ifc_reg.fuse_mldsa_revocation.mldsa_revocation
+ always_comb begin
+ automatic logic [3:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_mldsa_revocation.mldsa_revocation.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_mldsa_revocation && decoded_req_is_wr && !(hwif_in.fuse_mldsa_revocation.mldsa_revocation.swwel)) begin // SW write
+ next_c = (field_storage.fuse_mldsa_revocation.mldsa_revocation.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_mldsa_revocation.mldsa_revocation.next = next_c;
+ field_combo.fuse_mldsa_revocation.mldsa_revocation.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_mldsa_revocation.mldsa_revocation.value <= 4'h0;
+ end else if(field_combo.fuse_mldsa_revocation.mldsa_revocation.load_next) begin
+ field_storage.fuse_mldsa_revocation.mldsa_revocation.value <= field_combo.fuse_mldsa_revocation.mldsa_revocation.next;
+ end
+ end
+ assign hwif_out.fuse_mldsa_revocation.mldsa_revocation.value = field_storage.fuse_mldsa_revocation.mldsa_revocation.value;
+ // Field: soc_ifc_reg.fuse_soc_stepping_id.soc_stepping_id
+ always_comb begin
+ automatic logic [15:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_soc_stepping_id.soc_stepping_id.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_soc_stepping_id && decoded_req_is_wr && !(hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel)) begin // SW write
+ next_c = (field_storage.fuse_soc_stepping_id.soc_stepping_id.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_soc_stepping_id.soc_stepping_id.next = next_c;
+ field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= 16'h0;
+ end else if(field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next) begin
+ field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= field_combo.fuse_soc_stepping_id.soc_stepping_id.next;
+ end
+ end
+ assign hwif_out.fuse_soc_stepping_id.soc_stepping_id.value = field_storage.fuse_soc_stepping_id.soc_stepping_id.value;
+ for(genvar i0=0; i0<4; i0++) begin
+ // Field: soc_ifc_reg.fuse_manuf_dbg_unlock_token[].token
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.fuse_manuf_dbg_unlock_token[i0].token.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.fuse_manuf_dbg_unlock_token[i0] && decoded_req_is_wr && !(hwif_in.fuse_manuf_dbg_unlock_token[i0].token.swwel)) begin // SW write
+ next_c = (field_storage.fuse_manuf_dbg_unlock_token[i0].token.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.fuse_manuf_dbg_unlock_token[i0].token.next = next_c;
+ field_combo.fuse_manuf_dbg_unlock_token[i0].token.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.fuse_manuf_dbg_unlock_token[i0].token.value <= 32'h0;
+ end else if(field_combo.fuse_manuf_dbg_unlock_token[i0].token.load_next) begin
+ field_storage.fuse_manuf_dbg_unlock_token[i0].token.value <= field_combo.fuse_manuf_dbg_unlock_token[i0].token.next;
+ end
+ end
+ assign hwif_out.fuse_manuf_dbg_unlock_token[i0].token.value = field_storage.fuse_manuf_dbg_unlock_token[i0].token.value;
+ end
+ // Field: soc_ifc_reg.SS_CALIPTRA_BASE_ADDR_L.addr_l
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L && decoded_req_is_wr && !(hwif_in.SS_CALIPTRA_BASE_ADDR_L.addr_l.swwel)) begin // SW write
+ next_c = (field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_CALIPTRA_BASE_ADDR_L.addr_l.we) begin // HW Write - we
+ next_c = hwif_in.SS_CALIPTRA_BASE_ADDR_L.addr_l.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_CALIPTRA_BASE_ADDR_L.addr_l.next = next_c;
+ field_combo.SS_CALIPTRA_BASE_ADDR_L.addr_l.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value <= 32'h0;
+ end else if(field_combo.SS_CALIPTRA_BASE_ADDR_L.addr_l.load_next) begin
+ field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value <= field_combo.SS_CALIPTRA_BASE_ADDR_L.addr_l.next;
+ end
+ end
+ assign hwif_out.SS_CALIPTRA_BASE_ADDR_L.addr_l.value = field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value;
+ // Field: soc_ifc_reg.SS_CALIPTRA_BASE_ADDR_H.addr_h
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H && decoded_req_is_wr && !(hwif_in.SS_CALIPTRA_BASE_ADDR_H.addr_h.swwel)) begin // SW write
+ next_c = (field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_CALIPTRA_BASE_ADDR_H.addr_h.we) begin // HW Write - we
+ next_c = hwif_in.SS_CALIPTRA_BASE_ADDR_H.addr_h.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_CALIPTRA_BASE_ADDR_H.addr_h.next = next_c;
+ field_combo.SS_CALIPTRA_BASE_ADDR_H.addr_h.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value <= 32'h0;
+ end else if(field_combo.SS_CALIPTRA_BASE_ADDR_H.addr_h.load_next) begin
+ field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value <= field_combo.SS_CALIPTRA_BASE_ADDR_H.addr_h.next;
+ end
+ end
+ assign hwif_out.SS_CALIPTRA_BASE_ADDR_H.addr_h.value = field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value;
+ // Field: soc_ifc_reg.SS_MCI_BASE_ADDR_L.addr_l
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_MCI_BASE_ADDR_L.addr_l.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_MCI_BASE_ADDR_L && decoded_req_is_wr && !(hwif_in.SS_MCI_BASE_ADDR_L.addr_l.swwel)) begin // SW write
+ next_c = (field_storage.SS_MCI_BASE_ADDR_L.addr_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_MCI_BASE_ADDR_L.addr_l.we) begin // HW Write - we
+ next_c = hwif_in.SS_MCI_BASE_ADDR_L.addr_l.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_MCI_BASE_ADDR_L.addr_l.next = next_c;
+ field_combo.SS_MCI_BASE_ADDR_L.addr_l.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_MCI_BASE_ADDR_L.addr_l.value <= 32'h0;
+ end else if(field_combo.SS_MCI_BASE_ADDR_L.addr_l.load_next) begin
+ field_storage.SS_MCI_BASE_ADDR_L.addr_l.value <= field_combo.SS_MCI_BASE_ADDR_L.addr_l.next;
+ end
+ end
+ assign hwif_out.SS_MCI_BASE_ADDR_L.addr_l.value = field_storage.SS_MCI_BASE_ADDR_L.addr_l.value;
+ // Field: soc_ifc_reg.SS_MCI_BASE_ADDR_H.addr_h
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_MCI_BASE_ADDR_H.addr_h.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_MCI_BASE_ADDR_H && decoded_req_is_wr && !(hwif_in.SS_MCI_BASE_ADDR_H.addr_h.swwel)) begin // SW write
+ next_c = (field_storage.SS_MCI_BASE_ADDR_H.addr_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_MCI_BASE_ADDR_H.addr_h.we) begin // HW Write - we
+ next_c = hwif_in.SS_MCI_BASE_ADDR_H.addr_h.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_MCI_BASE_ADDR_H.addr_h.next = next_c;
+ field_combo.SS_MCI_BASE_ADDR_H.addr_h.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_MCI_BASE_ADDR_H.addr_h.value <= 32'h0;
+ end else if(field_combo.SS_MCI_BASE_ADDR_H.addr_h.load_next) begin
+ field_storage.SS_MCI_BASE_ADDR_H.addr_h.value <= field_combo.SS_MCI_BASE_ADDR_H.addr_h.next;
+ end
+ end
+ assign hwif_out.SS_MCI_BASE_ADDR_H.addr_h.value = field_storage.SS_MCI_BASE_ADDR_H.addr_h.value;
+ // Field: soc_ifc_reg.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_L && decoded_req_is_wr && !(hwif_in.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.swwel)) begin // SW write
+ next_c = (field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.we) begin // HW Write - we
+ next_c = hwif_in.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.next = next_c;
+ field_combo.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value <= 32'h0;
+ end else if(field_combo.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.load_next) begin
+ field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value <= field_combo.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.next;
+ end
+ end
+ assign hwif_out.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value = field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value;
+ // Field: soc_ifc_reg.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_H && decoded_req_is_wr && !(hwif_in.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.swwel)) begin // SW write
+ next_c = (field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.we) begin // HW Write - we
+ next_c = hwif_in.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.next = next_c;
+ field_combo.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value <= 32'h0;
+ end else if(field_combo.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.load_next) begin
+ field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value <= field_combo.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.next;
+ end
+ end
+ assign hwif_out.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value = field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value;
+ // Field: soc_ifc_reg.SS_OTP_FC_BASE_ADDR_L.addr_l
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_OTP_FC_BASE_ADDR_L && decoded_req_is_wr && !(hwif_in.SS_OTP_FC_BASE_ADDR_L.addr_l.swwel)) begin // SW write
+ next_c = (field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_OTP_FC_BASE_ADDR_L.addr_l.we) begin // HW Write - we
+ next_c = hwif_in.SS_OTP_FC_BASE_ADDR_L.addr_l.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_OTP_FC_BASE_ADDR_L.addr_l.next = next_c;
+ field_combo.SS_OTP_FC_BASE_ADDR_L.addr_l.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value <= 32'h0;
+ end else if(field_combo.SS_OTP_FC_BASE_ADDR_L.addr_l.load_next) begin
+ field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value <= field_combo.SS_OTP_FC_BASE_ADDR_L.addr_l.next;
+ end
+ end
+ assign hwif_out.SS_OTP_FC_BASE_ADDR_L.addr_l.value = field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value;
+ // Field: soc_ifc_reg.SS_OTP_FC_BASE_ADDR_H.addr_h
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_OTP_FC_BASE_ADDR_H && decoded_req_is_wr && !(hwif_in.SS_OTP_FC_BASE_ADDR_H.addr_h.swwel)) begin // SW write
+ next_c = (field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_OTP_FC_BASE_ADDR_H.addr_h.we) begin // HW Write - we
+ next_c = hwif_in.SS_OTP_FC_BASE_ADDR_H.addr_h.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_OTP_FC_BASE_ADDR_H.addr_h.next = next_c;
+ field_combo.SS_OTP_FC_BASE_ADDR_H.addr_h.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value <= 32'h0;
+ end else if(field_combo.SS_OTP_FC_BASE_ADDR_H.addr_h.load_next) begin
+ field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value <= field_combo.SS_OTP_FC_BASE_ADDR_H.addr_h.next;
+ end
+ end
+ assign hwif_out.SS_OTP_FC_BASE_ADDR_H.addr_h.value = field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value;
+ // Field: soc_ifc_reg.SS_UDS_SEED_BASE_ADDR_L.addr_l
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_L && decoded_req_is_wr && !(hwif_in.SS_UDS_SEED_BASE_ADDR_L.addr_l.swwel)) begin // SW write
+ next_c = (field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_UDS_SEED_BASE_ADDR_L.addr_l.we) begin // HW Write - we
+ next_c = hwif_in.SS_UDS_SEED_BASE_ADDR_L.addr_l.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_UDS_SEED_BASE_ADDR_L.addr_l.next = next_c;
+ field_combo.SS_UDS_SEED_BASE_ADDR_L.addr_l.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value <= 32'h0;
+ end else if(field_combo.SS_UDS_SEED_BASE_ADDR_L.addr_l.load_next) begin
+ field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value <= field_combo.SS_UDS_SEED_BASE_ADDR_L.addr_l.next;
+ end
+ end
+ assign hwif_out.SS_UDS_SEED_BASE_ADDR_L.addr_l.value = field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value;
+ // Field: soc_ifc_reg.SS_UDS_SEED_BASE_ADDR_H.addr_h
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_H && decoded_req_is_wr && !(hwif_in.SS_UDS_SEED_BASE_ADDR_H.addr_h.swwel)) begin // SW write
+ next_c = (field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_UDS_SEED_BASE_ADDR_H.addr_h.we) begin // HW Write - we
+ next_c = hwif_in.SS_UDS_SEED_BASE_ADDR_H.addr_h.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_UDS_SEED_BASE_ADDR_H.addr_h.next = next_c;
+ field_combo.SS_UDS_SEED_BASE_ADDR_H.addr_h.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value <= 32'h0;
+ end else if(field_combo.SS_UDS_SEED_BASE_ADDR_H.addr_h.load_next) begin
+ field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value <= field_combo.SS_UDS_SEED_BASE_ADDR_H.addr_h.next;
+ end
+ end
+ assign hwif_out.SS_UDS_SEED_BASE_ADDR_H.addr_h.value = field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value;
+ // Field: soc_ifc_reg.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET && decoded_req_is_wr && !(hwif_in.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.swwel)) begin // SW write
+ next_c = (field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.we) begin // HW Write - we
+ next_c = hwif_in.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.next = next_c;
+ field_combo.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value <= 32'h0;
+ end else if(field_combo.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.load_next) begin
+ field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value <= field_combo.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.next;
+ end
+ end
+ assign hwif_out.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value = field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value;
+ // Field: soc_ifc_reg.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES && decoded_req_is_wr && !(hwif_in.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.swwel)) begin // SW write
+ next_c = (field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.we) begin // HW Write - we
+ next_c = hwif_in.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.next = next_c;
+ field_combo.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+ if(~hwif_in.cptra_pwrgood) begin
+ field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value <= 32'h8;
+ end else if(field_combo.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.load_next) begin
+ field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value <= field_combo.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.next;
end
- assign hwif_out.fuse_key_manifest_pk_hash[i0].hash.value = field_storage.fuse_key_manifest_pk_hash[i0].hash.value;
end
- // Field: soc_ifc_reg.fuse_key_manifest_pk_hash_mask.mask
+ assign hwif_out.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value = field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value;
+ // Field: soc_ifc_reg.SS_DEBUG_INTENT.debug_intent
always_comb begin
- automatic logic [3:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_key_manifest_pk_hash_mask.mask.value;
+ next_c = field_storage.SS_DEBUG_INTENT.debug_intent.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_key_manifest_pk_hash_mask && decoded_req_is_wr && !(hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel)) begin // SW write
- next_c = (field_storage.fuse_key_manifest_pk_hash_mask.mask.value & ~decoded_wr_biten[3:0]) | (decoded_wr_data[3:0] & decoded_wr_biten[3:0]);
+ if(hwif_in.SS_DEBUG_INTENT.debug_intent.we) begin // HW Write - we
+ next_c = hwif_in.SS_DEBUG_INTENT.debug_intent.next;
load_next_c = '1;
end
- field_combo.fuse_key_manifest_pk_hash_mask.mask.next = next_c;
- field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next = load_next_c;
+ field_combo.SS_DEBUG_INTENT.debug_intent.next = next_c;
+ field_combo.SS_DEBUG_INTENT.debug_intent.load_next = load_next_c;
end
always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= 4'h0;
- end else if(field_combo.fuse_key_manifest_pk_hash_mask.mask.load_next) begin
- field_storage.fuse_key_manifest_pk_hash_mask.mask.value <= field_combo.fuse_key_manifest_pk_hash_mask.mask.next;
+ field_storage.SS_DEBUG_INTENT.debug_intent.value <= 1'h0;
+ end else if(field_combo.SS_DEBUG_INTENT.debug_intent.load_next) begin
+ field_storage.SS_DEBUG_INTENT.debug_intent.value <= field_combo.SS_DEBUG_INTENT.debug_intent.next;
end
end
- assign hwif_out.fuse_key_manifest_pk_hash_mask.mask.value = field_storage.fuse_key_manifest_pk_hash_mask.mask.value;
- for(genvar i0=0; i0<12; i0++) begin
- // Field: soc_ifc_reg.fuse_owner_pk_hash[].hash
+ assign hwif_out.SS_DEBUG_INTENT.debug_intent.value = field_storage.SS_DEBUG_INTENT.debug_intent.value;
+ for(genvar i0=0; i0<4; i0++) begin
+ // Field: soc_ifc_reg.SS_STRAP_GENERIC[].data
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_owner_pk_hash[i0].hash.value;
+ next_c = field_storage.SS_STRAP_GENERIC[i0].data.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_owner_pk_hash[i0] && decoded_req_is_wr && !(hwif_in.fuse_owner_pk_hash[i0].hash.swwel)) begin // SW write
- next_c = (field_storage.fuse_owner_pk_hash[i0].hash.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ if(decoded_reg_strb.SS_STRAP_GENERIC[i0] && decoded_req_is_wr && !(hwif_in.SS_STRAP_GENERIC[i0].data.swwel)) begin // SW write
+ next_c = (field_storage.SS_STRAP_GENERIC[i0].data.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_STRAP_GENERIC[i0].data.we) begin // HW Write - we
+ next_c = hwif_in.SS_STRAP_GENERIC[i0].data.next;
load_next_c = '1;
end
- field_combo.fuse_owner_pk_hash[i0].hash.next = next_c;
- field_combo.fuse_owner_pk_hash[i0].hash.load_next = load_next_c;
+ field_combo.SS_STRAP_GENERIC[i0].data.next = next_c;
+ field_combo.SS_STRAP_GENERIC[i0].data.load_next = load_next_c;
end
always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_owner_pk_hash[i0].hash.value <= 32'h0;
- end else if(field_combo.fuse_owner_pk_hash[i0].hash.load_next) begin
- field_storage.fuse_owner_pk_hash[i0].hash.value <= field_combo.fuse_owner_pk_hash[i0].hash.next;
+ field_storage.SS_STRAP_GENERIC[i0].data.value <= 32'h0;
+ end else if(field_combo.SS_STRAP_GENERIC[i0].data.load_next) begin
+ field_storage.SS_STRAP_GENERIC[i0].data.value <= field_combo.SS_STRAP_GENERIC[i0].data.next;
end
end
- assign hwif_out.fuse_owner_pk_hash[i0].hash.value = field_storage.fuse_owner_pk_hash[i0].hash.value;
+ assign hwif_out.SS_STRAP_GENERIC[i0].data.value = field_storage.SS_STRAP_GENERIC[i0].data.value;
end
- // Field: soc_ifc_reg.fuse_fmc_key_manifest_svn.svn
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ
always_comb begin
- automatic logic [31:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_fmc_key_manifest_svn.svn.value;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_fmc_key_manifest_svn && decoded_req_is_wr && !(hwif_in.fuse_fmc_key_manifest_svn.svn.swwel)) begin // SW write
- next_c = (field_storage.fuse_fmc_key_manifest_svn.svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.next;
load_next_c = '1;
end
- field_combo.fuse_fmc_key_manifest_svn.svn.next = next_c;
- field_combo.fuse_fmc_key_manifest_svn.svn.load_next = load_next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.load_next = load_next_c;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_fmc_key_manifest_svn.svn.value <= 32'h0;
- end else if(field_combo.fuse_fmc_key_manifest_svn.svn.load_next) begin
- field_storage.fuse_fmc_key_manifest_svn.svn.value <= field_combo.fuse_fmc_key_manifest_svn.svn.next;
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.next;
end
end
- assign hwif_out.fuse_fmc_key_manifest_svn.svn.value = field_storage.fuse_fmc_key_manifest_svn.svn.value;
- for(genvar i0=0; i0<4; i0++) begin
- // Field: soc_ifc_reg.fuse_runtime_svn[].svn
- always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.fuse_runtime_svn[i0].svn.value;
- load_next_c = '0;
- if(decoded_reg_strb.fuse_runtime_svn[i0] && decoded_req_is_wr && !(hwif_in.fuse_runtime_svn[i0].svn.swwel)) begin // SW write
- next_c = (field_storage.fuse_runtime_svn[i0].svn.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
- load_next_c = '1;
- end
- field_combo.fuse_runtime_svn[i0].svn.next = next_c;
- field_combo.fuse_runtime_svn[i0].svn.load_next = load_next_c;
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value = field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.next;
+ load_next_c = '1;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_runtime_svn[i0].svn.value <= 32'h0;
- end else if(field_combo.fuse_runtime_svn[i0].svn.load_next) begin
- field_storage.fuse_runtime_svn[i0].svn.value <= field_combo.fuse_runtime_svn[i0].svn.next;
- end
+ field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.next;
end
- assign hwif_out.fuse_runtime_svn[i0].svn.value = field_storage.fuse_runtime_svn[i0].svn.value;
end
- // Field: soc_ifc_reg.fuse_anti_rollback_disable.dis
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value = field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_anti_rollback_disable.dis.value;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_anti_rollback_disable && decoded_req_is_wr && !(hwif_in.fuse_anti_rollback_disable.dis.swwel)) begin // SW write
- next_c = (field_storage.fuse_anti_rollback_disable.dis.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.next;
load_next_c = '1;
end
- field_combo.fuse_anti_rollback_disable.dis.next = next_c;
- field_combo.fuse_anti_rollback_disable.dis.load_next = load_next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.load_next = load_next_c;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_anti_rollback_disable.dis.value <= 1'h0;
- end else if(field_combo.fuse_anti_rollback_disable.dis.load_next) begin
- field_storage.fuse_anti_rollback_disable.dis.value <= field_combo.fuse_anti_rollback_disable.dis.next;
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.next;
end
end
- assign hwif_out.fuse_anti_rollback_disable.dis.value = field_storage.fuse_anti_rollback_disable.dis.value;
- for(genvar i0=0; i0<24; i0++) begin
- // Field: soc_ifc_reg.fuse_idevid_cert_attr[].cert
- always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.fuse_idevid_cert_attr[i0].cert.value;
- load_next_c = '0;
- if(decoded_reg_strb.fuse_idevid_cert_attr[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_cert_attr[i0].cert.swwel)) begin // SW write
- next_c = (field_storage.fuse_idevid_cert_attr[i0].cert.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
- load_next_c = '1;
- end
- field_combo.fuse_idevid_cert_attr[i0].cert.next = next_c;
- field_combo.fuse_idevid_cert_attr[i0].cert.load_next = load_next_c;
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value = field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.next;
+ load_next_c = '1;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_idevid_cert_attr[i0].cert.value <= 32'h0;
- end else if(field_combo.fuse_idevid_cert_attr[i0].cert.load_next) begin
- field_storage.fuse_idevid_cert_attr[i0].cert.value <= field_combo.fuse_idevid_cert_attr[i0].cert.next;
- end
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.next;
end
- assign hwif_out.fuse_idevid_cert_attr[i0].cert.value = field_storage.fuse_idevid_cert_attr[i0].cert.value;
end
- for(genvar i0=0; i0<4; i0++) begin
- // Field: soc_ifc_reg.fuse_idevid_manuf_hsm_id[].hsm_id
- always_comb begin
- automatic logic [31:0] next_c;
- automatic logic load_next_c;
- next_c = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value;
- load_next_c = '0;
- if(decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && decoded_req_is_wr && !(hwif_in.fuse_idevid_manuf_hsm_id[i0].hsm_id.swwel)) begin // SW write
- next_c = (field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
- load_next_c = '1;
- end
- field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.next = next_c;
- field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.load_next = load_next_c;
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.next;
+ load_next_c = '1;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= 32'h0;
- end else if(field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.load_next) begin
- field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value <= field_combo.fuse_idevid_manuf_hsm_id[i0].hsm_id.next;
- end
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.next;
end
- assign hwif_out.fuse_idevid_manuf_hsm_id[i0].hsm_id.value = field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value;
end
- // Field: soc_ifc_reg.fuse_life_cycle.life_cycle
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS
always_comb begin
- automatic logic [1:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_life_cycle.life_cycle.value;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_life_cycle && decoded_req_is_wr && !(hwif_in.fuse_life_cycle.life_cycle.swwel)) begin // SW write
- next_c = (field_storage.fuse_life_cycle.life_cycle.value & ~decoded_wr_biten[1:0]) | (decoded_wr_data[1:0] & decoded_wr_biten[1:0]);
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value & ~decoded_wr_biten[2:2]) | (decoded_wr_data[2:2] & decoded_wr_biten[2:2]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.next;
load_next_c = '1;
end
- field_combo.fuse_life_cycle.life_cycle.next = next_c;
- field_combo.fuse_life_cycle.life_cycle.load_next = load_next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.load_next = load_next_c;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_life_cycle.life_cycle.value <= 2'h0;
- end else if(field_combo.fuse_life_cycle.life_cycle.load_next) begin
- field_storage.fuse_life_cycle.life_cycle.value <= field_combo.fuse_life_cycle.life_cycle.next;
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.next;
end
end
- assign hwif_out.fuse_life_cycle.life_cycle.value = field_storage.fuse_life_cycle.life_cycle.value;
- // Field: soc_ifc_reg.fuse_lms_verify.lms_verify
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_lms_verify.lms_verify.value;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_lms_verify && decoded_req_is_wr && !(hwif_in.fuse_lms_verify.lms_verify.swwel)) begin // SW write
- next_c = (field_storage.fuse_lms_verify.lms_verify.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.next;
load_next_c = '1;
end
- field_combo.fuse_lms_verify.lms_verify.next = next_c;
- field_combo.fuse_lms_verify.lms_verify.load_next = load_next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.load_next = load_next_c;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_lms_verify.lms_verify.value <= 1'h0;
- end else if(field_combo.fuse_lms_verify.lms_verify.load_next) begin
- field_storage.fuse_lms_verify.lms_verify.value <= field_combo.fuse_lms_verify.lms_verify.next;
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.next;
end
end
- assign hwif_out.fuse_lms_verify.lms_verify.value = field_storage.fuse_lms_verify.lms_verify.value;
- // Field: soc_ifc_reg.fuse_lms_revocation.lms_revocation
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL
always_comb begin
- automatic logic [31:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_lms_revocation.lms_revocation.value;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_lms_revocation && decoded_req_is_wr && !(hwif_in.fuse_lms_revocation.lms_revocation.swwel)) begin // SW write
- next_c = (field_storage.fuse_lms_revocation.lms_revocation.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.next;
load_next_c = '1;
end
- field_combo.fuse_lms_revocation.lms_revocation.next = next_c;
- field_combo.fuse_lms_revocation.lms_revocation.load_next = load_next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.load_next = load_next_c;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_lms_revocation.lms_revocation.value <= 32'h0;
- end else if(field_combo.fuse_lms_revocation.lms_revocation.load_next) begin
- field_storage.fuse_lms_revocation.lms_revocation.value <= field_combo.fuse_lms_revocation.lms_revocation.next;
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.next;
end
end
- assign hwif_out.fuse_lms_revocation.lms_revocation.value = field_storage.fuse_lms_revocation.lms_revocation.value;
- // Field: soc_ifc_reg.fuse_soc_stepping_id.soc_stepping_id
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS
always_comb begin
- automatic logic [15:0] next_c;
+ automatic logic [0:0] next_c;
automatic logic load_next_c;
- next_c = field_storage.fuse_soc_stepping_id.soc_stepping_id.value;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value;
load_next_c = '0;
- if(decoded_reg_strb.fuse_soc_stepping_id && decoded_req_is_wr && !(hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel)) begin // SW write
- next_c = (field_storage.fuse_soc_stepping_id.soc_stepping_id.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.next;
load_next_c = '1;
end
- field_combo.fuse_soc_stepping_id.soc_stepping_id.next = next_c;
- field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next = load_next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.load_next = load_next_c;
end
- always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
- if(~hwif_in.cptra_pwrgood) begin
- field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= 16'h0;
- end else if(field_combo.fuse_soc_stepping_id.soc_stepping_id.load_next) begin
- field_storage.fuse_soc_stepping_id.soc_stepping_id.value <= field_combo.fuse_soc_stepping_id.soc_stepping_id.next;
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.next;
end
end
- assign hwif_out.fuse_soc_stepping_id.soc_stepping_id.value = field_storage.fuse_soc_stepping_id.soc_stepping_id.value;
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.next;
+ end
+ end
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value & ~decoded_wr_biten[7:7]) | (decoded_wr_data[7:7] & decoded_wr_biten[7:7]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.next;
+ end
+ end
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value;
+ // Field: soc_ifc_reg.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS
+ always_comb begin
+ automatic logic [0:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && decoded_req_is_wr && hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.swwe) begin // SW write
+ next_c = (field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value & ~decoded_wr_biten[8:8]) | (decoded_wr_data[8:8] & decoded_wr_biten[8:8]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.we) begin // HW Write - we
+ next_c = hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.next = next_c;
+ field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value <= 1'h0;
+ end else if(field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.load_next) begin
+ field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value <= field_combo.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.next;
+ end
+ end
+ assign hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value = field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value;
+ for(genvar i0=0; i0<2; i0++) begin
+ // Field: soc_ifc_reg.SS_SOC_DBG_UNLOCK_LEVEL[].LEVEL
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_SOC_DBG_UNLOCK_LEVEL[i0] && decoded_req_is_wr && !(hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.swwel)) begin // SW write
+ next_c = (field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end else if(hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.we) begin // HW Write - we
+ next_c = hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.next;
+ load_next_c = '1;
+ end
+ field_combo.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.next = next_c;
+ field_combo.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value <= 32'h0;
+ end else if(field_combo.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.load_next) begin
+ field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value <= field_combo.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.next;
+ end
+ end
+ assign hwif_out.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value = field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value;
+ end
+ for(genvar i0=0; i0<4; i0++) begin
+ // Field: soc_ifc_reg.SS_GENERIC_FW_EXEC_CTRL[].go
+ always_comb begin
+ automatic logic [31:0] next_c;
+ automatic logic load_next_c;
+ next_c = field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value;
+ load_next_c = '0;
+ if(decoded_reg_strb.SS_GENERIC_FW_EXEC_CTRL[i0] && decoded_req_is_wr && !(hwif_in.soc_req)) begin // SW write
+ next_c = (field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
+ load_next_c = '1;
+ end
+ field_combo.SS_GENERIC_FW_EXEC_CTRL[i0].go.next = next_c;
+ field_combo.SS_GENERIC_FW_EXEC_CTRL[i0].go.load_next = load_next_c;
+ end
+ always_ff @(posedge clk or negedge hwif_in.cptra_rst_b) begin
+ if(~hwif_in.cptra_rst_b) begin
+ field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value <= 32'h0;
+ end else if(field_combo.SS_GENERIC_FW_EXEC_CTRL[i0].go.load_next) begin
+ field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value <= field_combo.SS_GENERIC_FW_EXEC_CTRL[i0].go.next;
+ end
+ end
+ assign hwif_out.SS_GENERIC_FW_EXEC_CTRL[i0].go.value = field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value;
+ end
for(genvar i0=0; i0<8; i0++) begin
// Field: soc_ifc_reg.internal_obf_key[].key
always_comb begin
@@ -5772,16 +6896,16 @@ module soc_ifc_reg (
logic [31:0] readback_data;
// Assign readback values to a flattened array
- logic [186-1:0][31:0] readback_array;
+ logic [225-1:0][31:0] readback_array;
assign readback_array[0][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value : '0;
assign readback_array[0][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value : '0;
assign readback_array[0][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value : '0;
assign readback_array[0][3:3] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.crypto_err.value : '0;
- assign readback_array[0][31:4] = '0;
+ assign readback_array[0][31:4] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next : '0;
assign readback_array[1][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value : '0;
assign readback_array[1][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value : '0;
assign readback_array[1][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value : '0;
- assign readback_array[1][31:3] = '0;
+ assign readback_array[1][31:3] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_ERROR_NON_FATAL.rsvd.next : '0;
assign readback_array[2][31:0] = (decoded_reg_strb.CPTRA_FW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_FW_ERROR_FATAL.error_code.value : '0;
assign readback_array[3][31:0] = (decoded_reg_strb.CPTRA_FW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_FW_ERROR_NON_FATAL.error_code.value : '0;
assign readback_array[4][31:0] = (decoded_reg_strb.CPTRA_HW_ERROR_ENC && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_ENC.error_code.value : '0;
@@ -5793,7 +6917,7 @@ module soc_ifc_reg (
assign readback_array[15][23:0] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.status.value : '0;
assign readback_array[15][24:24] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.idevid_csr_ready.value : '0;
assign readback_array[15][27:25] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? hwif_in.CPTRA_FLOW_STATUS.boot_fsm_ps.next : '0;
- assign readback_array[15][28:28] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_fw.value : '0;
+ assign readback_array[15][28:28] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_mb_processing.value : '0;
assign readback_array[15][29:29] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.ready_for_runtime.value : '0;
assign readback_array[15][30:30] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? hwif_in.CPTRA_FLOW_STATUS.ready_for_fuses.next : '0;
assign readback_array[15][31:31] = (decoded_reg_strb.CPTRA_FLOW_STATUS && !decoded_req_is_wr) ? field_storage.CPTRA_FLOW_STATUS.mailbox_flow_done.value : '0;
@@ -5842,11 +6966,10 @@ module soc_ifc_reg (
assign readback_array[i0*1 + 54][31:0] = (decoded_reg_strb.CPTRA_FW_REV_ID[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_FW_REV_ID[i0].REV_ID.value : '0;
end
assign readback_array[56][0:0] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.iTRNG_en.next : '0;
- assign readback_array[56][1:1] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.QSPI_en.next : '0;
- assign readback_array[56][2:2] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.I3C_en.next : '0;
- assign readback_array[56][3:3] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.UART_en.next : '0;
+ assign readback_array[56][3:1] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.RSVD_en.next : '0;
assign readback_array[56][4:4] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.LMS_acc_en.next : '0;
- assign readback_array[56][31:5] = '0;
+ assign readback_array[56][5:5] = (decoded_reg_strb.CPTRA_HW_CONFIG && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_CONFIG.ACTIVE_MODE_en.next : '0;
+ assign readback_array[56][31:6] = '0;
assign readback_array[57][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_EN && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_EN.timer1_en.value : '0;
assign readback_array[57][31:1] = '0;
assign readback_array[58][0:0] = (decoded_reg_strb.CPTRA_WDT_TIMER1_CTRL && !decoded_req_is_wr) ? field_storage.CPTRA_WDT_TIMER1_CTRL.timer1_restart.value : '0;
@@ -5877,152 +7000,197 @@ module soc_ifc_reg (
for(genvar i0=0; i0<2; i0++) begin
assign readback_array[i0*1 + 72][31:0] = (decoded_reg_strb.CPTRA_RSVD_REG[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_RSVD_REG[i0].RSVD.value : '0;
end
+ assign readback_array[74][31:0] = (decoded_reg_strb.CPTRA_HW_CAPABILITIES && !decoded_req_is_wr) ? field_storage.CPTRA_HW_CAPABILITIES.cap.value : '0;
+ assign readback_array[75][31:0] = (decoded_reg_strb.CPTRA_FW_CAPABILITIES && !decoded_req_is_wr) ? field_storage.CPTRA_FW_CAPABILITIES.cap.value : '0;
+ assign readback_array[76][0:0] = (decoded_reg_strb.CPTRA_CAP_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_CAP_LOCK.lock.value : '0;
+ assign readback_array[76][31:1] = '0;
for(genvar i0=0; i0<12; i0++) begin
- assign readback_array[i0*1 + 74][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash[i0].hash.value : '0;
+ assign readback_array[i0*1 + 77][31:0] = (decoded_reg_strb.CPTRA_OWNER_PK_HASH[i0] && !decoded_req_is_wr) ? field_storage.CPTRA_OWNER_PK_HASH[i0].hash.value : '0;
end
- assign readback_array[86][3:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash_mask && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash_mask.mask.value : '0;
- assign readback_array[86][31:4] = '0;
+ assign readback_array[89][0:0] = (decoded_reg_strb.CPTRA_OWNER_PK_HASH_LOCK && !decoded_req_is_wr) ? field_storage.CPTRA_OWNER_PK_HASH_LOCK.lock.value : '0;
+ assign readback_array[89][31:1] = '0;
for(genvar i0=0; i0<12; i0++) begin
- assign readback_array[i0*1 + 87][31:0] = (decoded_reg_strb.fuse_owner_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_owner_pk_hash[i0].hash.value : '0;
+ assign readback_array[i0*1 + 90][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash[i0].hash.value : '0;
+ end
+ for(genvar i0=0; i0<8; i0++) begin
+ assign readback_array[i0*1 + 102][31:0] = (decoded_reg_strb.fuse_key_manifest_pk_hash_mask[i0] && !decoded_req_is_wr) ? field_storage.fuse_key_manifest_pk_hash_mask[i0].mask.value : '0;
end
- assign readback_array[99][31:0] = (decoded_reg_strb.fuse_fmc_key_manifest_svn && !decoded_req_is_wr) ? field_storage.fuse_fmc_key_manifest_svn.svn.value : '0;
+ assign readback_array[110][31:0] = (decoded_reg_strb.fuse_fmc_key_manifest_svn && !decoded_req_is_wr) ? field_storage.fuse_fmc_key_manifest_svn.svn.value : '0;
for(genvar i0=0; i0<4; i0++) begin
- assign readback_array[i0*1 + 100][31:0] = (decoded_reg_strb.fuse_runtime_svn[i0] && !decoded_req_is_wr) ? field_storage.fuse_runtime_svn[i0].svn.value : '0;
+ assign readback_array[i0*1 + 111][31:0] = (decoded_reg_strb.fuse_runtime_svn[i0] && !decoded_req_is_wr) ? field_storage.fuse_runtime_svn[i0].svn.value : '0;
end
- assign readback_array[104][0:0] = (decoded_reg_strb.fuse_anti_rollback_disable && !decoded_req_is_wr) ? field_storage.fuse_anti_rollback_disable.dis.value : '0;
- assign readback_array[104][31:1] = '0;
+ assign readback_array[115][0:0] = (decoded_reg_strb.fuse_anti_rollback_disable && !decoded_req_is_wr) ? field_storage.fuse_anti_rollback_disable.dis.value : '0;
+ assign readback_array[115][31:1] = '0;
for(genvar i0=0; i0<24; i0++) begin
- assign readback_array[i0*1 + 105][31:0] = (decoded_reg_strb.fuse_idevid_cert_attr[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_cert_attr[i0].cert.value : '0;
+ assign readback_array[i0*1 + 116][31:0] = (decoded_reg_strb.fuse_idevid_cert_attr[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_cert_attr[i0].cert.value : '0;
+ end
+ for(genvar i0=0; i0<4; i0++) begin
+ assign readback_array[i0*1 + 140][31:0] = (decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value : '0;
+ end
+ assign readback_array[144][31:0] = (decoded_reg_strb.fuse_lms_revocation && !decoded_req_is_wr) ? field_storage.fuse_lms_revocation.lms_revocation.value : '0;
+ assign readback_array[145][3:0] = (decoded_reg_strb.fuse_mldsa_revocation && !decoded_req_is_wr) ? field_storage.fuse_mldsa_revocation.mldsa_revocation.value : '0;
+ assign readback_array[145][31:4] = '0;
+ assign readback_array[146][15:0] = (decoded_reg_strb.fuse_soc_stepping_id && !decoded_req_is_wr) ? field_storage.fuse_soc_stepping_id.soc_stepping_id.value : '0;
+ assign readback_array[146][31:16] = '0;
+ for(genvar i0=0; i0<4; i0++) begin
+ assign readback_array[i0*1 + 147][31:0] = (decoded_reg_strb.fuse_manuf_dbg_unlock_token[i0] && !decoded_req_is_wr) ? field_storage.fuse_manuf_dbg_unlock_token[i0].token.value : '0;
+ end
+ assign readback_array[151][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_L.addr_l.value : '0;
+ assign readback_array[152][31:0] = (decoded_reg_strb.SS_CALIPTRA_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_CALIPTRA_BASE_ADDR_H.addr_h.value : '0;
+ assign readback_array[153][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_L.addr_l.value : '0;
+ assign readback_array[154][31:0] = (decoded_reg_strb.SS_MCI_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_MCI_BASE_ADDR_H.addr_h.value : '0;
+ assign readback_array[155][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value : '0;
+ assign readback_array[156][31:0] = (decoded_reg_strb.SS_RECOVERY_IFC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value : '0;
+ assign readback_array[157][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_L.addr_l.value : '0;
+ assign readback_array[158][31:0] = (decoded_reg_strb.SS_OTP_FC_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_OTP_FC_BASE_ADDR_H.addr_h.value : '0;
+ assign readback_array[159][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_L && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_L.addr_l.value : '0;
+ assign readback_array[160][31:0] = (decoded_reg_strb.SS_UDS_SEED_BASE_ADDR_H && !decoded_req_is_wr) ? field_storage.SS_UDS_SEED_BASE_ADDR_H.addr_h.value : '0;
+ assign readback_array[161][31:0] = (decoded_reg_strb.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET && !decoded_req_is_wr) ? field_storage.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.value : '0;
+ assign readback_array[162][31:0] = (decoded_reg_strb.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES && !decoded_req_is_wr) ? field_storage.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.value : '0;
+ assign readback_array[163][0:0] = (decoded_reg_strb.SS_DEBUG_INTENT && !decoded_req_is_wr) ? field_storage.SS_DEBUG_INTENT.debug_intent.value : '0;
+ assign readback_array[163][31:1] = '0;
+ for(genvar i0=0; i0<4; i0++) begin
+ assign readback_array[i0*1 + 164][31:0] = (decoded_reg_strb.SS_STRAP_GENERIC[i0] && !decoded_req_is_wr) ? field_storage.SS_STRAP_GENERIC[i0].data.value : '0;
+ end
+ assign readback_array[168][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value : '0;
+ assign readback_array[168][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value : '0;
+ assign readback_array[168][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value : '0;
+ assign readback_array[168][31:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_REQ && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next : '0;
+ assign readback_array[169][0:0] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value : '0;
+ assign readback_array[169][1:1] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.value : '0;
+ assign readback_array[169][2:2] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.value : '0;
+ assign readback_array[169][3:3] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value : '0;
+ assign readback_array[169][4:4] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.value : '0;
+ assign readback_array[169][5:5] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.value : '0;
+ assign readback_array[169][6:6] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.value : '0;
+ assign readback_array[169][7:7] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.value : '0;
+ assign readback_array[169][8:8] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? field_storage.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.value : '0;
+ assign readback_array[169][31:9] = (decoded_reg_strb.SS_DBG_MANUF_SERVICE_REG_RSP && !decoded_req_is_wr) ? hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next : '0;
+ for(genvar i0=0; i0<2; i0++) begin
+ assign readback_array[i0*1 + 170][31:0] = (decoded_reg_strb.SS_SOC_DBG_UNLOCK_LEVEL[i0] && !decoded_req_is_wr) ? field_storage.SS_SOC_DBG_UNLOCK_LEVEL[i0].LEVEL.value : '0;
end
for(genvar i0=0; i0<4; i0++) begin
- assign readback_array[i0*1 + 129][31:0] = (decoded_reg_strb.fuse_idevid_manuf_hsm_id[i0] && !decoded_req_is_wr) ? field_storage.fuse_idevid_manuf_hsm_id[i0].hsm_id.value : '0;
- end
- assign readback_array[133][1:0] = (decoded_reg_strb.fuse_life_cycle && !decoded_req_is_wr) ? field_storage.fuse_life_cycle.life_cycle.value : '0;
- assign readback_array[133][31:2] = '0;
- assign readback_array[134][0:0] = (decoded_reg_strb.fuse_lms_verify && !decoded_req_is_wr) ? field_storage.fuse_lms_verify.lms_verify.value : '0;
- assign readback_array[134][31:1] = '0;
- assign readback_array[135][31:0] = (decoded_reg_strb.fuse_lms_revocation && !decoded_req_is_wr) ? field_storage.fuse_lms_revocation.lms_revocation.value : '0;
- assign readback_array[136][15:0] = (decoded_reg_strb.fuse_soc_stepping_id && !decoded_req_is_wr) ? field_storage.fuse_soc_stepping_id.soc_stepping_id.value : '0;
- assign readback_array[136][31:16] = '0;
- assign readback_array[137][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0;
- assign readback_array[137][31:1] = '0;
- assign readback_array[138][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0;
- assign readback_array[138][31:1] = '0;
- assign readback_array[139][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0;
- assign readback_array[139][31:8] = '0;
- assign readback_array[140][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0;
- assign readback_array[141][0:0] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value : '0;
- assign readback_array[141][1:1] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value : '0;
- assign readback_array[141][2:2] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value : '0;
- assign readback_array[141][3:3] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? 1'h0 : '0;
- assign readback_array[141][31:4] = '0;
- assign readback_array[142][0:0] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value : '0;
- assign readback_array[142][1:1] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value : '0;
- assign readback_array[142][2:2] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value : '0;
- assign readback_array[142][31:3] = '0;
- assign readback_array[143][31:0] = (decoded_reg_strb.internal_fw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_fatal_mask.mask.value : '0;
- assign readback_array[144][31:0] = (decoded_reg_strb.internal_fw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_non_fatal_mask.mask.value : '0;
- assign readback_array[145][31:0] = (decoded_reg_strb.internal_rv_mtime_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_l.count_l.value : '0;
- assign readback_array[146][31:0] = (decoded_reg_strb.internal_rv_mtime_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_h.count_h.value : '0;
- assign readback_array[147][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_l.compare_l.value : '0;
- assign readback_array[148][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_h.compare_h.value : '0;
- assign readback_array[149][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0;
- assign readback_array[149][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0;
- assign readback_array[149][31:2] = '0;
- assign readback_array[150][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0;
- assign readback_array[150][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0;
- assign readback_array[150][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0;
- assign readback_array[150][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0;
- assign readback_array[150][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0;
- assign readback_array[150][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0;
- assign readback_array[150][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0;
- assign readback_array[150][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0;
- assign readback_array[150][31:8] = '0;
- assign readback_array[151][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0;
- assign readback_array[151][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0;
- assign readback_array[151][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0;
- assign readback_array[151][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value : '0;
- assign readback_array[151][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0;
- assign readback_array[151][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value : '0;
- assign readback_array[151][31:6] = '0;
- assign readback_array[152][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0;
- assign readback_array[152][31:1] = '0;
- assign readback_array[153][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0;
- assign readback_array[153][31:1] = '0;
- assign readback_array[154][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0;
- assign readback_array[154][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0;
- assign readback_array[154][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0;
- assign readback_array[154][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0;
- assign readback_array[154][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0;
- assign readback_array[154][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0;
- assign readback_array[154][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0;
- assign readback_array[154][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0;
- assign readback_array[154][31:8] = '0;
- assign readback_array[155][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0;
- assign readback_array[155][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0;
- assign readback_array[155][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0;
- assign readback_array[155][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value : '0;
- assign readback_array[155][4:4] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0;
- assign readback_array[155][5:5] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value : '0;
- assign readback_array[155][31:6] = '0;
- assign readback_array[156][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0;
- assign readback_array[156][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0;
- assign readback_array[156][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0;
- assign readback_array[156][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0;
- assign readback_array[156][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0;
- assign readback_array[156][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0;
- assign readback_array[156][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0;
- assign readback_array[156][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0;
- assign readback_array[156][31:8] = '0;
- assign readback_array[157][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0;
- assign readback_array[157][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0;
- assign readback_array[157][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0;
- assign readback_array[157][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value : '0;
- assign readback_array[157][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0;
- assign readback_array[157][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value : '0;
- assign readback_array[157][31:6] = '0;
- assign readback_array[158][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0;
- assign readback_array[159][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0;
- assign readback_array[160][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0;
- assign readback_array[161][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0;
- assign readback_array[162][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0;
- assign readback_array[163][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0;
- assign readback_array[164][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0;
- assign readback_array[165][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0;
- assign readback_array[166][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0;
- assign readback_array[167][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0;
- assign readback_array[168][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0;
- assign readback_array[169][31:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value : '0;
- assign readback_array[170][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0;
- assign readback_array[171][31:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value : '0;
- assign readback_array[172][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0;
- assign readback_array[172][31:1] = '0;
- assign readback_array[173][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0;
- assign readback_array[173][31:1] = '0;
- assign readback_array[174][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0;
- assign readback_array[174][31:1] = '0;
- assign readback_array[175][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0;
- assign readback_array[175][31:1] = '0;
- assign readback_array[176][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[i0*1 + 172][31:0] = (decoded_reg_strb.SS_GENERIC_FW_EXEC_CTRL[i0] && !decoded_req_is_wr) ? field_storage.SS_GENERIC_FW_EXEC_CTRL[i0].go.value : '0;
+ end
+ assign readback_array[176][0:0] = (decoded_reg_strb.internal_iccm_lock && !decoded_req_is_wr) ? field_storage.internal_iccm_lock.lock.value : '0;
assign readback_array[176][31:1] = '0;
- assign readback_array[177][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[177][0:0] = (decoded_reg_strb.internal_fw_update_reset && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset.core_rst.value : '0;
assign readback_array[177][31:1] = '0;
- assign readback_array[178][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0;
- assign readback_array[178][31:1] = '0;
- assign readback_array[179][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0;
- assign readback_array[179][31:1] = '0;
- assign readback_array[180][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0;
- assign readback_array[180][31:1] = '0;
- assign readback_array[181][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0;
- assign readback_array[181][31:1] = '0;
- assign readback_array[182][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0;
- assign readback_array[182][31:1] = '0;
- assign readback_array[183][0:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value : '0;
- assign readback_array[183][31:1] = '0;
- assign readback_array[184][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0;
- assign readback_array[184][31:1] = '0;
- assign readback_array[185][0:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value : '0;
- assign readback_array[185][31:1] = '0;
+ assign readback_array[178][7:0] = (decoded_reg_strb.internal_fw_update_reset_wait_cycles && !decoded_req_is_wr) ? field_storage.internal_fw_update_reset_wait_cycles.wait_cycles.value : '0;
+ assign readback_array[178][31:8] = '0;
+ assign readback_array[179][31:0] = (decoded_reg_strb.internal_nmi_vector && !decoded_req_is_wr) ? field_storage.internal_nmi_vector.vec.value : '0;
+ assign readback_array[180][0:0] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value : '0;
+ assign readback_array[180][1:1] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value : '0;
+ assign readback_array[180][2:2] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_fatal_mask.mask_nmi_pin.value : '0;
+ assign readback_array[180][3:3] = (decoded_reg_strb.internal_hw_error_fatal_mask && !decoded_req_is_wr) ? 1'h0 : '0;
+ assign readback_array[180][31:4] = '0;
+ assign readback_array[181][0:0] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value : '0;
+ assign readback_array[181][1:1] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo.value : '0;
+ assign readback_array[181][2:2] = (decoded_reg_strb.internal_hw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_hw_error_non_fatal_mask.mask_mbox_ecc_unc.value : '0;
+ assign readback_array[181][31:3] = '0;
+ assign readback_array[182][31:0] = (decoded_reg_strb.internal_fw_error_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_fatal_mask.mask.value : '0;
+ assign readback_array[183][31:0] = (decoded_reg_strb.internal_fw_error_non_fatal_mask && !decoded_req_is_wr) ? field_storage.internal_fw_error_non_fatal_mask.mask.value : '0;
+ assign readback_array[184][31:0] = (decoded_reg_strb.internal_rv_mtime_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_l.count_l.value : '0;
+ assign readback_array[185][31:0] = (decoded_reg_strb.internal_rv_mtime_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtime_h.count_h.value : '0;
+ assign readback_array[186][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_l && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_l.compare_l.value : '0;
+ assign readback_array[187][31:0] = (decoded_reg_strb.internal_rv_mtimecmp_h && !decoded_req_is_wr) ? field_storage.internal_rv_mtimecmp_h.compare_h.value : '0;
+ assign readback_array[188][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0;
+ assign readback_array[188][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0;
+ assign readback_array[188][31:2] = '0;
+ assign readback_array[189][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0;
+ assign readback_array[189][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_inv_dev_en.value : '0;
+ assign readback_array[189][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_cmd_fail_en.value : '0;
+ assign readback_array[189][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_bad_fuse_en.value : '0;
+ assign readback_array[189][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_iccm_blocked_en.value : '0;
+ assign readback_array[189][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_mbox_ecc_unc_en.value : '0;
+ assign readback_array[189][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer1_timeout_en.value : '0;
+ assign readback_array[189][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_wdt_timer2_timeout_en.value : '0;
+ assign readback_array[189][31:8] = '0;
+ assign readback_array[190][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_avail_en.value : '0;
+ assign readback_array[190][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_mbox_ecc_cor_en.value : '0;
+ assign readback_array[190][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_debug_locked_en.value : '0;
+ assign readback_array[190][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_scan_mode_en.value : '0;
+ assign readback_array[190][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_soc_req_lock_en.value : '0;
+ assign readback_array[190][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_gen_in_toggle_en.value : '0;
+ assign readback_array[190][31:6] = '0;
+ assign readback_array[191][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0;
+ assign readback_array[191][31:1] = '0;
+ assign readback_array[192][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0;
+ assign readback_array[192][31:1] = '0;
+ assign readback_array[193][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0;
+ assign readback_array[193][1:1] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_inv_dev_sts.value : '0;
+ assign readback_array[193][2:2] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_cmd_fail_sts.value : '0;
+ assign readback_array[193][3:3] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_bad_fuse_sts.value : '0;
+ assign readback_array[193][4:4] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_iccm_blocked_sts.value : '0;
+ assign readback_array[193][5:5] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_mbox_ecc_unc_sts.value : '0;
+ assign readback_array[193][6:6] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer1_timeout_sts.value : '0;
+ assign readback_array[193][7:7] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_wdt_timer2_timeout_sts.value : '0;
+ assign readback_array[193][31:8] = '0;
+ assign readback_array[194][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_avail_sts.value : '0;
+ assign readback_array[194][1:1] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_mbox_ecc_cor_sts.value : '0;
+ assign readback_array[194][2:2] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_debug_locked_sts.value : '0;
+ assign readback_array[194][3:3] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_scan_mode_sts.value : '0;
+ assign readback_array[194][4:4] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_soc_req_lock_sts.value : '0;
+ assign readback_array[194][5:5] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_gen_in_toggle_sts.value : '0;
+ assign readback_array[194][31:6] = '0;
+ assign readback_array[195][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0;
+ assign readback_array[195][1:1] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_inv_dev_trig.value : '0;
+ assign readback_array[195][2:2] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_cmd_fail_trig.value : '0;
+ assign readback_array[195][3:3] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_bad_fuse_trig.value : '0;
+ assign readback_array[195][4:4] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_iccm_blocked_trig.value : '0;
+ assign readback_array[195][5:5] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_mbox_ecc_unc_trig.value : '0;
+ assign readback_array[195][6:6] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer1_timeout_trig.value : '0;
+ assign readback_array[195][7:7] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_wdt_timer2_timeout_trig.value : '0;
+ assign readback_array[195][31:8] = '0;
+ assign readback_array[196][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_avail_trig.value : '0;
+ assign readback_array[196][1:1] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_mbox_ecc_cor_trig.value : '0;
+ assign readback_array[196][2:2] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_debug_locked_trig.value : '0;
+ assign readback_array[196][3:3] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_scan_mode_trig.value : '0;
+ assign readback_array[196][4:4] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_soc_req_lock_trig.value : '0;
+ assign readback_array[196][5:5] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_gen_in_toggle_trig.value : '0;
+ assign readback_array[196][31:6] = '0;
+ assign readback_array[197][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0;
+ assign readback_array[198][31:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_r.cnt.value : '0;
+ assign readback_array[199][31:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_r.cnt.value : '0;
+ assign readback_array[200][31:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_r.cnt.value : '0;
+ assign readback_array[201][31:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_r.cnt.value : '0;
+ assign readback_array[202][31:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_r.cnt.value : '0;
+ assign readback_array[203][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_r.cnt.value : '0;
+ assign readback_array[204][31:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_r.cnt.value : '0;
+ assign readback_array[205][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_r.cnt.value : '0;
+ assign readback_array[206][31:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_r.cnt.value : '0;
+ assign readback_array[207][31:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_r.cnt.value : '0;
+ assign readback_array[208][31:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_r.cnt.value : '0;
+ assign readback_array[209][31:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_r.cnt.value : '0;
+ assign readback_array[210][31:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_r.cnt.value : '0;
+ assign readback_array[211][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[211][31:1] = '0;
+ assign readback_array[212][0:0] = (decoded_reg_strb.intr_block_rf.error_inv_dev_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_inv_dev_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[212][31:1] = '0;
+ assign readback_array[213][0:0] = (decoded_reg_strb.intr_block_rf.error_cmd_fail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_cmd_fail_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[213][31:1] = '0;
+ assign readback_array[214][0:0] = (decoded_reg_strb.intr_block_rf.error_bad_fuse_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_bad_fuse_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[214][31:1] = '0;
+ assign readback_array[215][0:0] = (decoded_reg_strb.intr_block_rf.error_iccm_blocked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_iccm_blocked_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[215][31:1] = '0;
+ assign readback_array[216][0:0] = (decoded_reg_strb.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_mbox_ecc_unc_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[216][31:1] = '0;
+ assign readback_array[217][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer1_timeout_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[217][31:1] = '0;
+ assign readback_array[218][0:0] = (decoded_reg_strb.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_wdt_timer2_timeout_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[218][31:1] = '0;
+ assign readback_array[219][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_avail_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_avail_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[219][31:1] = '0;
+ assign readback_array[220][0:0] = (decoded_reg_strb.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_mbox_ecc_cor_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[220][31:1] = '0;
+ assign readback_array[221][0:0] = (decoded_reg_strb.intr_block_rf.notif_debug_locked_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_debug_locked_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[221][31:1] = '0;
+ assign readback_array[222][0:0] = (decoded_reg_strb.intr_block_rf.notif_scan_mode_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_scan_mode_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[222][31:1] = '0;
+ assign readback_array[223][0:0] = (decoded_reg_strb.intr_block_rf.notif_soc_req_lock_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_soc_req_lock_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[223][31:1] = '0;
+ assign readback_array[224][0:0] = (decoded_reg_strb.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_gen_in_toggle_intr_count_incr_r.pulse.value : '0;
+ assign readback_array[224][31:1] = '0;
// Reduce the array
always_comb begin
@@ -6030,7 +7198,7 @@ module soc_ifc_reg (
readback_done = decoded_req & ~decoded_req_is_wr;
readback_err = '0;
readback_data_var = '0;
- for(int i=0; i<186; i++) readback_data_var |= readback_array[i];
+ for(int i=0; i<225; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh
index b65dbeacc..b3b94bc89 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh
+++ b/src/soc_ifc/rtl/soc_ifc_reg_covergroups.svh
@@ -31,13 +31,15 @@
input bit [1-1:0] iccm_ecc_unc,
input bit [1-1:0] dccm_ecc_unc,
input bit [1-1:0] nmi_pin,
- input bit [1-1:0] crypto_err
+ input bit [1-1:0] crypto_err,
+ input bit [28-1:0] rsvd
);
option.per_instance = 1;
iccm_ecc_unc_cp : coverpoint iccm_ecc_unc;
dccm_ecc_unc_cp : coverpoint dccm_ecc_unc;
nmi_pin_cp : coverpoint nmi_pin;
crypto_err_cp : coverpoint crypto_err;
+ rsvd_cp : coverpoint rsvd;
endgroup
@@ -56,12 +58,14 @@
covergroup soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_fld_cg with function sample(
input bit [1-1:0] mbox_prot_no_lock,
input bit [1-1:0] mbox_prot_ooo,
- input bit [1-1:0] mbox_ecc_unc
+ input bit [1-1:0] mbox_ecc_unc,
+ input bit [29-1:0] rsvd
);
option.per_instance = 1;
mbox_prot_no_lock_cp : coverpoint mbox_prot_no_lock;
mbox_prot_ooo_cp : coverpoint mbox_prot_ooo;
mbox_ecc_unc_cp : coverpoint mbox_ecc_unc;
+ rsvd_cp : coverpoint rsvd;
endgroup
@@ -201,7 +205,7 @@
input bit [24-1:0] status,
input bit [1-1:0] idevid_csr_ready,
input bit [3-1:0] boot_fsm_ps,
- input bit [1-1:0] ready_for_fw,
+ input bit [1-1:0] ready_for_mb_processing,
input bit [1-1:0] ready_for_runtime,
input bit [1-1:0] ready_for_fuses,
input bit [1-1:0] mailbox_flow_done
@@ -210,7 +214,7 @@
status_cp : coverpoint status;
idevid_csr_ready_cp : coverpoint idevid_csr_ready;
boot_fsm_ps_cp : coverpoint boot_fsm_ps;
- ready_for_fw_cp : coverpoint ready_for_fw;
+ ready_for_mb_processing_cp : coverpoint ready_for_mb_processing;
ready_for_runtime_cp : coverpoint ready_for_runtime;
ready_for_fuses_cp : coverpoint ready_for_fuses;
mailbox_flow_done_cp : coverpoint mailbox_flow_done;
@@ -633,17 +637,15 @@
endgroup
covergroup soc_ifc_reg__CPTRA_HW_CONFIG_fld_cg with function sample(
input bit [1-1:0] iTRNG_en,
- input bit [1-1:0] QSPI_en,
- input bit [1-1:0] I3C_en,
- input bit [1-1:0] UART_en,
- input bit [1-1:0] LMS_acc_en
+ input bit [3-1:0] RSVD_en,
+ input bit [1-1:0] LMS_acc_en,
+ input bit [1-1:0] ACTIVE_MODE_en
);
option.per_instance = 1;
iTRNG_en_cp : coverpoint iTRNG_en;
- QSPI_en_cp : coverpoint QSPI_en;
- I3C_en_cp : coverpoint I3C_en;
- UART_en_cp : coverpoint UART_en;
+ RSVD_en_cp : coverpoint RSVD_en;
LMS_acc_en_cp : coverpoint LMS_acc_en;
+ ACTIVE_MODE_en_cp : coverpoint ACTIVE_MODE_en;
endgroup
@@ -919,6 +921,106 @@
endgroup
+ /*----------------------- SOC_IFC_REG__CPTRA_HW_CAPABILITIES COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__CPTRA_HW_CAPABILITIES_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__CPTRA_HW_CAPABILITIES_fld_cg with function sample(
+ input bit [32-1:0] cap
+ );
+ option.per_instance = 1;
+ cap_cp : coverpoint cap;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__CPTRA_FW_CAPABILITIES COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__CPTRA_FW_CAPABILITIES_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__CPTRA_FW_CAPABILITIES_fld_cg with function sample(
+ input bit [32-1:0] cap
+ );
+ option.per_instance = 1;
+ cap_cp : coverpoint cap;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__CPTRA_CAP_LOCK COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__CPTRA_CAP_LOCK_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__CPTRA_CAP_LOCK_fld_cg with function sample(
+ input bit [1-1:0] lock
+ );
+ option.per_instance = 1;
+ lock_cp : coverpoint lock;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_fld_cg with function sample(
+ input bit [32-1:0] hash
+ );
+ option.per_instance = 1;
+ hash_cp : coverpoint hash;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH_LOCK COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_fld_cg with function sample(
+ input bit [1-1:0] lock
+ );
+ option.per_instance = 1;
+ lock_cp : coverpoint lock;
+
+ endgroup
+
/*----------------------- SOC_IFC_REG__FUSE_UDS_SEED COVERGROUPS -----------------------*/
covergroup soc_ifc_reg__fuse_uds_seed_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
@@ -1010,36 +1112,10 @@
endgroup
covergroup soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg with function sample(
- input bit [4-1:0] mask
+ input bit [32-1:0] mask
);
option.per_instance = 1;
mask_cp : coverpoint mask {
- bins zero_val = {4'h0};
- bins rand_val[4] = {[1:4'hE]};
- bins ones_val = {{4{1'b1}}};
- wildcard bins set = (0 => 4'h?);
- wildcard bins clr = (4'h? => 0);
- }
-
- endgroup
-
- /*----------------------- SOC_IFC_REG__FUSE_OWNER_PK_HASH COVERGROUPS -----------------------*/
- covergroup soc_ifc_reg__fuse_owner_pk_hash_bit_cg with function sample(input bit reg_bit);
- option.per_instance = 1;
- reg_bit_cp : coverpoint reg_bit {
- bins value[2] = {0,1};
- }
- reg_bit_edge_cp : coverpoint reg_bit {
- bins rise = (0 => 1);
- bins fall = (1 => 0);
- }
-
- endgroup
- covergroup soc_ifc_reg__fuse_owner_pk_hash_fld_cg with function sample(
- input bit [32-1:0] hash
- );
- option.per_instance = 1;
- hash_cp : coverpoint hash {
bins zero_val = {32'h0};
bins rand_val[64] = {[1:32'hFFFF_FFFE]};
bins ones_val = {{32{1'b1}}};
@@ -1173,8 +1249,8 @@
endgroup
- /*----------------------- SOC_IFC_REG__FUSE_LIFE_CYCLE COVERGROUPS -----------------------*/
- covergroup soc_ifc_reg__fuse_life_cycle_bit_cg with function sample(input bit reg_bit);
+ /*----------------------- SOC_IFC_REG__FUSE_LMS_REVOCATION COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__fuse_lms_revocation_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
@@ -1185,16 +1261,16 @@
}
endgroup
- covergroup soc_ifc_reg__fuse_life_cycle_fld_cg with function sample(
- input bit [2-1:0] life_cycle
+ covergroup soc_ifc_reg__fuse_lms_revocation_fld_cg with function sample(
+ input bit [32-1:0] lms_revocation
);
option.per_instance = 1;
- life_cycle_cp : coverpoint life_cycle;
+ lms_revocation_cp : coverpoint lms_revocation;
endgroup
- /*----------------------- SOC_IFC_REG__FUSE_LMS_VERIFY COVERGROUPS -----------------------*/
- covergroup soc_ifc_reg__fuse_lms_verify_bit_cg with function sample(input bit reg_bit);
+ /*----------------------- SOC_IFC_REG__FUSE_MLDSA_REVOCATION COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__fuse_mldsa_revocation_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
@@ -1205,16 +1281,16 @@
}
endgroup
- covergroup soc_ifc_reg__fuse_lms_verify_fld_cg with function sample(
- input bit [1-1:0] lms_verify
+ covergroup soc_ifc_reg__fuse_mldsa_revocation_fld_cg with function sample(
+ input bit [4-1:0] mldsa_revocation
);
option.per_instance = 1;
- lms_verify_cp : coverpoint lms_verify;
+ mldsa_revocation_cp : coverpoint mldsa_revocation;
endgroup
- /*----------------------- SOC_IFC_REG__FUSE_LMS_REVOCATION COVERGROUPS -----------------------*/
- covergroup soc_ifc_reg__fuse_lms_revocation_bit_cg with function sample(input bit reg_bit);
+ /*----------------------- SOC_IFC_REG__FUSE_SOC_STEPPING_ID COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__fuse_soc_stepping_id_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
@@ -1225,16 +1301,16 @@
}
endgroup
- covergroup soc_ifc_reg__fuse_lms_revocation_fld_cg with function sample(
- input bit [32-1:0] lms_revocation
+ covergroup soc_ifc_reg__fuse_soc_stepping_id_fld_cg with function sample(
+ input bit [16-1:0] soc_stepping_id
);
option.per_instance = 1;
- lms_revocation_cp : coverpoint lms_revocation;
+ soc_stepping_id_cp : coverpoint soc_stepping_id;
endgroup
- /*----------------------- SOC_IFC_REG__FUSE_SOC_STEPPING_ID COVERGROUPS -----------------------*/
- covergroup soc_ifc_reg__fuse_soc_stepping_id_bit_cg with function sample(input bit reg_bit);
+ /*----------------------- SOC_IFC_REG__FUSE_MANUF_DBG_UNLOCK_TOKEN COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__fuse_manuf_dbg_unlock_token_bit_cg with function sample(input bit reg_bit);
option.per_instance = 1;
reg_bit_cp : coverpoint reg_bit {
bins value[2] = {0,1};
@@ -1245,11 +1321,395 @@
}
endgroup
- covergroup soc_ifc_reg__fuse_soc_stepping_id_fld_cg with function sample(
- input bit [16-1:0] soc_stepping_id
+ covergroup soc_ifc_reg__fuse_manuf_dbg_unlock_token_fld_cg with function sample(
+ input bit [32-1:0] token
);
option.per_instance = 1;
- soc_stepping_id_cp : coverpoint soc_stepping_id;
+ token_cp : coverpoint token;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_CALIPTRA_BASE_ADDR_L COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L_fld_cg with function sample(
+ input bit [32-1:0] addr_l
+ );
+ option.per_instance = 1;
+ addr_l_cp : coverpoint addr_l;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_CALIPTRA_BASE_ADDR_H COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H_fld_cg with function sample(
+ input bit [32-1:0] addr_h
+ );
+ option.per_instance = 1;
+ addr_h_cp : coverpoint addr_h;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_MCI_BASE_ADDR_L COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_MCI_BASE_ADDR_L_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_MCI_BASE_ADDR_L_fld_cg with function sample(
+ input bit [32-1:0] addr_l
+ );
+ option.per_instance = 1;
+ addr_l_cp : coverpoint addr_l;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_MCI_BASE_ADDR_H COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_MCI_BASE_ADDR_H_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_MCI_BASE_ADDR_H_fld_cg with function sample(
+ input bit [32-1:0] addr_h
+ );
+ option.per_instance = 1;
+ addr_h_cp : coverpoint addr_h;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_RECOVERY_IFC_BASE_ADDR_L COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L_fld_cg with function sample(
+ input bit [32-1:0] addr_l
+ );
+ option.per_instance = 1;
+ addr_l_cp : coverpoint addr_l;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_RECOVERY_IFC_BASE_ADDR_H COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H_fld_cg with function sample(
+ input bit [32-1:0] addr_h
+ );
+ option.per_instance = 1;
+ addr_h_cp : coverpoint addr_h;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_OTP_FC_BASE_ADDR_L COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L_fld_cg with function sample(
+ input bit [32-1:0] addr_l
+ );
+ option.per_instance = 1;
+ addr_l_cp : coverpoint addr_l;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_OTP_FC_BASE_ADDR_H COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H_fld_cg with function sample(
+ input bit [32-1:0] addr_h
+ );
+ option.per_instance = 1;
+ addr_h_cp : coverpoint addr_h;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_UDS_SEED_BASE_ADDR_L COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L_fld_cg with function sample(
+ input bit [32-1:0] addr_l
+ );
+ option.per_instance = 1;
+ addr_l_cp : coverpoint addr_l;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_UDS_SEED_BASE_ADDR_H COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H_fld_cg with function sample(
+ input bit [32-1:0] addr_h
+ );
+ option.per_instance = 1;
+ addr_h_cp : coverpoint addr_h;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET_fld_cg with function sample(
+ input bit [32-1:0] offset
+ );
+ option.per_instance = 1;
+ offset_cp : coverpoint offset;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES_fld_cg with function sample(
+ input bit [32-1:0] num
+ );
+ option.per_instance = 1;
+ num_cp : coverpoint num;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_DEBUG_INTENT COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_DEBUG_INTENT_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_DEBUG_INTENT_fld_cg with function sample(
+ input bit [1-1:0] debug_intent
+ );
+ option.per_instance = 1;
+ debug_intent_cp : coverpoint debug_intent;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_STRAP_GENERIC COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_STRAP_GENERIC_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_STRAP_GENERIC_fld_cg with function sample(
+ input bit [32-1:0] data
+ );
+ option.per_instance = 1;
+ data_cp : coverpoint data;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_DBG_MANUF_SERVICE_REG_REQ COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ_fld_cg with function sample(
+ input bit [1-1:0] MANUF_DBG_UNLOCK_REQ,
+ input bit [1-1:0] PROD_DBG_UNLOCK_REQ,
+ input bit [1-1:0] UDS_PROGRAM_REQ,
+ input bit [29-1:0] RSVD
+ );
+ option.per_instance = 1;
+ MANUF_DBG_UNLOCK_REQ_cp : coverpoint MANUF_DBG_UNLOCK_REQ;
+ PROD_DBG_UNLOCK_REQ_cp : coverpoint PROD_DBG_UNLOCK_REQ;
+ UDS_PROGRAM_REQ_cp : coverpoint UDS_PROGRAM_REQ;
+ RSVD_cp : coverpoint RSVD;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_DBG_MANUF_SERVICE_REG_RSP COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_fld_cg with function sample(
+ input bit [1-1:0] MANUF_DBG_UNLOCK_SUCCESS,
+ input bit [1-1:0] MANUF_DBG_UNLOCK_FAIL,
+ input bit [1-1:0] MANUF_DBG_UNLOCK_IN_PROGRESS,
+ input bit [1-1:0] PROD_DBG_UNLOCK_SUCCESS,
+ input bit [1-1:0] PROD_DBG_UNLOCK_FAIL,
+ input bit [1-1:0] PROD_DBG_UNLOCK_IN_PROGRESS,
+ input bit [1-1:0] UDS_PROGRAM_SUCCESS,
+ input bit [1-1:0] UDS_PROGRAM_FAIL,
+ input bit [1-1:0] UDS_PROGRAM_IN_PROGRESS,
+ input bit [23-1:0] RSVD
+ );
+ option.per_instance = 1;
+ MANUF_DBG_UNLOCK_SUCCESS_cp : coverpoint MANUF_DBG_UNLOCK_SUCCESS;
+ MANUF_DBG_UNLOCK_FAIL_cp : coverpoint MANUF_DBG_UNLOCK_FAIL;
+ MANUF_DBG_UNLOCK_IN_PROGRESS_cp : coverpoint MANUF_DBG_UNLOCK_IN_PROGRESS;
+ PROD_DBG_UNLOCK_SUCCESS_cp : coverpoint PROD_DBG_UNLOCK_SUCCESS;
+ PROD_DBG_UNLOCK_FAIL_cp : coverpoint PROD_DBG_UNLOCK_FAIL;
+ PROD_DBG_UNLOCK_IN_PROGRESS_cp : coverpoint PROD_DBG_UNLOCK_IN_PROGRESS;
+ UDS_PROGRAM_SUCCESS_cp : coverpoint UDS_PROGRAM_SUCCESS;
+ UDS_PROGRAM_FAIL_cp : coverpoint UDS_PROGRAM_FAIL;
+ UDS_PROGRAM_IN_PROGRESS_cp : coverpoint UDS_PROGRAM_IN_PROGRESS;
+ RSVD_cp : coverpoint RSVD;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_SOC_DBG_UNLOCK_LEVEL COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL_fld_cg with function sample(
+ input bit [32-1:0] LEVEL
+ );
+ option.per_instance = 1;
+ LEVEL_cp : coverpoint LEVEL;
+
+ endgroup
+
+ /*----------------------- SOC_IFC_REG__SS_GENERIC_FW_EXEC_CTRL COVERGROUPS -----------------------*/
+ covergroup soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL_bit_cg with function sample(input bit reg_bit);
+ option.per_instance = 1;
+ reg_bit_cp : coverpoint reg_bit {
+ bins value[2] = {0,1};
+ }
+ reg_bit_edge_cp : coverpoint reg_bit {
+ bins rise = (0 => 1);
+ bins fall = (1 => 0);
+ }
+
+ endgroup
+ covergroup soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL_fld_cg with function sample(
+ input bit [32-1:0] go
+ );
+ option.per_instance = 1;
+ go_cp : coverpoint go;
endgroup
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
index dbbea2814..e3c456864 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
+++ b/src/soc_ifc/rtl/soc_ifc_reg_pkg.sv
@@ -11,17 +11,27 @@ package soc_ifc_reg_pkg;
logic we;
} soc_ifc_reg__rw_rw_sticky_hw__in_t;
+ typedef struct packed{
+ logic [27:0] next;
+ } soc_ifc_reg__CPTRA_HW_ERROR_FATAL__rsvd__in_t;
+
typedef struct packed{
soc_ifc_reg__rw_rw_sticky_hw__in_t iccm_ecc_unc;
soc_ifc_reg__rw_rw_sticky_hw__in_t dccm_ecc_unc;
soc_ifc_reg__rw_rw_sticky_hw__in_t nmi_pin;
soc_ifc_reg__rw_rw_sticky_hw__in_t crypto_err;
+ soc_ifc_reg__CPTRA_HW_ERROR_FATAL__rsvd__in_t rsvd;
} soc_ifc_reg__CPTRA_HW_ERROR_FATAL__in_t;
+ typedef struct packed{
+ logic [28:0] next;
+ } soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL__rsvd__in_t;
+
typedef struct packed{
soc_ifc_reg__rw_rw_sticky_hw__in_t mbox_prot_no_lock;
soc_ifc_reg__rw_rw_sticky_hw__in_t mbox_prot_ooo;
soc_ifc_reg__rw_rw_sticky_hw__in_t mbox_ecc_unc;
+ soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL__rsvd__in_t rsvd;
} soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL__in_t;
typedef struct packed{
@@ -179,27 +189,22 @@ package soc_ifc_reg_pkg;
} soc_ifc_reg__CPTRA_HW_CONFIG__iTRNG_en__in_t;
typedef struct packed{
- logic next;
- } soc_ifc_reg__CPTRA_HW_CONFIG__QSPI_en__in_t;
-
- typedef struct packed{
- logic next;
- } soc_ifc_reg__CPTRA_HW_CONFIG__I3C_en__in_t;
+ logic [2:0] next;
+ } soc_ifc_reg__CPTRA_HW_CONFIG__RSVD_en__in_t;
typedef struct packed{
logic next;
- } soc_ifc_reg__CPTRA_HW_CONFIG__UART_en__in_t;
+ } soc_ifc_reg__CPTRA_HW_CONFIG__LMS_acc_en__in_t;
typedef struct packed{
logic next;
- } soc_ifc_reg__CPTRA_HW_CONFIG__LMS_acc_en__in_t;
+ } soc_ifc_reg__CPTRA_HW_CONFIG__ACTIVE_MODE_en__in_t;
typedef struct packed{
soc_ifc_reg__CPTRA_HW_CONFIG__iTRNG_en__in_t iTRNG_en;
- soc_ifc_reg__CPTRA_HW_CONFIG__QSPI_en__in_t QSPI_en;
- soc_ifc_reg__CPTRA_HW_CONFIG__I3C_en__in_t I3C_en;
- soc_ifc_reg__CPTRA_HW_CONFIG__UART_en__in_t UART_en;
+ soc_ifc_reg__CPTRA_HW_CONFIG__RSVD_en__in_t RSVD_en;
soc_ifc_reg__CPTRA_HW_CONFIG__LMS_acc_en__in_t LMS_acc_en;
+ soc_ifc_reg__CPTRA_HW_CONFIG__ACTIVE_MODE_en__in_t ACTIVE_MODE_en;
} soc_ifc_reg__CPTRA_HW_CONFIG__in_t;
typedef struct packed{
@@ -231,6 +236,46 @@ package soc_ifc_reg_pkg;
soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__LOCK__in_t LOCK;
} soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__in_t;
+ typedef struct packed{
+ logic swwel;
+ } soc_ifc_reg__CPTRA_HW_CAPABILITIES__cap__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_HW_CAPABILITIES__cap__in_t cap;
+ } soc_ifc_reg__CPTRA_HW_CAPABILITIES__in_t;
+
+ typedef struct packed{
+ logic swwel;
+ } soc_ifc_reg__CPTRA_FW_CAPABILITIES__cap__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_FW_CAPABILITIES__cap__in_t cap;
+ } soc_ifc_reg__CPTRA_FW_CAPABILITIES__in_t;
+
+ typedef struct packed{
+ logic swwel;
+ } soc_ifc_reg__CPTRA_CAP_LOCK__lock__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_CAP_LOCK__lock__in_t lock;
+ } soc_ifc_reg__CPTRA_CAP_LOCK__in_t;
+
+ typedef struct packed{
+ logic swwel;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH__hash__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH__hash__in_t hash;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH__in_t;
+
+ typedef struct packed{
+ logic swwe;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__lock__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__lock__in_t lock;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__in_t;
+
typedef struct packed{
logic swwel;
logic hwclr;
@@ -253,17 +298,9 @@ package soc_ifc_reg_pkg;
} soc_ifc_reg__fuse_key_manifest_pk_hash__in_t;
typedef struct packed{
- logic swwel;
- } soc_ifc_reg__Fuse_w4__in_t;
-
- typedef struct packed{
- soc_ifc_reg__Fuse_w4__in_t mask;
+ soc_ifc_reg__Fuse_w32__in_t mask;
} soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t;
- typedef struct packed{
- soc_ifc_reg__Fuse_w32__in_t hash;
- } soc_ifc_reg__fuse_owner_pk_hash__in_t;
-
typedef struct packed{
soc_ifc_reg__Fuse_w32__in_t svn;
} soc_ifc_reg__fuse_fmc_key_manifest_svn__in_t;
@@ -289,20 +326,16 @@ package soc_ifc_reg_pkg;
} soc_ifc_reg__fuse_idevid_manuf_hsm_id__in_t;
typedef struct packed{
- logic swwel;
- } soc_ifc_reg__Fuse_w2__in_t;
-
- typedef struct packed{
- soc_ifc_reg__Fuse_w2__in_t life_cycle;
- } soc_ifc_reg__fuse_life_cycle__in_t;
+ soc_ifc_reg__Fuse_w32__in_t lms_revocation;
+ } soc_ifc_reg__fuse_lms_revocation__in_t;
typedef struct packed{
- soc_ifc_reg__Fuse__in_t lms_verify;
- } soc_ifc_reg__fuse_lms_verify__in_t;
+ logic swwel;
+ } soc_ifc_reg__Fuse_w4__in_t;
typedef struct packed{
- soc_ifc_reg__Fuse_w32__in_t lms_revocation;
- } soc_ifc_reg__fuse_lms_revocation__in_t;
+ soc_ifc_reg__Fuse_w4__in_t mldsa_revocation;
+ } soc_ifc_reg__fuse_mldsa_revocation__in_t;
typedef struct packed{
logic swwel;
@@ -312,6 +345,187 @@ package soc_ifc_reg_pkg;
soc_ifc_reg__Fuse_w16__in_t soc_stepping_id;
} soc_ifc_reg__fuse_soc_stepping_id__in_t;
+ typedef struct packed{
+ soc_ifc_reg__Fuse_w32__in_t token;
+ } soc_ifc_reg__fuse_manuf_dbg_unlock_token__in_t;
+
+ typedef struct packed{
+ logic [31:0] next;
+ logic we;
+ logic swwel;
+ } soc_ifc_reg__strap_w32__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_l;
+ } soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_h;
+ } soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_l;
+ } soc_ifc_reg__SS_MCI_BASE_ADDR_L__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_h;
+ } soc_ifc_reg__SS_MCI_BASE_ADDR_H__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_l;
+ } soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_h;
+ } soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_l;
+ } soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_h;
+ } soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_l;
+ } soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t addr_h;
+ } soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t offset;
+ } soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t num;
+ } soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ } soc_ifc_reg__SS_DEBUG_INTENT__strap__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_DEBUG_INTENT__strap__in_t debug_intent;
+ } soc_ifc_reg__SS_DEBUG_INTENT__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__in_t data;
+ } soc_ifc_reg__SS_STRAP_GENERIC__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__MANUF_DBG_UNLOCK_REQ__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__PROD_DBG_UNLOCK_REQ__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__UDS_PROGRAM_REQ__in_t;
+
+ typedef struct packed{
+ logic [28:0] next;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__RSVD__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__MANUF_DBG_UNLOCK_REQ__in_t MANUF_DBG_UNLOCK_REQ;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__PROD_DBG_UNLOCK_REQ__in_t PROD_DBG_UNLOCK_REQ;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__UDS_PROGRAM_REQ__in_t UDS_PROGRAM_REQ;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__RSVD__in_t RSVD;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_SUCCESS__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_FAIL__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_IN_PROGRESS__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_SUCCESS__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_FAIL__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_IN_PROGRESS__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_SUCCESS__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_FAIL__in_t;
+
+ typedef struct packed{
+ logic next;
+ logic we;
+ logic swwe;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_IN_PROGRESS__in_t;
+
+ typedef struct packed{
+ logic [22:0] next;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__RSVD__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_SUCCESS__in_t MANUF_DBG_UNLOCK_SUCCESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_FAIL__in_t MANUF_DBG_UNLOCK_FAIL;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_IN_PROGRESS__in_t MANUF_DBG_UNLOCK_IN_PROGRESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_SUCCESS__in_t PROD_DBG_UNLOCK_SUCCESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_FAIL__in_t PROD_DBG_UNLOCK_FAIL;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_IN_PROGRESS__in_t PROD_DBG_UNLOCK_IN_PROGRESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_SUCCESS__in_t UDS_PROGRAM_SUCCESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_FAIL__in_t UDS_PROGRAM_FAIL;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_IN_PROGRESS__in_t UDS_PROGRAM_IN_PROGRESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__RSVD__in_t RSVD;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__in_t;
+
+ typedef struct packed{
+ logic [31:0] next;
+ logic we;
+ logic swwel;
+ } soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__LEVEL__in_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__LEVEL__in_t LEVEL;
+ } soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__in_t;
+
typedef struct packed{
logic [31:0] next;
logic wel;
@@ -454,20 +668,41 @@ package soc_ifc_reg_pkg;
soc_ifc_reg__CPTRA_WDT_STATUS__in_t CPTRA_WDT_STATUS;
soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__in_t CPTRA_FUSE_VALID_AXI_USER;
soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__in_t CPTRA_FUSE_AXI_USER_LOCK;
+ soc_ifc_reg__CPTRA_HW_CAPABILITIES__in_t CPTRA_HW_CAPABILITIES;
+ soc_ifc_reg__CPTRA_FW_CAPABILITIES__in_t CPTRA_FW_CAPABILITIES;
+ soc_ifc_reg__CPTRA_CAP_LOCK__in_t CPTRA_CAP_LOCK;
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH__in_t [12-1:0]CPTRA_OWNER_PK_HASH;
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__in_t CPTRA_OWNER_PK_HASH_LOCK;
soc_ifc_reg__fuse_uds_seed__in_t [16-1:0]fuse_uds_seed;
soc_ifc_reg__fuse_field_entropy__in_t [8-1:0]fuse_field_entropy;
soc_ifc_reg__fuse_key_manifest_pk_hash__in_t [12-1:0]fuse_key_manifest_pk_hash;
- soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t fuse_key_manifest_pk_hash_mask;
- soc_ifc_reg__fuse_owner_pk_hash__in_t [12-1:0]fuse_owner_pk_hash;
+ soc_ifc_reg__fuse_key_manifest_pk_hash_mask__in_t [8-1:0]fuse_key_manifest_pk_hash_mask;
soc_ifc_reg__fuse_fmc_key_manifest_svn__in_t fuse_fmc_key_manifest_svn;
soc_ifc_reg__fuse_runtime_svn__in_t [4-1:0]fuse_runtime_svn;
soc_ifc_reg__fuse_anti_rollback_disable__in_t fuse_anti_rollback_disable;
soc_ifc_reg__fuse_idevid_cert_attr__in_t [24-1:0]fuse_idevid_cert_attr;
soc_ifc_reg__fuse_idevid_manuf_hsm_id__in_t [4-1:0]fuse_idevid_manuf_hsm_id;
- soc_ifc_reg__fuse_life_cycle__in_t fuse_life_cycle;
- soc_ifc_reg__fuse_lms_verify__in_t fuse_lms_verify;
soc_ifc_reg__fuse_lms_revocation__in_t fuse_lms_revocation;
+ soc_ifc_reg__fuse_mldsa_revocation__in_t fuse_mldsa_revocation;
soc_ifc_reg__fuse_soc_stepping_id__in_t fuse_soc_stepping_id;
+ soc_ifc_reg__fuse_manuf_dbg_unlock_token__in_t [4-1:0]fuse_manuf_dbg_unlock_token;
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L__in_t SS_CALIPTRA_BASE_ADDR_L;
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H__in_t SS_CALIPTRA_BASE_ADDR_H;
+ soc_ifc_reg__SS_MCI_BASE_ADDR_L__in_t SS_MCI_BASE_ADDR_L;
+ soc_ifc_reg__SS_MCI_BASE_ADDR_H__in_t SS_MCI_BASE_ADDR_H;
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L__in_t SS_RECOVERY_IFC_BASE_ADDR_L;
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H__in_t SS_RECOVERY_IFC_BASE_ADDR_H;
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L__in_t SS_OTP_FC_BASE_ADDR_L;
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H__in_t SS_OTP_FC_BASE_ADDR_H;
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L__in_t SS_UDS_SEED_BASE_ADDR_L;
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H__in_t SS_UDS_SEED_BASE_ADDR_H;
+ soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET__in_t SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET;
+ soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES__in_t SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES;
+ soc_ifc_reg__SS_DEBUG_INTENT__in_t SS_DEBUG_INTENT;
+ soc_ifc_reg__SS_STRAP_GENERIC__in_t [4-1:0]SS_STRAP_GENERIC;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__in_t SS_DBG_MANUF_SERVICE_REG_REQ;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__in_t SS_DBG_MANUF_SERVICE_REG_RSP;
+ soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__in_t [2-1:0]SS_SOC_DBG_UNLOCK_LEVEL;
soc_ifc_reg__internal_obf_key__in_t [8-1:0]internal_obf_key;
soc_ifc_reg__internal_iccm_lock__in_t internal_iccm_lock;
soc_ifc_reg__internal_rv_mtime_l__in_t internal_rv_mtime_l;
@@ -543,7 +778,7 @@ package soc_ifc_reg_pkg;
typedef struct packed{
logic value;
- } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fw__out_t;
+ } soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_mb_processing__out_t;
typedef struct packed{
logic value;
@@ -555,7 +790,7 @@ package soc_ifc_reg_pkg;
typedef struct packed{
soc_ifc_reg__CPTRA_FLOW_STATUS__idevid_csr_ready__out_t idevid_csr_ready;
- soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_fw__out_t ready_for_fw;
+ soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_mb_processing__out_t ready_for_mb_processing;
soc_ifc_reg__CPTRA_FLOW_STATUS__ready_for_runtime__out_t ready_for_runtime;
soc_ifc_reg__CPTRA_FLOW_STATUS__mailbox_flow_done__out_t mailbox_flow_done;
} soc_ifc_reg__CPTRA_FLOW_STATUS__out_t;
@@ -763,6 +998,30 @@ package soc_ifc_reg_pkg;
soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__LOCK__out_t LOCK;
} soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__out_t;
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__CPTRA_CAP_LOCK__lock__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_CAP_LOCK__lock__out_t lock;
+ } soc_ifc_reg__CPTRA_CAP_LOCK__out_t;
+
+ typedef struct packed{
+ logic [31:0] value;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH__hash__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH__hash__out_t hash;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__lock__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__lock__out_t lock;
+ } soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__out_t;
+
typedef struct packed{
logic [31:0] value;
} soc_ifc_reg__secret_w32__out_t;
@@ -784,17 +1043,9 @@ package soc_ifc_reg_pkg;
} soc_ifc_reg__fuse_key_manifest_pk_hash__out_t;
typedef struct packed{
- logic [3:0] value;
- } soc_ifc_reg__Fuse_w4__out_t;
-
- typedef struct packed{
- soc_ifc_reg__Fuse_w4__out_t mask;
+ soc_ifc_reg__Fuse_w32__out_t mask;
} soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t;
- typedef struct packed{
- soc_ifc_reg__Fuse_w32__out_t hash;
- } soc_ifc_reg__fuse_owner_pk_hash__out_t;
-
typedef struct packed{
soc_ifc_reg__Fuse_w32__out_t svn;
} soc_ifc_reg__fuse_fmc_key_manifest_svn__out_t;
@@ -820,20 +1071,16 @@ package soc_ifc_reg_pkg;
} soc_ifc_reg__fuse_idevid_manuf_hsm_id__out_t;
typedef struct packed{
- logic [1:0] value;
- } soc_ifc_reg__Fuse_w2__out_t;
+ soc_ifc_reg__Fuse_w32__out_t lms_revocation;
+ } soc_ifc_reg__fuse_lms_revocation__out_t;
typedef struct packed{
- soc_ifc_reg__Fuse_w2__out_t life_cycle;
- } soc_ifc_reg__fuse_life_cycle__out_t;
+ logic [3:0] value;
+ } soc_ifc_reg__Fuse_w4__out_t;
typedef struct packed{
- soc_ifc_reg__Fuse__out_t lms_verify;
- } soc_ifc_reg__fuse_lms_verify__out_t;
-
- typedef struct packed{
- soc_ifc_reg__Fuse_w32__out_t lms_revocation;
- } soc_ifc_reg__fuse_lms_revocation__out_t;
+ soc_ifc_reg__Fuse_w4__out_t mldsa_revocation;
+ } soc_ifc_reg__fuse_mldsa_revocation__out_t;
typedef struct packed{
logic [15:0] value;
@@ -843,6 +1090,156 @@ package soc_ifc_reg_pkg;
soc_ifc_reg__Fuse_w16__out_t soc_stepping_id;
} soc_ifc_reg__fuse_soc_stepping_id__out_t;
+ typedef struct packed{
+ soc_ifc_reg__Fuse_w32__out_t token;
+ } soc_ifc_reg__fuse_manuf_dbg_unlock_token__out_t;
+
+ typedef struct packed{
+ logic [31:0] value;
+ } soc_ifc_reg__strap_w32__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_l;
+ } soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_h;
+ } soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_l;
+ } soc_ifc_reg__SS_MCI_BASE_ADDR_L__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_h;
+ } soc_ifc_reg__SS_MCI_BASE_ADDR_H__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_l;
+ } soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_h;
+ } soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_l;
+ } soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_h;
+ } soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_l;
+ } soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t addr_h;
+ } soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t offset;
+ } soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t num;
+ } soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DEBUG_INTENT__strap__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_DEBUG_INTENT__strap__out_t debug_intent;
+ } soc_ifc_reg__SS_DEBUG_INTENT__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__strap_w32__out_t data;
+ } soc_ifc_reg__SS_STRAP_GENERIC__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__MANUF_DBG_UNLOCK_REQ__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__PROD_DBG_UNLOCK_REQ__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__UDS_PROGRAM_REQ__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__MANUF_DBG_UNLOCK_REQ__out_t MANUF_DBG_UNLOCK_REQ;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__PROD_DBG_UNLOCK_REQ__out_t PROD_DBG_UNLOCK_REQ;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__UDS_PROGRAM_REQ__out_t UDS_PROGRAM_REQ;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_SUCCESS__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_FAIL__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_IN_PROGRESS__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_SUCCESS__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_FAIL__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_IN_PROGRESS__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_SUCCESS__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_FAIL__out_t;
+
+ typedef struct packed{
+ logic value;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_IN_PROGRESS__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_SUCCESS__out_t MANUF_DBG_UNLOCK_SUCCESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_FAIL__out_t MANUF_DBG_UNLOCK_FAIL;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__MANUF_DBG_UNLOCK_IN_PROGRESS__out_t MANUF_DBG_UNLOCK_IN_PROGRESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_SUCCESS__out_t PROD_DBG_UNLOCK_SUCCESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_FAIL__out_t PROD_DBG_UNLOCK_FAIL;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__PROD_DBG_UNLOCK_IN_PROGRESS__out_t PROD_DBG_UNLOCK_IN_PROGRESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_SUCCESS__out_t UDS_PROGRAM_SUCCESS;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_FAIL__out_t UDS_PROGRAM_FAIL;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__UDS_PROGRAM_IN_PROGRESS__out_t UDS_PROGRAM_IN_PROGRESS;
+ } soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__out_t;
+
+ typedef struct packed{
+ logic [31:0] value;
+ } soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__LEVEL__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__LEVEL__out_t LEVEL;
+ } soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__out_t;
+
+ typedef struct packed{
+ logic [31:0] value;
+ } soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL__go__out_t;
+
+ typedef struct packed{
+ soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL__go__out_t go;
+ } soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL__out_t;
+
typedef struct packed{
logic [31:0] value;
} soc_ifc_reg__key_w32__out_t;
@@ -1003,20 +1400,40 @@ package soc_ifc_reg_pkg;
soc_ifc_reg__CPTRA_WDT_STATUS__out_t CPTRA_WDT_STATUS;
soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER__out_t CPTRA_FUSE_VALID_AXI_USER;
soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK__out_t CPTRA_FUSE_AXI_USER_LOCK;
+ soc_ifc_reg__CPTRA_CAP_LOCK__out_t CPTRA_CAP_LOCK;
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH__out_t [12-1:0]CPTRA_OWNER_PK_HASH;
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK__out_t CPTRA_OWNER_PK_HASH_LOCK;
soc_ifc_reg__fuse_uds_seed__out_t [16-1:0]fuse_uds_seed;
soc_ifc_reg__fuse_field_entropy__out_t [8-1:0]fuse_field_entropy;
soc_ifc_reg__fuse_key_manifest_pk_hash__out_t [12-1:0]fuse_key_manifest_pk_hash;
- soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t fuse_key_manifest_pk_hash_mask;
- soc_ifc_reg__fuse_owner_pk_hash__out_t [12-1:0]fuse_owner_pk_hash;
+ soc_ifc_reg__fuse_key_manifest_pk_hash_mask__out_t [8-1:0]fuse_key_manifest_pk_hash_mask;
soc_ifc_reg__fuse_fmc_key_manifest_svn__out_t fuse_fmc_key_manifest_svn;
soc_ifc_reg__fuse_runtime_svn__out_t [4-1:0]fuse_runtime_svn;
soc_ifc_reg__fuse_anti_rollback_disable__out_t fuse_anti_rollback_disable;
soc_ifc_reg__fuse_idevid_cert_attr__out_t [24-1:0]fuse_idevid_cert_attr;
soc_ifc_reg__fuse_idevid_manuf_hsm_id__out_t [4-1:0]fuse_idevid_manuf_hsm_id;
- soc_ifc_reg__fuse_life_cycle__out_t fuse_life_cycle;
- soc_ifc_reg__fuse_lms_verify__out_t fuse_lms_verify;
soc_ifc_reg__fuse_lms_revocation__out_t fuse_lms_revocation;
+ soc_ifc_reg__fuse_mldsa_revocation__out_t fuse_mldsa_revocation;
soc_ifc_reg__fuse_soc_stepping_id__out_t fuse_soc_stepping_id;
+ soc_ifc_reg__fuse_manuf_dbg_unlock_token__out_t [4-1:0]fuse_manuf_dbg_unlock_token;
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L__out_t SS_CALIPTRA_BASE_ADDR_L;
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H__out_t SS_CALIPTRA_BASE_ADDR_H;
+ soc_ifc_reg__SS_MCI_BASE_ADDR_L__out_t SS_MCI_BASE_ADDR_L;
+ soc_ifc_reg__SS_MCI_BASE_ADDR_H__out_t SS_MCI_BASE_ADDR_H;
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L__out_t SS_RECOVERY_IFC_BASE_ADDR_L;
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H__out_t SS_RECOVERY_IFC_BASE_ADDR_H;
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L__out_t SS_OTP_FC_BASE_ADDR_L;
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H__out_t SS_OTP_FC_BASE_ADDR_H;
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L__out_t SS_UDS_SEED_BASE_ADDR_L;
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H__out_t SS_UDS_SEED_BASE_ADDR_H;
+ soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET__out_t SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET;
+ soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES__out_t SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES;
+ soc_ifc_reg__SS_DEBUG_INTENT__out_t SS_DEBUG_INTENT;
+ soc_ifc_reg__SS_STRAP_GENERIC__out_t [4-1:0]SS_STRAP_GENERIC;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ__out_t SS_DBG_MANUF_SERVICE_REG_REQ;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP__out_t SS_DBG_MANUF_SERVICE_REG_RSP;
+ soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL__out_t [2-1:0]SS_SOC_DBG_UNLOCK_LEVEL;
+ soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL__out_t [4-1:0]SS_GENERIC_FW_EXEC_CTRL;
soc_ifc_reg__internal_obf_key__out_t [8-1:0]internal_obf_key;
soc_ifc_reg__internal_iccm_lock__out_t internal_iccm_lock;
soc_ifc_reg__internal_fw_update_reset__out_t internal_fw_update_reset;
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh
index e46e5a92b..f7c178b26 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg_sample.svh
+++ b/src/soc_ifc/rtl/soc_ifc_reg_sample.svh
@@ -28,9 +28,10 @@
foreach(dccm_ecc_unc_bit_cg[bt]) this.dccm_ecc_unc_bit_cg[bt].sample(data[1 + bt]);
foreach(nmi_pin_bit_cg[bt]) this.nmi_pin_bit_cg[bt].sample(data[2 + bt]);
foreach(crypto_err_bit_cg[bt]) this.crypto_err_bit_cg[bt].sample(data[3 + bt]);
+ foreach(rsvd_bit_cg[bt]) this.rsvd_bit_cg[bt].sample(data[4 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[0:0]/*iccm_ecc_unc*/ , data[1:1]/*dccm_ecc_unc*/ , data[2:2]/*nmi_pin*/ , data[3:3]/*crypto_err*/ );
+ this.fld_cg.sample( data[0:0]/*iccm_ecc_unc*/ , data[1:1]/*dccm_ecc_unc*/ , data[2:2]/*nmi_pin*/ , data[3:3]/*crypto_err*/ , data[31:4]/*rsvd*/ );
end
endfunction
@@ -40,9 +41,10 @@
foreach(dccm_ecc_unc_bit_cg[bt]) this.dccm_ecc_unc_bit_cg[bt].sample(dccm_ecc_unc.get_mirrored_value() >> bt);
foreach(nmi_pin_bit_cg[bt]) this.nmi_pin_bit_cg[bt].sample(nmi_pin.get_mirrored_value() >> bt);
foreach(crypto_err_bit_cg[bt]) this.crypto_err_bit_cg[bt].sample(crypto_err.get_mirrored_value() >> bt);
+ foreach(rsvd_bit_cg[bt]) this.rsvd_bit_cg[bt].sample(rsvd.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( iccm_ecc_unc.get_mirrored_value() , dccm_ecc_unc.get_mirrored_value() , nmi_pin.get_mirrored_value() , crypto_err.get_mirrored_value() );
+ this.fld_cg.sample( iccm_ecc_unc.get_mirrored_value() , dccm_ecc_unc.get_mirrored_value() , nmi_pin.get_mirrored_value() , crypto_err.get_mirrored_value() , rsvd.get_mirrored_value() );
end
endfunction
@@ -58,9 +60,10 @@
foreach(mbox_prot_no_lock_bit_cg[bt]) this.mbox_prot_no_lock_bit_cg[bt].sample(data[0 + bt]);
foreach(mbox_prot_ooo_bit_cg[bt]) this.mbox_prot_ooo_bit_cg[bt].sample(data[1 + bt]);
foreach(mbox_ecc_unc_bit_cg[bt]) this.mbox_ecc_unc_bit_cg[bt].sample(data[2 + bt]);
+ foreach(rsvd_bit_cg[bt]) this.rsvd_bit_cg[bt].sample(data[3 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[0:0]/*mbox_prot_no_lock*/ , data[1:1]/*mbox_prot_ooo*/ , data[2:2]/*mbox_ecc_unc*/ );
+ this.fld_cg.sample( data[0:0]/*mbox_prot_no_lock*/ , data[1:1]/*mbox_prot_ooo*/ , data[2:2]/*mbox_ecc_unc*/ , data[31:3]/*rsvd*/ );
end
endfunction
@@ -69,9 +72,10 @@
foreach(mbox_prot_no_lock_bit_cg[bt]) this.mbox_prot_no_lock_bit_cg[bt].sample(mbox_prot_no_lock.get_mirrored_value() >> bt);
foreach(mbox_prot_ooo_bit_cg[bt]) this.mbox_prot_ooo_bit_cg[bt].sample(mbox_prot_ooo.get_mirrored_value() >> bt);
foreach(mbox_ecc_unc_bit_cg[bt]) this.mbox_ecc_unc_bit_cg[bt].sample(mbox_ecc_unc.get_mirrored_value() >> bt);
+ foreach(rsvd_bit_cg[bt]) this.rsvd_bit_cg[bt].sample(rsvd.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( mbox_prot_no_lock.get_mirrored_value() , mbox_prot_ooo.get_mirrored_value() , mbox_ecc_unc.get_mirrored_value() );
+ this.fld_cg.sample( mbox_prot_no_lock.get_mirrored_value() , mbox_prot_ooo.get_mirrored_value() , mbox_ecc_unc.get_mirrored_value() , rsvd.get_mirrored_value() );
end
endfunction
@@ -237,13 +241,13 @@
foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(data[0 + bt]);
foreach(idevid_csr_ready_bit_cg[bt]) this.idevid_csr_ready_bit_cg[bt].sample(data[24 + bt]);
foreach(boot_fsm_ps_bit_cg[bt]) this.boot_fsm_ps_bit_cg[bt].sample(data[25 + bt]);
- foreach(ready_for_fw_bit_cg[bt]) this.ready_for_fw_bit_cg[bt].sample(data[28 + bt]);
+ foreach(ready_for_mb_processing_bit_cg[bt]) this.ready_for_mb_processing_bit_cg[bt].sample(data[28 + bt]);
foreach(ready_for_runtime_bit_cg[bt]) this.ready_for_runtime_bit_cg[bt].sample(data[29 + bt]);
foreach(ready_for_fuses_bit_cg[bt]) this.ready_for_fuses_bit_cg[bt].sample(data[30 + bt]);
foreach(mailbox_flow_done_bit_cg[bt]) this.mailbox_flow_done_bit_cg[bt].sample(data[31 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[23:0]/*status*/ , data[24:24]/*idevid_csr_ready*/ , data[27:25]/*boot_fsm_ps*/ , data[28:28]/*ready_for_fw*/ , data[29:29]/*ready_for_runtime*/ , data[30:30]/*ready_for_fuses*/ , data[31:31]/*mailbox_flow_done*/ );
+ this.fld_cg.sample( data[23:0]/*status*/ , data[24:24]/*idevid_csr_ready*/ , data[27:25]/*boot_fsm_ps*/ , data[28:28]/*ready_for_mb_processing*/ , data[29:29]/*ready_for_runtime*/ , data[30:30]/*ready_for_fuses*/ , data[31:31]/*mailbox_flow_done*/ );
end
endfunction
@@ -252,13 +256,13 @@
foreach(status_bit_cg[bt]) this.status_bit_cg[bt].sample(status.get_mirrored_value() >> bt);
foreach(idevid_csr_ready_bit_cg[bt]) this.idevid_csr_ready_bit_cg[bt].sample(idevid_csr_ready.get_mirrored_value() >> bt);
foreach(boot_fsm_ps_bit_cg[bt]) this.boot_fsm_ps_bit_cg[bt].sample(boot_fsm_ps.get_mirrored_value() >> bt);
- foreach(ready_for_fw_bit_cg[bt]) this.ready_for_fw_bit_cg[bt].sample(ready_for_fw.get_mirrored_value() >> bt);
+ foreach(ready_for_mb_processing_bit_cg[bt]) this.ready_for_mb_processing_bit_cg[bt].sample(ready_for_mb_processing.get_mirrored_value() >> bt);
foreach(ready_for_runtime_bit_cg[bt]) this.ready_for_runtime_bit_cg[bt].sample(ready_for_runtime.get_mirrored_value() >> bt);
foreach(ready_for_fuses_bit_cg[bt]) this.ready_for_fuses_bit_cg[bt].sample(ready_for_fuses.get_mirrored_value() >> bt);
foreach(mailbox_flow_done_bit_cg[bt]) this.mailbox_flow_done_bit_cg[bt].sample(mailbox_flow_done.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( status.get_mirrored_value() , idevid_csr_ready.get_mirrored_value() , boot_fsm_ps.get_mirrored_value() , ready_for_fw.get_mirrored_value() , ready_for_runtime.get_mirrored_value() , ready_for_fuses.get_mirrored_value() , mailbox_flow_done.get_mirrored_value() );
+ this.fld_cg.sample( status.get_mirrored_value() , idevid_csr_ready.get_mirrored_value() , boot_fsm_ps.get_mirrored_value() , ready_for_mb_processing.get_mirrored_value() , ready_for_runtime.get_mirrored_value() , ready_for_fuses.get_mirrored_value() , mailbox_flow_done.get_mirrored_value() );
end
endfunction
@@ -734,26 +738,24 @@
m_is_read = is_read;
if (get_coverage(UVM_CVR_REG_BITS)) begin
foreach(iTRNG_en_bit_cg[bt]) this.iTRNG_en_bit_cg[bt].sample(data[0 + bt]);
- foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(data[1 + bt]);
- foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(data[2 + bt]);
- foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(data[3 + bt]);
+ foreach(RSVD_en_bit_cg[bt]) this.RSVD_en_bit_cg[bt].sample(data[1 + bt]);
foreach(LMS_acc_en_bit_cg[bt]) this.LMS_acc_en_bit_cg[bt].sample(data[4 + bt]);
+ foreach(ACTIVE_MODE_en_bit_cg[bt]) this.ACTIVE_MODE_en_bit_cg[bt].sample(data[5 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[0:0]/*iTRNG_en*/ , data[1:1]/*QSPI_en*/ , data[2:2]/*I3C_en*/ , data[3:3]/*UART_en*/ , data[4:4]/*LMS_acc_en*/ );
+ this.fld_cg.sample( data[0:0]/*iTRNG_en*/ , data[3:1]/*RSVD_en*/ , data[4:4]/*LMS_acc_en*/ , data[5:5]/*ACTIVE_MODE_en*/ );
end
endfunction
function void soc_ifc_reg__CPTRA_HW_CONFIG::sample_values();
if (get_coverage(UVM_CVR_REG_BITS)) begin
foreach(iTRNG_en_bit_cg[bt]) this.iTRNG_en_bit_cg[bt].sample(iTRNG_en.get_mirrored_value() >> bt);
- foreach(QSPI_en_bit_cg[bt]) this.QSPI_en_bit_cg[bt].sample(QSPI_en.get_mirrored_value() >> bt);
- foreach(I3C_en_bit_cg[bt]) this.I3C_en_bit_cg[bt].sample(I3C_en.get_mirrored_value() >> bt);
- foreach(UART_en_bit_cg[bt]) this.UART_en_bit_cg[bt].sample(UART_en.get_mirrored_value() >> bt);
+ foreach(RSVD_en_bit_cg[bt]) this.RSVD_en_bit_cg[bt].sample(RSVD_en.get_mirrored_value() >> bt);
foreach(LMS_acc_en_bit_cg[bt]) this.LMS_acc_en_bit_cg[bt].sample(LMS_acc_en.get_mirrored_value() >> bt);
+ foreach(ACTIVE_MODE_en_bit_cg[bt]) this.ACTIVE_MODE_en_bit_cg[bt].sample(ACTIVE_MODE_en.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( iTRNG_en.get_mirrored_value() , QSPI_en.get_mirrored_value() , I3C_en.get_mirrored_value() , UART_en.get_mirrored_value() , LMS_acc_en.get_mirrored_value() );
+ this.fld_cg.sample( iTRNG_en.get_mirrored_value() , RSVD_en.get_mirrored_value() , LMS_acc_en.get_mirrored_value() , ACTIVE_MODE_en.get_mirrored_value() );
end
endfunction
@@ -1088,6 +1090,131 @@
end
endfunction
+ /*----------------------- SOC_IFC_REG__CPTRA_HW_CAPABILITIES SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__CPTRA_HW_CAPABILITIES::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(cap_bit_cg[bt]) this.cap_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*cap*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__CPTRA_HW_CAPABILITIES::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(cap_bit_cg[bt]) this.cap_bit_cg[bt].sample(cap.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( cap.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__CPTRA_FW_CAPABILITIES SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__CPTRA_FW_CAPABILITIES::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(cap_bit_cg[bt]) this.cap_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*cap*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__CPTRA_FW_CAPABILITIES::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(cap_bit_cg[bt]) this.cap_bit_cg[bt].sample(cap.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( cap.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__CPTRA_CAP_LOCK SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__CPTRA_CAP_LOCK::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[0:0]/*lock*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__CPTRA_CAP_LOCK::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(lock.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( lock.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__CPTRA_OWNER_PK_HASH::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*hash*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__CPTRA_OWNER_PK_HASH::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(hash.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( hash.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__CPTRA_OWNER_PK_HASH_LOCK SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[0:0]/*lock*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(lock_bit_cg[bt]) this.lock_bit_cg[bt].sample(lock.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( lock.get_mirrored_value() );
+ end
+ endfunction
+
/*----------------------- SOC_IFC_REG__FUSE_UDS_SEED SAMPLE FUNCTIONS -----------------------*/
function void soc_ifc_reg__fuse_uds_seed::sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
@@ -1175,7 +1302,7 @@
foreach(mask_bit_cg[bt]) this.mask_bit_cg[bt].sample(data[0 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[3:0]/*mask*/ );
+ this.fld_cg.sample( data[31:0]/*mask*/ );
end
endfunction
@@ -1188,31 +1315,6 @@
end
endfunction
- /*----------------------- SOC_IFC_REG__FUSE_OWNER_PK_HASH SAMPLE FUNCTIONS -----------------------*/
- function void soc_ifc_reg__fuse_owner_pk_hash::sample(uvm_reg_data_t data,
- uvm_reg_data_t byte_en,
- bit is_read,
- uvm_reg_map map);
- m_current = get();
- m_data = data;
- m_is_read = is_read;
- if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(data[0 + bt]);
- end
- if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[31:0]/*hash*/ );
- end
- endfunction
-
- function void soc_ifc_reg__fuse_owner_pk_hash::sample_values();
- if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(hash_bit_cg[bt]) this.hash_bit_cg[bt].sample(hash.get_mirrored_value() >> bt);
- end
- if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( hash.get_mirrored_value() );
- end
- endfunction
-
/*----------------------- SOC_IFC_REG__FUSE_FMC_KEY_MANIFEST_SVN SAMPLE FUNCTIONS -----------------------*/
function void soc_ifc_reg__fuse_fmc_key_manifest_svn::sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
@@ -1338,8 +1440,8 @@
end
endfunction
- /*----------------------- SOC_IFC_REG__FUSE_LIFE_CYCLE SAMPLE FUNCTIONS -----------------------*/
- function void soc_ifc_reg__fuse_life_cycle::sample(uvm_reg_data_t data,
+ /*----------------------- SOC_IFC_REG__FUSE_LMS_REVOCATION SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__fuse_lms_revocation::sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
bit is_read,
uvm_reg_map map);
@@ -1347,24 +1449,24 @@
m_data = data;
m_is_read = is_read;
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(life_cycle_bit_cg[bt]) this.life_cycle_bit_cg[bt].sample(data[0 + bt]);
+ foreach(lms_revocation_bit_cg[bt]) this.lms_revocation_bit_cg[bt].sample(data[0 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[1:0]/*life_cycle*/ );
+ this.fld_cg.sample( data[31:0]/*lms_revocation*/ );
end
endfunction
- function void soc_ifc_reg__fuse_life_cycle::sample_values();
+ function void soc_ifc_reg__fuse_lms_revocation::sample_values();
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(life_cycle_bit_cg[bt]) this.life_cycle_bit_cg[bt].sample(life_cycle.get_mirrored_value() >> bt);
+ foreach(lms_revocation_bit_cg[bt]) this.lms_revocation_bit_cg[bt].sample(lms_revocation.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( life_cycle.get_mirrored_value() );
+ this.fld_cg.sample( lms_revocation.get_mirrored_value() );
end
endfunction
- /*----------------------- SOC_IFC_REG__FUSE_LMS_VERIFY SAMPLE FUNCTIONS -----------------------*/
- function void soc_ifc_reg__fuse_lms_verify::sample(uvm_reg_data_t data,
+ /*----------------------- SOC_IFC_REG__FUSE_MLDSA_REVOCATION SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__fuse_mldsa_revocation::sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
bit is_read,
uvm_reg_map map);
@@ -1372,24 +1474,24 @@
m_data = data;
m_is_read = is_read;
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(lms_verify_bit_cg[bt]) this.lms_verify_bit_cg[bt].sample(data[0 + bt]);
+ foreach(mldsa_revocation_bit_cg[bt]) this.mldsa_revocation_bit_cg[bt].sample(data[0 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[0:0]/*lms_verify*/ );
+ this.fld_cg.sample( data[3:0]/*mldsa_revocation*/ );
end
endfunction
- function void soc_ifc_reg__fuse_lms_verify::sample_values();
+ function void soc_ifc_reg__fuse_mldsa_revocation::sample_values();
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(lms_verify_bit_cg[bt]) this.lms_verify_bit_cg[bt].sample(lms_verify.get_mirrored_value() >> bt);
+ foreach(mldsa_revocation_bit_cg[bt]) this.mldsa_revocation_bit_cg[bt].sample(mldsa_revocation.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( lms_verify.get_mirrored_value() );
+ this.fld_cg.sample( mldsa_revocation.get_mirrored_value() );
end
endfunction
- /*----------------------- SOC_IFC_REG__FUSE_LMS_REVOCATION SAMPLE FUNCTIONS -----------------------*/
- function void soc_ifc_reg__fuse_lms_revocation::sample(uvm_reg_data_t data,
+ /*----------------------- SOC_IFC_REG__FUSE_SOC_STEPPING_ID SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__fuse_soc_stepping_id::sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
bit is_read,
uvm_reg_map map);
@@ -1397,24 +1499,24 @@
m_data = data;
m_is_read = is_read;
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(lms_revocation_bit_cg[bt]) this.lms_revocation_bit_cg[bt].sample(data[0 + bt]);
+ foreach(soc_stepping_id_bit_cg[bt]) this.soc_stepping_id_bit_cg[bt].sample(data[0 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[31:0]/*lms_revocation*/ );
+ this.fld_cg.sample( data[15:0]/*soc_stepping_id*/ );
end
endfunction
- function void soc_ifc_reg__fuse_lms_revocation::sample_values();
+ function void soc_ifc_reg__fuse_soc_stepping_id::sample_values();
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(lms_revocation_bit_cg[bt]) this.lms_revocation_bit_cg[bt].sample(lms_revocation.get_mirrored_value() >> bt);
+ foreach(soc_stepping_id_bit_cg[bt]) this.soc_stepping_id_bit_cg[bt].sample(soc_stepping_id.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( lms_revocation.get_mirrored_value() );
+ this.fld_cg.sample( soc_stepping_id.get_mirrored_value() );
end
endfunction
- /*----------------------- SOC_IFC_REG__FUSE_SOC_STEPPING_ID SAMPLE FUNCTIONS -----------------------*/
- function void soc_ifc_reg__fuse_soc_stepping_id::sample(uvm_reg_data_t data,
+ /*----------------------- SOC_IFC_REG__FUSE_MANUF_DBG_UNLOCK_TOKEN SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__fuse_manuf_dbg_unlock_token::sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
bit is_read,
uvm_reg_map map);
@@ -1422,19 +1524,493 @@
m_data = data;
m_is_read = is_read;
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(soc_stepping_id_bit_cg[bt]) this.soc_stepping_id_bit_cg[bt].sample(data[0 + bt]);
+ foreach(token_bit_cg[bt]) this.token_bit_cg[bt].sample(data[0 + bt]);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( data[15:0]/*soc_stepping_id*/ );
+ this.fld_cg.sample( data[31:0]/*token*/ );
end
endfunction
- function void soc_ifc_reg__fuse_soc_stepping_id::sample_values();
+ function void soc_ifc_reg__fuse_manuf_dbg_unlock_token::sample_values();
if (get_coverage(UVM_CVR_REG_BITS)) begin
- foreach(soc_stepping_id_bit_cg[bt]) this.soc_stepping_id_bit_cg[bt].sample(soc_stepping_id.get_mirrored_value() >> bt);
+ foreach(token_bit_cg[bt]) this.token_bit_cg[bt].sample(token.get_mirrored_value() >> bt);
end
if (get_coverage(UVM_CVR_FIELD_VALS)) begin
- this.fld_cg.sample( soc_stepping_id.get_mirrored_value() );
+ this.fld_cg.sample( token.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_CALIPTRA_BASE_ADDR_L SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_l*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(addr_l.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_l.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_CALIPTRA_BASE_ADDR_H SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_h*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(addr_h.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_h.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_MCI_BASE_ADDR_L SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_MCI_BASE_ADDR_L::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_l*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_MCI_BASE_ADDR_L::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(addr_l.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_l.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_MCI_BASE_ADDR_H SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_MCI_BASE_ADDR_H::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_h*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_MCI_BASE_ADDR_H::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(addr_h.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_h.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_RECOVERY_IFC_BASE_ADDR_L SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_l*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(addr_l.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_l.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_RECOVERY_IFC_BASE_ADDR_H SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_h*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(addr_h.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_h.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_OTP_FC_BASE_ADDR_L SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_l*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(addr_l.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_l.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_OTP_FC_BASE_ADDR_H SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_h*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(addr_h.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_h.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_UDS_SEED_BASE_ADDR_L SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_l*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_l_bit_cg[bt]) this.addr_l_bit_cg[bt].sample(addr_l.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_l.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_UDS_SEED_BASE_ADDR_H SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*addr_h*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(addr_h_bit_cg[bt]) this.addr_h_bit_cg[bt].sample(addr_h.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( addr_h.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(offset_bit_cg[bt]) this.offset_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*offset*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(offset_bit_cg[bt]) this.offset_bit_cg[bt].sample(offset.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( offset.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(num_bit_cg[bt]) this.num_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*num*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(num_bit_cg[bt]) this.num_bit_cg[bt].sample(num.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( num.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_DEBUG_INTENT SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_DEBUG_INTENT::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(debug_intent_bit_cg[bt]) this.debug_intent_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[0:0]/*debug_intent*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_DEBUG_INTENT::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(debug_intent_bit_cg[bt]) this.debug_intent_bit_cg[bt].sample(debug_intent.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( debug_intent.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_STRAP_GENERIC SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_STRAP_GENERIC::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(data_bit_cg[bt]) this.data_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*data*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_STRAP_GENERIC::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(data_bit_cg[bt]) this.data_bit_cg[bt].sample(data.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_DBG_MANUF_SERVICE_REG_REQ SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(MANUF_DBG_UNLOCK_REQ_bit_cg[bt]) this.MANUF_DBG_UNLOCK_REQ_bit_cg[bt].sample(data[0 + bt]);
+ foreach(PROD_DBG_UNLOCK_REQ_bit_cg[bt]) this.PROD_DBG_UNLOCK_REQ_bit_cg[bt].sample(data[1 + bt]);
+ foreach(UDS_PROGRAM_REQ_bit_cg[bt]) this.UDS_PROGRAM_REQ_bit_cg[bt].sample(data[2 + bt]);
+ foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(data[3 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[0:0]/*MANUF_DBG_UNLOCK_REQ*/ , data[1:1]/*PROD_DBG_UNLOCK_REQ*/ , data[2:2]/*UDS_PROGRAM_REQ*/ , data[31:3]/*RSVD*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(MANUF_DBG_UNLOCK_REQ_bit_cg[bt]) this.MANUF_DBG_UNLOCK_REQ_bit_cg[bt].sample(MANUF_DBG_UNLOCK_REQ.get_mirrored_value() >> bt);
+ foreach(PROD_DBG_UNLOCK_REQ_bit_cg[bt]) this.PROD_DBG_UNLOCK_REQ_bit_cg[bt].sample(PROD_DBG_UNLOCK_REQ.get_mirrored_value() >> bt);
+ foreach(UDS_PROGRAM_REQ_bit_cg[bt]) this.UDS_PROGRAM_REQ_bit_cg[bt].sample(UDS_PROGRAM_REQ.get_mirrored_value() >> bt);
+ foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(RSVD.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( MANUF_DBG_UNLOCK_REQ.get_mirrored_value() , PROD_DBG_UNLOCK_REQ.get_mirrored_value() , UDS_PROGRAM_REQ.get_mirrored_value() , RSVD.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_DBG_MANUF_SERVICE_REG_RSP SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(MANUF_DBG_UNLOCK_SUCCESS_bit_cg[bt]) this.MANUF_DBG_UNLOCK_SUCCESS_bit_cg[bt].sample(data[0 + bt]);
+ foreach(MANUF_DBG_UNLOCK_FAIL_bit_cg[bt]) this.MANUF_DBG_UNLOCK_FAIL_bit_cg[bt].sample(data[1 + bt]);
+ foreach(MANUF_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt]) this.MANUF_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt].sample(data[2 + bt]);
+ foreach(PROD_DBG_UNLOCK_SUCCESS_bit_cg[bt]) this.PROD_DBG_UNLOCK_SUCCESS_bit_cg[bt].sample(data[3 + bt]);
+ foreach(PROD_DBG_UNLOCK_FAIL_bit_cg[bt]) this.PROD_DBG_UNLOCK_FAIL_bit_cg[bt].sample(data[4 + bt]);
+ foreach(PROD_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt]) this.PROD_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt].sample(data[5 + bt]);
+ foreach(UDS_PROGRAM_SUCCESS_bit_cg[bt]) this.UDS_PROGRAM_SUCCESS_bit_cg[bt].sample(data[6 + bt]);
+ foreach(UDS_PROGRAM_FAIL_bit_cg[bt]) this.UDS_PROGRAM_FAIL_bit_cg[bt].sample(data[7 + bt]);
+ foreach(UDS_PROGRAM_IN_PROGRESS_bit_cg[bt]) this.UDS_PROGRAM_IN_PROGRESS_bit_cg[bt].sample(data[8 + bt]);
+ foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(data[9 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[0:0]/*MANUF_DBG_UNLOCK_SUCCESS*/ , data[1:1]/*MANUF_DBG_UNLOCK_FAIL*/ , data[2:2]/*MANUF_DBG_UNLOCK_IN_PROGRESS*/ , data[3:3]/*PROD_DBG_UNLOCK_SUCCESS*/ , data[4:4]/*PROD_DBG_UNLOCK_FAIL*/ , data[5:5]/*PROD_DBG_UNLOCK_IN_PROGRESS*/ , data[6:6]/*UDS_PROGRAM_SUCCESS*/ , data[7:7]/*UDS_PROGRAM_FAIL*/ , data[8:8]/*UDS_PROGRAM_IN_PROGRESS*/ , data[31:9]/*RSVD*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(MANUF_DBG_UNLOCK_SUCCESS_bit_cg[bt]) this.MANUF_DBG_UNLOCK_SUCCESS_bit_cg[bt].sample(MANUF_DBG_UNLOCK_SUCCESS.get_mirrored_value() >> bt);
+ foreach(MANUF_DBG_UNLOCK_FAIL_bit_cg[bt]) this.MANUF_DBG_UNLOCK_FAIL_bit_cg[bt].sample(MANUF_DBG_UNLOCK_FAIL.get_mirrored_value() >> bt);
+ foreach(MANUF_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt]) this.MANUF_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt].sample(MANUF_DBG_UNLOCK_IN_PROGRESS.get_mirrored_value() >> bt);
+ foreach(PROD_DBG_UNLOCK_SUCCESS_bit_cg[bt]) this.PROD_DBG_UNLOCK_SUCCESS_bit_cg[bt].sample(PROD_DBG_UNLOCK_SUCCESS.get_mirrored_value() >> bt);
+ foreach(PROD_DBG_UNLOCK_FAIL_bit_cg[bt]) this.PROD_DBG_UNLOCK_FAIL_bit_cg[bt].sample(PROD_DBG_UNLOCK_FAIL.get_mirrored_value() >> bt);
+ foreach(PROD_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt]) this.PROD_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt].sample(PROD_DBG_UNLOCK_IN_PROGRESS.get_mirrored_value() >> bt);
+ foreach(UDS_PROGRAM_SUCCESS_bit_cg[bt]) this.UDS_PROGRAM_SUCCESS_bit_cg[bt].sample(UDS_PROGRAM_SUCCESS.get_mirrored_value() >> bt);
+ foreach(UDS_PROGRAM_FAIL_bit_cg[bt]) this.UDS_PROGRAM_FAIL_bit_cg[bt].sample(UDS_PROGRAM_FAIL.get_mirrored_value() >> bt);
+ foreach(UDS_PROGRAM_IN_PROGRESS_bit_cg[bt]) this.UDS_PROGRAM_IN_PROGRESS_bit_cg[bt].sample(UDS_PROGRAM_IN_PROGRESS.get_mirrored_value() >> bt);
+ foreach(RSVD_bit_cg[bt]) this.RSVD_bit_cg[bt].sample(RSVD.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( MANUF_DBG_UNLOCK_SUCCESS.get_mirrored_value() , MANUF_DBG_UNLOCK_FAIL.get_mirrored_value() , MANUF_DBG_UNLOCK_IN_PROGRESS.get_mirrored_value() , PROD_DBG_UNLOCK_SUCCESS.get_mirrored_value() , PROD_DBG_UNLOCK_FAIL.get_mirrored_value() , PROD_DBG_UNLOCK_IN_PROGRESS.get_mirrored_value() , UDS_PROGRAM_SUCCESS.get_mirrored_value() , UDS_PROGRAM_FAIL.get_mirrored_value() , UDS_PROGRAM_IN_PROGRESS.get_mirrored_value() , RSVD.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_SOC_DBG_UNLOCK_LEVEL SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(LEVEL_bit_cg[bt]) this.LEVEL_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*LEVEL*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(LEVEL_bit_cg[bt]) this.LEVEL_bit_cg[bt].sample(LEVEL.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( LEVEL.get_mirrored_value() );
+ end
+ endfunction
+
+ /*----------------------- SOC_IFC_REG__SS_GENERIC_FW_EXEC_CTRL SAMPLE FUNCTIONS -----------------------*/
+ function void soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL::sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+ m_current = get();
+ m_data = data;
+ m_is_read = is_read;
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(go_bit_cg[bt]) this.go_bit_cg[bt].sample(data[0 + bt]);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( data[31:0]/*go*/ );
+ end
+ endfunction
+
+ function void soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL::sample_values();
+ if (get_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(go_bit_cg[bt]) this.go_bit_cg[bt].sample(go.get_mirrored_value() >> bt);
+ end
+ if (get_coverage(UVM_CVR_FIELD_VALS)) begin
+ this.fld_cg.sample( go.get_mirrored_value() );
end
endfunction
diff --git a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv
index b6df335a9..df96f25fc 100644
--- a/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv
+++ b/src/soc_ifc/rtl/soc_ifc_reg_uvm.sv
@@ -14,11 +14,13 @@ package soc_ifc_reg_uvm;
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg dccm_ecc_unc_bit_cg[1];
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg nmi_pin_bit_cg[1];
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg crypto_err_bit_cg[1];
+ soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg rsvd_bit_cg[28];
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_fld_cg fld_cg;
rand uvm_reg_field iccm_ecc_unc;
rand uvm_reg_field dccm_ecc_unc;
rand uvm_reg_field nmi_pin;
rand uvm_reg_field crypto_err;
+ rand uvm_reg_field rsvd;
function new(string name = "soc_ifc_reg__CPTRA_HW_ERROR_FATAL");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
@@ -38,11 +40,14 @@ package soc_ifc_reg_uvm;
this.nmi_pin.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
this.crypto_err = new("crypto_err");
this.crypto_err.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
+ this.rsvd = new("rsvd");
+ this.rsvd.configure(this, 28, 4, "RO", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
foreach(iccm_ecc_unc_bit_cg[bt]) iccm_ecc_unc_bit_cg[bt] = new();
foreach(dccm_ecc_unc_bit_cg[bt]) dccm_ecc_unc_bit_cg[bt] = new();
foreach(nmi_pin_bit_cg[bt]) nmi_pin_bit_cg[bt] = new();
foreach(crypto_err_bit_cg[bt]) crypto_err_bit_cg[bt] = new();
+ foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
@@ -58,10 +63,12 @@ package soc_ifc_reg_uvm;
soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg mbox_prot_no_lock_bit_cg[1];
soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg mbox_prot_ooo_bit_cg[1];
soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg mbox_ecc_unc_bit_cg[1];
+ soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_bit_cg rsvd_bit_cg[29];
soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL_fld_cg fld_cg;
rand uvm_reg_field mbox_prot_no_lock;
rand uvm_reg_field mbox_prot_ooo;
rand uvm_reg_field mbox_ecc_unc;
+ rand uvm_reg_field rsvd;
function new(string name = "soc_ifc_reg__CPTRA_HW_ERROR_NON_FATAL");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
@@ -79,10 +86,13 @@ package soc_ifc_reg_uvm;
this.mbox_prot_ooo.configure(this, 1, 1, "W1C", 1, 'h0, 1, 1, 0);
this.mbox_ecc_unc = new("mbox_ecc_unc");
this.mbox_ecc_unc.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
+ this.rsvd = new("rsvd");
+ this.rsvd.configure(this, 29, 3, "RO", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
foreach(mbox_prot_no_lock_bit_cg[bt]) mbox_prot_no_lock_bit_cg[bt] = new();
foreach(mbox_prot_ooo_bit_cg[bt]) mbox_prot_ooo_bit_cg[bt] = new();
foreach(mbox_ecc_unc_bit_cg[bt]) mbox_ecc_unc_bit_cg[bt] = new();
+ foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
@@ -278,7 +288,7 @@ package soc_ifc_reg_uvm;
soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg status_bit_cg[24];
soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg idevid_csr_ready_bit_cg[1];
soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg boot_fsm_ps_bit_cg[3];
- soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg ready_for_fw_bit_cg[1];
+ soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg ready_for_mb_processing_bit_cg[1];
soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg ready_for_runtime_bit_cg[1];
soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg ready_for_fuses_bit_cg[1];
soc_ifc_reg__CPTRA_FLOW_STATUS_bit_cg mailbox_flow_done_bit_cg[1];
@@ -286,7 +296,7 @@ package soc_ifc_reg_uvm;
rand uvm_reg_field status;
rand uvm_reg_field idevid_csr_ready;
rand uvm_reg_field boot_fsm_ps;
- rand uvm_reg_field ready_for_fw;
+ rand uvm_reg_field ready_for_mb_processing;
rand uvm_reg_field ready_for_runtime;
rand uvm_reg_field ready_for_fuses;
rand uvm_reg_field mailbox_flow_done;
@@ -307,8 +317,8 @@ package soc_ifc_reg_uvm;
this.idevid_csr_ready.configure(this, 1, 24, "RW", 0, 'h0, 1, 1, 0);
this.boot_fsm_ps = new("boot_fsm_ps");
this.boot_fsm_ps.configure(this, 3, 25, "RO", 1, 'h0, 0, 1, 0);
- this.ready_for_fw = new("ready_for_fw");
- this.ready_for_fw.configure(this, 1, 28, "RW", 0, 'h0, 1, 1, 0);
+ this.ready_for_mb_processing = new("ready_for_mb_processing");
+ this.ready_for_mb_processing.configure(this, 1, 28, "RW", 0, 'h0, 1, 1, 0);
this.ready_for_runtime = new("ready_for_runtime");
this.ready_for_runtime.configure(this, 1, 29, "RW", 0, 'h0, 1, 1, 0);
this.ready_for_fuses = new("ready_for_fuses");
@@ -319,7 +329,7 @@ package soc_ifc_reg_uvm;
foreach(status_bit_cg[bt]) status_bit_cg[bt] = new();
foreach(idevid_csr_ready_bit_cg[bt]) idevid_csr_ready_bit_cg[bt] = new();
foreach(boot_fsm_ps_bit_cg[bt]) boot_fsm_ps_bit_cg[bt] = new();
- foreach(ready_for_fw_bit_cg[bt]) ready_for_fw_bit_cg[bt] = new();
+ foreach(ready_for_mb_processing_bit_cg[bt]) ready_for_mb_processing_bit_cg[bt] = new();
foreach(ready_for_runtime_bit_cg[bt]) ready_for_runtime_bit_cg[bt] = new();
foreach(ready_for_fuses_bit_cg[bt]) ready_for_fuses_bit_cg[bt] = new();
foreach(mailbox_flow_done_bit_cg[bt]) mailbox_flow_done_bit_cg[bt] = new();
@@ -906,16 +916,14 @@ package soc_ifc_reg_uvm;
protected bit m_is_read;
soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg iTRNG_en_bit_cg[1];
- soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg QSPI_en_bit_cg[1];
- soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg I3C_en_bit_cg[1];
- soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg UART_en_bit_cg[1];
+ soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg RSVD_en_bit_cg[3];
soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg LMS_acc_en_bit_cg[1];
+ soc_ifc_reg__CPTRA_HW_CONFIG_bit_cg ACTIVE_MODE_en_bit_cg[1];
soc_ifc_reg__CPTRA_HW_CONFIG_fld_cg fld_cg;
rand uvm_reg_field iTRNG_en;
- rand uvm_reg_field QSPI_en;
- rand uvm_reg_field I3C_en;
- rand uvm_reg_field UART_en;
+ rand uvm_reg_field RSVD_en;
rand uvm_reg_field LMS_acc_en;
+ rand uvm_reg_field ACTIVE_MODE_en;
function new(string name = "soc_ifc_reg__CPTRA_HW_CONFIG");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
@@ -929,20 +937,17 @@ package soc_ifc_reg_uvm;
virtual function void build();
this.iTRNG_en = new("iTRNG_en");
this.iTRNG_en.configure(this, 1, 0, "RO", 1, 'h0, 0, 1, 0);
- this.QSPI_en = new("QSPI_en");
- this.QSPI_en.configure(this, 1, 1, "RO", 1, 'h0, 0, 1, 0);
- this.I3C_en = new("I3C_en");
- this.I3C_en.configure(this, 1, 2, "RO", 1, 'h0, 0, 1, 0);
- this.UART_en = new("UART_en");
- this.UART_en.configure(this, 1, 3, "RO", 1, 'h0, 0, 1, 0);
+ this.RSVD_en = new("RSVD_en");
+ this.RSVD_en.configure(this, 3, 1, "RO", 1, 'h0, 0, 1, 0);
this.LMS_acc_en = new("LMS_acc_en");
this.LMS_acc_en.configure(this, 1, 4, "RO", 1, 'h0, 0, 1, 0);
+ this.ACTIVE_MODE_en = new("ACTIVE_MODE_en");
+ this.ACTIVE_MODE_en.configure(this, 1, 5, "RO", 1, 'h0, 0, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
foreach(iTRNG_en_bit_cg[bt]) iTRNG_en_bit_cg[bt] = new();
- foreach(QSPI_en_bit_cg[bt]) QSPI_en_bit_cg[bt] = new();
- foreach(I3C_en_bit_cg[bt]) I3C_en_bit_cg[bt] = new();
- foreach(UART_en_bit_cg[bt]) UART_en_bit_cg[bt] = new();
+ foreach(RSVD_en_bit_cg[bt]) RSVD_en_bit_cg[bt] = new();
foreach(LMS_acc_en_bit_cg[bt]) LMS_acc_en_bit_cg[bt] = new();
+ foreach(ACTIVE_MODE_en_bit_cg[bt]) ACTIVE_MODE_en_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
@@ -1089,27 +1094,702 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.timer2_restart = new("timer2_restart");
- this.timer2_restart.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.timer2_restart = new("timer2_restart");
+ this.timer2_restart.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(timer2_restart_bit_cg[bt]) timer2_restart_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL
+
+ // Reg - soc_ifc_reg::CPTRA_WDT_TIMER2_TIMEOUT_PERIOD
+ class soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_bit_cg timer2_timeout_period_bit_cg[32];
+ soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_fld_cg fld_cg;
+ rand uvm_reg_field timer2_timeout_period;
+
+ function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.timer2_timeout_period = new("timer2_timeout_period");
+ this.timer2_timeout_period.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(timer2_timeout_period_bit_cg[bt]) timer2_timeout_period_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD
+
+ // Reg - soc_ifc_reg::CPTRA_WDT_STATUS
+ class soc_ifc_reg__CPTRA_WDT_STATUS extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_WDT_STATUS_bit_cg t1_timeout_bit_cg[1];
+ soc_ifc_reg__CPTRA_WDT_STATUS_bit_cg t2_timeout_bit_cg[1];
+ soc_ifc_reg__CPTRA_WDT_STATUS_fld_cg fld_cg;
+ rand uvm_reg_field t1_timeout;
+ rand uvm_reg_field t2_timeout;
+
+ function new(string name = "soc_ifc_reg__CPTRA_WDT_STATUS");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.t1_timeout = new("t1_timeout");
+ this.t1_timeout.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
+ this.t2_timeout = new("t2_timeout");
+ this.t2_timeout.configure(this, 1, 1, "RW", 1, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(t1_timeout_bit_cg[bt]) t1_timeout_bit_cg[bt] = new();
+ foreach(t2_timeout_bit_cg[bt]) t2_timeout_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_WDT_STATUS
+
+ // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_AXI_USER
+ class soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_bit_cg AXI_USER_bit_cg[32];
+ soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_fld_cg fld_cg;
+ rand uvm_reg_field AXI_USER;
+
+ function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.AXI_USER = new("AXI_USER");
+ this.AXI_USER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(AXI_USER_bit_cg[bt]) AXI_USER_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER
+
+ // Reg - soc_ifc_reg::CPTRA_FUSE_AXI_USER_LOCK
+ class soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_bit_cg LOCK_bit_cg[1];
+ soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_fld_cg fld_cg;
+ rand uvm_reg_field LOCK;
+
+ function new(string name = "soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.LOCK = new("LOCK");
+ this.LOCK.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(LOCK_bit_cg[bt]) LOCK_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK
+
+ // Reg - soc_ifc_reg::CPTRA_WDT_CFG
+ class soc_ifc_reg__CPTRA_WDT_CFG extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_WDT_CFG_bit_cg TIMEOUT_bit_cg[32];
+ soc_ifc_reg__CPTRA_WDT_CFG_fld_cg fld_cg;
+ rand uvm_reg_field TIMEOUT;
+
+ function new(string name = "soc_ifc_reg__CPTRA_WDT_CFG");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.TIMEOUT = new("TIMEOUT");
+ this.TIMEOUT.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(TIMEOUT_bit_cg[bt]) TIMEOUT_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_WDT_CFG
+
+ // Reg - soc_ifc_reg::CPTRA_iTRNG_ENTROPY_CONFIG_0
+ class soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_bit_cg low_threshold_bit_cg[16];
+ soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_bit_cg high_threshold_bit_cg[16];
+ soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_fld_cg fld_cg;
+ rand uvm_reg_field low_threshold;
+ rand uvm_reg_field high_threshold;
+
+ function new(string name = "soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.low_threshold = new("low_threshold");
+ this.low_threshold.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.high_threshold = new("high_threshold");
+ this.high_threshold.configure(this, 16, 16, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(low_threshold_bit_cg[bt]) low_threshold_bit_cg[bt] = new();
+ foreach(high_threshold_bit_cg[bt]) high_threshold_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0
+
+ // Reg - soc_ifc_reg::CPTRA_iTRNG_ENTROPY_CONFIG_1
+ class soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_bit_cg repetition_count_bit_cg[16];
+ soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_bit_cg RSVD_bit_cg[16];
+ soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_fld_cg fld_cg;
+ rand uvm_reg_field repetition_count;
+ rand uvm_reg_field RSVD;
+
+ function new(string name = "soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.repetition_count = new("repetition_count");
+ this.repetition_count.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.RSVD = new("RSVD");
+ this.RSVD.configure(this, 16, 16, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(repetition_count_bit_cg[bt]) repetition_count_bit_cg[bt] = new();
+ foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1
+
+ // Reg - soc_ifc_reg::CPTRA_RSVD_REG
+ class soc_ifc_reg__CPTRA_RSVD_REG extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_RSVD_REG_bit_cg RSVD_bit_cg[32];
+ soc_ifc_reg__CPTRA_RSVD_REG_fld_cg fld_cg;
+ rand uvm_reg_field RSVD;
+
+ function new(string name = "soc_ifc_reg__CPTRA_RSVD_REG");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.RSVD = new("RSVD");
+ this.RSVD.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_RSVD_REG
+
+ // Reg - soc_ifc_reg::CPTRA_HW_CAPABILITIES
+ class soc_ifc_reg__CPTRA_HW_CAPABILITIES extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_HW_CAPABILITIES_bit_cg cap_bit_cg[32];
+ soc_ifc_reg__CPTRA_HW_CAPABILITIES_fld_cg fld_cg;
+ rand uvm_reg_field cap;
+
+ function new(string name = "soc_ifc_reg__CPTRA_HW_CAPABILITIES");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.cap = new("cap");
+ this.cap.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(cap_bit_cg[bt]) cap_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_HW_CAPABILITIES
+
+ // Reg - soc_ifc_reg::CPTRA_FW_CAPABILITIES
+ class soc_ifc_reg__CPTRA_FW_CAPABILITIES extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_FW_CAPABILITIES_bit_cg cap_bit_cg[32];
+ soc_ifc_reg__CPTRA_FW_CAPABILITIES_fld_cg fld_cg;
+ rand uvm_reg_field cap;
+
+ function new(string name = "soc_ifc_reg__CPTRA_FW_CAPABILITIES");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.cap = new("cap");
+ this.cap.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(cap_bit_cg[bt]) cap_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_FW_CAPABILITIES
+
+ // Reg - soc_ifc_reg::CPTRA_CAP_LOCK
+ class soc_ifc_reg__CPTRA_CAP_LOCK extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_CAP_LOCK_bit_cg lock_bit_cg[1];
+ soc_ifc_reg__CPTRA_CAP_LOCK_fld_cg fld_cg;
+ rand uvm_reg_field lock;
+
+ function new(string name = "soc_ifc_reg__CPTRA_CAP_LOCK");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.lock = new("lock");
+ this.lock.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(lock_bit_cg[bt]) lock_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_CAP_LOCK
+
+ // Reg - soc_ifc_reg::CPTRA_OWNER_PK_HASH
+ class soc_ifc_reg__CPTRA_OWNER_PK_HASH extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_bit_cg hash_bit_cg[32];
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_fld_cg fld_cg;
+ rand uvm_reg_field hash;
+
+ function new(string name = "soc_ifc_reg__CPTRA_OWNER_PK_HASH");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.hash = new("hash");
+ this.hash.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(hash_bit_cg[bt]) hash_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_OWNER_PK_HASH
+
+ // Reg - soc_ifc_reg::CPTRA_OWNER_PK_HASH_LOCK
+ class soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_bit_cg lock_bit_cg[1];
+ soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK_fld_cg fld_cg;
+ rand uvm_reg_field lock;
+
+ function new(string name = "soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.lock = new("lock");
+ this.lock.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(lock_bit_cg[bt]) lock_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK
+
+ // Reg - soc_ifc_reg::fuse_uds_seed
+ class soc_ifc_reg__fuse_uds_seed extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_uds_seed_bit_cg seed_bit_cg[32];
+ soc_ifc_reg__fuse_uds_seed_fld_cg fld_cg;
+ rand uvm_reg_field seed;
+
+ function new(string name = "soc_ifc_reg__fuse_uds_seed");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.seed = new("seed");
+ this.seed.configure(this, 32, 0, "WO1", 1, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(seed_bit_cg[bt]) seed_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_uds_seed
+
+ // Reg - soc_ifc_reg::fuse_field_entropy
+ class soc_ifc_reg__fuse_field_entropy extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_field_entropy_bit_cg seed_bit_cg[32];
+ soc_ifc_reg__fuse_field_entropy_fld_cg fld_cg;
+ rand uvm_reg_field seed;
+
+ function new(string name = "soc_ifc_reg__fuse_field_entropy");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.seed = new("seed");
+ this.seed.configure(this, 32, 0, "WO1", 1, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(seed_bit_cg[bt]) seed_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_field_entropy
+
+ // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash
+ class soc_ifc_reg__fuse_key_manifest_pk_hash extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_key_manifest_pk_hash_bit_cg hash_bit_cg[32];
+ soc_ifc_reg__fuse_key_manifest_pk_hash_fld_cg fld_cg;
+ rand uvm_reg_field hash;
+
+ function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.hash = new("hash");
+ this.hash.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(hash_bit_cg[bt]) hash_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_key_manifest_pk_hash
+
+ // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash_mask
+ class soc_ifc_reg__fuse_key_manifest_pk_hash_mask extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg mask_bit_cg[32];
+ soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg fld_cg;
+ rand uvm_reg_field mask;
+
+ function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash_mask");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.mask = new("mask");
+ this.mask.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(mask_bit_cg[bt]) mask_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_key_manifest_pk_hash_mask
+
+ // Reg - soc_ifc_reg::fuse_fmc_key_manifest_svn
+ class soc_ifc_reg__fuse_fmc_key_manifest_svn extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_fmc_key_manifest_svn_bit_cg svn_bit_cg[32];
+ soc_ifc_reg__fuse_fmc_key_manifest_svn_fld_cg fld_cg;
+ rand uvm_reg_field svn;
+
+ function new(string name = "soc_ifc_reg__fuse_fmc_key_manifest_svn");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.svn = new("svn");
+ this.svn.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_fmc_key_manifest_svn
+
+ // Reg - soc_ifc_reg::fuse_runtime_svn
+ class soc_ifc_reg__fuse_runtime_svn extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_runtime_svn_bit_cg svn_bit_cg[32];
+ soc_ifc_reg__fuse_runtime_svn_fld_cg fld_cg;
+ rand uvm_reg_field svn;
+
+ function new(string name = "soc_ifc_reg__fuse_runtime_svn");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.svn = new("svn");
+ this.svn.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_runtime_svn
+
+ // Reg - soc_ifc_reg::fuse_anti_rollback_disable
+ class soc_ifc_reg__fuse_anti_rollback_disable extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_anti_rollback_disable_bit_cg dis_bit_cg[1];
+ soc_ifc_reg__fuse_anti_rollback_disable_fld_cg fld_cg;
+ rand uvm_reg_field dis;
+
+ function new(string name = "soc_ifc_reg__fuse_anti_rollback_disable");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.dis = new("dis");
+ this.dis.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(dis_bit_cg[bt]) dis_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_anti_rollback_disable
+
+ // Reg - soc_ifc_reg::fuse_idevid_cert_attr
+ class soc_ifc_reg__fuse_idevid_cert_attr extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_idevid_cert_attr_bit_cg cert_bit_cg[32];
+ soc_ifc_reg__fuse_idevid_cert_attr_fld_cg fld_cg;
+ rand uvm_reg_field cert;
+
+ function new(string name = "soc_ifc_reg__fuse_idevid_cert_attr");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.cert = new("cert");
+ this.cert.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ if (has_coverage(UVM_CVR_REG_BITS)) begin
+ foreach(cert_bit_cg[bt]) cert_bit_cg[bt] = new();
+ end
+ if (has_coverage(UVM_CVR_FIELD_VALS))
+ fld_cg = new();
+ endfunction : build
+ endclass : soc_ifc_reg__fuse_idevid_cert_attr
+
+ // Reg - soc_ifc_reg::fuse_idevid_manuf_hsm_id
+ class soc_ifc_reg__fuse_idevid_manuf_hsm_id extends uvm_reg;
+ protected uvm_reg_data_t m_current;
+ protected uvm_reg_data_t m_data;
+ protected bit m_is_read;
+
+ soc_ifc_reg__fuse_idevid_manuf_hsm_id_bit_cg hsm_id_bit_cg[32];
+ soc_ifc_reg__fuse_idevid_manuf_hsm_id_fld_cg fld_cg;
+ rand uvm_reg_field hsm_id;
+
+ function new(string name = "soc_ifc_reg__fuse_idevid_manuf_hsm_id");
+ super.new(name, 32, build_coverage(UVM_CVR_ALL));
+ endfunction : new
+ extern virtual function void sample_values();
+ extern protected virtual function void sample(uvm_reg_data_t data,
+ uvm_reg_data_t byte_en,
+ bit is_read,
+ uvm_reg_map map);
+
+ virtual function void build();
+ this.hsm_id = new("hsm_id");
+ this.hsm_id.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(timer2_restart_bit_cg[bt]) timer2_restart_bit_cg[bt] = new();
+ foreach(hsm_id_bit_cg[bt]) hsm_id_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_WDT_TIMER2_CTRL
+ endclass : soc_ifc_reg__fuse_idevid_manuf_hsm_id
- // Reg - soc_ifc_reg::CPTRA_WDT_TIMER2_TIMEOUT_PERIOD
- class soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD extends uvm_reg;
+ // Reg - soc_ifc_reg::fuse_lms_revocation
+ class soc_ifc_reg__fuse_lms_revocation extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_bit_cg timer2_timeout_period_bit_cg[32];
- soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_fld_cg fld_cg;
- rand uvm_reg_field timer2_timeout_period;
+ soc_ifc_reg__fuse_lms_revocation_bit_cg lms_revocation_bit_cg[32];
+ soc_ifc_reg__fuse_lms_revocation_fld_cg fld_cg;
+ rand uvm_reg_field lms_revocation;
- function new(string name = "soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD");
+ function new(string name = "soc_ifc_reg__fuse_lms_revocation");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1119,29 +1799,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.timer2_timeout_period = new("timer2_timeout_period");
- this.timer2_timeout_period.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+ this.lms_revocation = new("lms_revocation");
+ this.lms_revocation.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(timer2_timeout_period_bit_cg[bt]) timer2_timeout_period_bit_cg[bt] = new();
+ foreach(lms_revocation_bit_cg[bt]) lms_revocation_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_WDT_TIMER2_TIMEOUT_PERIOD
+ endclass : soc_ifc_reg__fuse_lms_revocation
- // Reg - soc_ifc_reg::CPTRA_WDT_STATUS
- class soc_ifc_reg__CPTRA_WDT_STATUS extends uvm_reg;
+ // Reg - soc_ifc_reg::fuse_mldsa_revocation
+ class soc_ifc_reg__fuse_mldsa_revocation extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_WDT_STATUS_bit_cg t1_timeout_bit_cg[1];
- soc_ifc_reg__CPTRA_WDT_STATUS_bit_cg t2_timeout_bit_cg[1];
- soc_ifc_reg__CPTRA_WDT_STATUS_fld_cg fld_cg;
- rand uvm_reg_field t1_timeout;
- rand uvm_reg_field t2_timeout;
+ soc_ifc_reg__fuse_mldsa_revocation_bit_cg mldsa_revocation_bit_cg[4];
+ soc_ifc_reg__fuse_mldsa_revocation_fld_cg fld_cg;
+ rand uvm_reg_field mldsa_revocation;
- function new(string name = "soc_ifc_reg__CPTRA_WDT_STATUS");
+ function new(string name = "soc_ifc_reg__fuse_mldsa_revocation");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1151,30 +1829,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.t1_timeout = new("t1_timeout");
- this.t1_timeout.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
- this.t2_timeout = new("t2_timeout");
- this.t2_timeout.configure(this, 1, 1, "RW", 1, 'h0, 1, 1, 0);
+ this.mldsa_revocation = new("mldsa_revocation");
+ this.mldsa_revocation.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(t1_timeout_bit_cg[bt]) t1_timeout_bit_cg[bt] = new();
- foreach(t2_timeout_bit_cg[bt]) t2_timeout_bit_cg[bt] = new();
+ foreach(mldsa_revocation_bit_cg[bt]) mldsa_revocation_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_WDT_STATUS
+ endclass : soc_ifc_reg__fuse_mldsa_revocation
- // Reg - soc_ifc_reg::CPTRA_FUSE_VALID_AXI_USER
- class soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER extends uvm_reg;
+ // Reg - soc_ifc_reg::fuse_soc_stepping_id
+ class soc_ifc_reg__fuse_soc_stepping_id extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_bit_cg AXI_USER_bit_cg[32];
- soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER_fld_cg fld_cg;
- rand uvm_reg_field AXI_USER;
+ soc_ifc_reg__fuse_soc_stepping_id_bit_cg soc_stepping_id_bit_cg[16];
+ soc_ifc_reg__fuse_soc_stepping_id_fld_cg fld_cg;
+ rand uvm_reg_field soc_stepping_id;
- function new(string name = "soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER");
+ function new(string name = "soc_ifc_reg__fuse_soc_stepping_id");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1184,27 +1859,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.AXI_USER = new("AXI_USER");
- this.AXI_USER.configure(this, 32, 0, "RW", 0, 'hffffffff, 1, 1, 0);
+ this.soc_stepping_id = new("soc_stepping_id");
+ this.soc_stepping_id.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(AXI_USER_bit_cg[bt]) AXI_USER_bit_cg[bt] = new();
+ foreach(soc_stepping_id_bit_cg[bt]) soc_stepping_id_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_FUSE_VALID_AXI_USER
+ endclass : soc_ifc_reg__fuse_soc_stepping_id
- // Reg - soc_ifc_reg::CPTRA_FUSE_AXI_USER_LOCK
- class soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK extends uvm_reg;
+ // Reg - soc_ifc_reg::fuse_manuf_dbg_unlock_token
+ class soc_ifc_reg__fuse_manuf_dbg_unlock_token extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_bit_cg LOCK_bit_cg[1];
- soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK_fld_cg fld_cg;
- rand uvm_reg_field LOCK;
+ soc_ifc_reg__fuse_manuf_dbg_unlock_token_bit_cg token_bit_cg[32];
+ soc_ifc_reg__fuse_manuf_dbg_unlock_token_fld_cg fld_cg;
+ rand uvm_reg_field token;
- function new(string name = "soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK");
+ function new(string name = "soc_ifc_reg__fuse_manuf_dbg_unlock_token");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1214,27 +1889,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.LOCK = new("LOCK");
- this.LOCK.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.token = new("token");
+ this.token.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(LOCK_bit_cg[bt]) LOCK_bit_cg[bt] = new();
+ foreach(token_bit_cg[bt]) token_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_FUSE_AXI_USER_LOCK
+ endclass : soc_ifc_reg__fuse_manuf_dbg_unlock_token
- // Reg - soc_ifc_reg::CPTRA_WDT_CFG
- class soc_ifc_reg__CPTRA_WDT_CFG extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_CALIPTRA_BASE_ADDR_L
+ class soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_WDT_CFG_bit_cg TIMEOUT_bit_cg[32];
- soc_ifc_reg__CPTRA_WDT_CFG_fld_cg fld_cg;
- rand uvm_reg_field TIMEOUT;
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L_bit_cg addr_l_bit_cg[32];
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L_fld_cg fld_cg;
+ rand uvm_reg_field addr_l;
- function new(string name = "soc_ifc_reg__CPTRA_WDT_CFG");
+ function new(string name = "soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1244,29 +1919,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.TIMEOUT = new("TIMEOUT");
- this.TIMEOUT.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_l = new("addr_l");
+ this.addr_l.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(TIMEOUT_bit_cg[bt]) TIMEOUT_bit_cg[bt] = new();
+ foreach(addr_l_bit_cg[bt]) addr_l_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_WDT_CFG
+ endclass : soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L
- // Reg - soc_ifc_reg::CPTRA_iTRNG_ENTROPY_CONFIG_0
- class soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_CALIPTRA_BASE_ADDR_H
+ class soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_bit_cg low_threshold_bit_cg[16];
- soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_bit_cg high_threshold_bit_cg[16];
- soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0_fld_cg fld_cg;
- rand uvm_reg_field low_threshold;
- rand uvm_reg_field high_threshold;
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H_bit_cg addr_h_bit_cg[32];
+ soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H_fld_cg fld_cg;
+ rand uvm_reg_field addr_h;
- function new(string name = "soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0");
+ function new(string name = "soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1276,32 +1949,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.low_threshold = new("low_threshold");
- this.low_threshold.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
- this.high_threshold = new("high_threshold");
- this.high_threshold.configure(this, 16, 16, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_h = new("addr_h");
+ this.addr_h.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(low_threshold_bit_cg[bt]) low_threshold_bit_cg[bt] = new();
- foreach(high_threshold_bit_cg[bt]) high_threshold_bit_cg[bt] = new();
+ foreach(addr_h_bit_cg[bt]) addr_h_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0
+ endclass : soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H
- // Reg - soc_ifc_reg::CPTRA_iTRNG_ENTROPY_CONFIG_1
- class soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_MCI_BASE_ADDR_L
+ class soc_ifc_reg__SS_MCI_BASE_ADDR_L extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_bit_cg repetition_count_bit_cg[16];
- soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_bit_cg RSVD_bit_cg[16];
- soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1_fld_cg fld_cg;
- rand uvm_reg_field repetition_count;
- rand uvm_reg_field RSVD;
+ soc_ifc_reg__SS_MCI_BASE_ADDR_L_bit_cg addr_l_bit_cg[32];
+ soc_ifc_reg__SS_MCI_BASE_ADDR_L_fld_cg fld_cg;
+ rand uvm_reg_field addr_l;
- function new(string name = "soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1");
+ function new(string name = "soc_ifc_reg__SS_MCI_BASE_ADDR_L");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1311,30 +1979,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.repetition_count = new("repetition_count");
- this.repetition_count.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
- this.RSVD = new("RSVD");
- this.RSVD.configure(this, 16, 16, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_l = new("addr_l");
+ this.addr_l.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(repetition_count_bit_cg[bt]) repetition_count_bit_cg[bt] = new();
- foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
+ foreach(addr_l_bit_cg[bt]) addr_l_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1
+ endclass : soc_ifc_reg__SS_MCI_BASE_ADDR_L
- // Reg - soc_ifc_reg::CPTRA_RSVD_REG
- class soc_ifc_reg__CPTRA_RSVD_REG extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_MCI_BASE_ADDR_H
+ class soc_ifc_reg__SS_MCI_BASE_ADDR_H extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__CPTRA_RSVD_REG_bit_cg RSVD_bit_cg[32];
- soc_ifc_reg__CPTRA_RSVD_REG_fld_cg fld_cg;
- rand uvm_reg_field RSVD;
+ soc_ifc_reg__SS_MCI_BASE_ADDR_H_bit_cg addr_h_bit_cg[32];
+ soc_ifc_reg__SS_MCI_BASE_ADDR_H_fld_cg fld_cg;
+ rand uvm_reg_field addr_h;
- function new(string name = "soc_ifc_reg__CPTRA_RSVD_REG");
+ function new(string name = "soc_ifc_reg__SS_MCI_BASE_ADDR_H");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1344,27 +2009,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.RSVD = new("RSVD");
- this.RSVD.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_h = new("addr_h");
+ this.addr_h.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
+ foreach(addr_h_bit_cg[bt]) addr_h_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__CPTRA_RSVD_REG
+ endclass : soc_ifc_reg__SS_MCI_BASE_ADDR_H
- // Reg - soc_ifc_reg::fuse_uds_seed
- class soc_ifc_reg__fuse_uds_seed extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_RECOVERY_IFC_BASE_ADDR_L
+ class soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_uds_seed_bit_cg seed_bit_cg[32];
- soc_ifc_reg__fuse_uds_seed_fld_cg fld_cg;
- rand uvm_reg_field seed;
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L_bit_cg addr_l_bit_cg[32];
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L_fld_cg fld_cg;
+ rand uvm_reg_field addr_l;
- function new(string name = "soc_ifc_reg__fuse_uds_seed");
+ function new(string name = "soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1374,27 +2039,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.seed = new("seed");
- this.seed.configure(this, 32, 0, "WO1", 1, 'h0, 1, 1, 0);
+ this.addr_l = new("addr_l");
+ this.addr_l.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(seed_bit_cg[bt]) seed_bit_cg[bt] = new();
+ foreach(addr_l_bit_cg[bt]) addr_l_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_uds_seed
+ endclass : soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L
- // Reg - soc_ifc_reg::fuse_field_entropy
- class soc_ifc_reg__fuse_field_entropy extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_RECOVERY_IFC_BASE_ADDR_H
+ class soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_field_entropy_bit_cg seed_bit_cg[32];
- soc_ifc_reg__fuse_field_entropy_fld_cg fld_cg;
- rand uvm_reg_field seed;
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H_bit_cg addr_h_bit_cg[32];
+ soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H_fld_cg fld_cg;
+ rand uvm_reg_field addr_h;
- function new(string name = "soc_ifc_reg__fuse_field_entropy");
+ function new(string name = "soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1404,27 +2069,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.seed = new("seed");
- this.seed.configure(this, 32, 0, "WO1", 1, 'h0, 1, 1, 0);
+ this.addr_h = new("addr_h");
+ this.addr_h.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(seed_bit_cg[bt]) seed_bit_cg[bt] = new();
+ foreach(addr_h_bit_cg[bt]) addr_h_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_field_entropy
+ endclass : soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H
- // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash
- class soc_ifc_reg__fuse_key_manifest_pk_hash extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_OTP_FC_BASE_ADDR_L
+ class soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_key_manifest_pk_hash_bit_cg hash_bit_cg[32];
- soc_ifc_reg__fuse_key_manifest_pk_hash_fld_cg fld_cg;
- rand uvm_reg_field hash;
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L_bit_cg addr_l_bit_cg[32];
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L_fld_cg fld_cg;
+ rand uvm_reg_field addr_l;
- function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash");
+ function new(string name = "soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1434,27 +2099,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.hash = new("hash");
- this.hash.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_l = new("addr_l");
+ this.addr_l.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(hash_bit_cg[bt]) hash_bit_cg[bt] = new();
+ foreach(addr_l_bit_cg[bt]) addr_l_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_key_manifest_pk_hash
+ endclass : soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L
- // Reg - soc_ifc_reg::fuse_key_manifest_pk_hash_mask
- class soc_ifc_reg__fuse_key_manifest_pk_hash_mask extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_OTP_FC_BASE_ADDR_H
+ class soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_key_manifest_pk_hash_mask_bit_cg mask_bit_cg[4];
- soc_ifc_reg__fuse_key_manifest_pk_hash_mask_fld_cg fld_cg;
- rand uvm_reg_field mask;
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H_bit_cg addr_h_bit_cg[32];
+ soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H_fld_cg fld_cg;
+ rand uvm_reg_field addr_h;
- function new(string name = "soc_ifc_reg__fuse_key_manifest_pk_hash_mask");
+ function new(string name = "soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1464,27 +2129,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.mask = new("mask");
- this.mask.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_h = new("addr_h");
+ this.addr_h.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(mask_bit_cg[bt]) mask_bit_cg[bt] = new();
+ foreach(addr_h_bit_cg[bt]) addr_h_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_key_manifest_pk_hash_mask
+ endclass : soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H
- // Reg - soc_ifc_reg::fuse_owner_pk_hash
- class soc_ifc_reg__fuse_owner_pk_hash extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_UDS_SEED_BASE_ADDR_L
+ class soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_owner_pk_hash_bit_cg hash_bit_cg[32];
- soc_ifc_reg__fuse_owner_pk_hash_fld_cg fld_cg;
- rand uvm_reg_field hash;
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L_bit_cg addr_l_bit_cg[32];
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L_fld_cg fld_cg;
+ rand uvm_reg_field addr_l;
- function new(string name = "soc_ifc_reg__fuse_owner_pk_hash");
+ function new(string name = "soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1494,27 +2159,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.hash = new("hash");
- this.hash.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_l = new("addr_l");
+ this.addr_l.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(hash_bit_cg[bt]) hash_bit_cg[bt] = new();
+ foreach(addr_l_bit_cg[bt]) addr_l_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_owner_pk_hash
+ endclass : soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L
- // Reg - soc_ifc_reg::fuse_fmc_key_manifest_svn
- class soc_ifc_reg__fuse_fmc_key_manifest_svn extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_UDS_SEED_BASE_ADDR_H
+ class soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_fmc_key_manifest_svn_bit_cg svn_bit_cg[32];
- soc_ifc_reg__fuse_fmc_key_manifest_svn_fld_cg fld_cg;
- rand uvm_reg_field svn;
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H_bit_cg addr_h_bit_cg[32];
+ soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H_fld_cg fld_cg;
+ rand uvm_reg_field addr_h;
- function new(string name = "soc_ifc_reg__fuse_fmc_key_manifest_svn");
+ function new(string name = "soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1524,27 +2189,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.svn = new("svn");
- this.svn.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.addr_h = new("addr_h");
+ this.addr_h.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new();
+ foreach(addr_h_bit_cg[bt]) addr_h_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_fmc_key_manifest_svn
+ endclass : soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H
- // Reg - soc_ifc_reg::fuse_runtime_svn
- class soc_ifc_reg__fuse_runtime_svn extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET
+ class soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_runtime_svn_bit_cg svn_bit_cg[32];
- soc_ifc_reg__fuse_runtime_svn_fld_cg fld_cg;
- rand uvm_reg_field svn;
+ soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET_bit_cg offset_bit_cg[32];
+ soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET_fld_cg fld_cg;
+ rand uvm_reg_field offset;
- function new(string name = "soc_ifc_reg__fuse_runtime_svn");
+ function new(string name = "soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1554,27 +2219,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.svn = new("svn");
- this.svn.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.offset = new("offset");
+ this.offset.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(svn_bit_cg[bt]) svn_bit_cg[bt] = new();
+ foreach(offset_bit_cg[bt]) offset_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_runtime_svn
+ endclass : soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET
- // Reg - soc_ifc_reg::fuse_anti_rollback_disable
- class soc_ifc_reg__fuse_anti_rollback_disable extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES
+ class soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_anti_rollback_disable_bit_cg dis_bit_cg[1];
- soc_ifc_reg__fuse_anti_rollback_disable_fld_cg fld_cg;
- rand uvm_reg_field dis;
+ soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES_bit_cg num_bit_cg[32];
+ soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES_fld_cg fld_cg;
+ rand uvm_reg_field num;
- function new(string name = "soc_ifc_reg__fuse_anti_rollback_disable");
+ function new(string name = "soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1584,27 +2249,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.dis = new("dis");
- this.dis.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.num = new("num");
+ this.num.configure(this, 32, 0, "RW", 1, 'h8, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(dis_bit_cg[bt]) dis_bit_cg[bt] = new();
+ foreach(num_bit_cg[bt]) num_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_anti_rollback_disable
+ endclass : soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES
- // Reg - soc_ifc_reg::fuse_idevid_cert_attr
- class soc_ifc_reg__fuse_idevid_cert_attr extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_DEBUG_INTENT
+ class soc_ifc_reg__SS_DEBUG_INTENT extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_idevid_cert_attr_bit_cg cert_bit_cg[32];
- soc_ifc_reg__fuse_idevid_cert_attr_fld_cg fld_cg;
- rand uvm_reg_field cert;
+ soc_ifc_reg__SS_DEBUG_INTENT_bit_cg debug_intent_bit_cg[1];
+ soc_ifc_reg__SS_DEBUG_INTENT_fld_cg fld_cg;
+ rand uvm_reg_field debug_intent;
- function new(string name = "soc_ifc_reg__fuse_idevid_cert_attr");
+ function new(string name = "soc_ifc_reg__SS_DEBUG_INTENT");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1614,27 +2279,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.cert = new("cert");
- this.cert.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.debug_intent = new("debug_intent");
+ this.debug_intent.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(cert_bit_cg[bt]) cert_bit_cg[bt] = new();
+ foreach(debug_intent_bit_cg[bt]) debug_intent_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_idevid_cert_attr
+ endclass : soc_ifc_reg__SS_DEBUG_INTENT
- // Reg - soc_ifc_reg::fuse_idevid_manuf_hsm_id
- class soc_ifc_reg__fuse_idevid_manuf_hsm_id extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_STRAP_GENERIC
+ class soc_ifc_reg__SS_STRAP_GENERIC extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_idevid_manuf_hsm_id_bit_cg hsm_id_bit_cg[32];
- soc_ifc_reg__fuse_idevid_manuf_hsm_id_fld_cg fld_cg;
- rand uvm_reg_field hsm_id;
+ soc_ifc_reg__SS_STRAP_GENERIC_bit_cg data_bit_cg[32];
+ soc_ifc_reg__SS_STRAP_GENERIC_fld_cg fld_cg;
+ rand uvm_reg_field data;
- function new(string name = "soc_ifc_reg__fuse_idevid_manuf_hsm_id");
+ function new(string name = "soc_ifc_reg__SS_STRAP_GENERIC");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1644,27 +2309,33 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.hsm_id = new("hsm_id");
- this.hsm_id.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.data = new("data");
+ this.data.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(hsm_id_bit_cg[bt]) hsm_id_bit_cg[bt] = new();
+ foreach(data_bit_cg[bt]) data_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_idevid_manuf_hsm_id
+ endclass : soc_ifc_reg__SS_STRAP_GENERIC
- // Reg - soc_ifc_reg::fuse_life_cycle
- class soc_ifc_reg__fuse_life_cycle extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_DBG_MANUF_SERVICE_REG_REQ
+ class soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_life_cycle_bit_cg life_cycle_bit_cg[2];
- soc_ifc_reg__fuse_life_cycle_fld_cg fld_cg;
- rand uvm_reg_field life_cycle;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ_bit_cg MANUF_DBG_UNLOCK_REQ_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ_bit_cg PROD_DBG_UNLOCK_REQ_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ_bit_cg UDS_PROGRAM_REQ_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ_bit_cg RSVD_bit_cg[29];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ_fld_cg fld_cg;
+ rand uvm_reg_field MANUF_DBG_UNLOCK_REQ;
+ rand uvm_reg_field PROD_DBG_UNLOCK_REQ;
+ rand uvm_reg_field UDS_PROGRAM_REQ;
+ rand uvm_reg_field RSVD;
- function new(string name = "soc_ifc_reg__fuse_life_cycle");
+ function new(string name = "soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1674,27 +2345,54 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.life_cycle = new("life_cycle");
- this.life_cycle.configure(this, 2, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.MANUF_DBG_UNLOCK_REQ = new("MANUF_DBG_UNLOCK_REQ");
+ this.MANUF_DBG_UNLOCK_REQ.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
+ this.PROD_DBG_UNLOCK_REQ = new("PROD_DBG_UNLOCK_REQ");
+ this.PROD_DBG_UNLOCK_REQ.configure(this, 1, 1, "RW", 1, 'h0, 1, 1, 0);
+ this.UDS_PROGRAM_REQ = new("UDS_PROGRAM_REQ");
+ this.UDS_PROGRAM_REQ.configure(this, 1, 2, "RW", 1, 'h0, 1, 1, 0);
+ this.RSVD = new("RSVD");
+ this.RSVD.configure(this, 29, 3, "RO", 1, 'h0, 0, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(life_cycle_bit_cg[bt]) life_cycle_bit_cg[bt] = new();
+ foreach(MANUF_DBG_UNLOCK_REQ_bit_cg[bt]) MANUF_DBG_UNLOCK_REQ_bit_cg[bt] = new();
+ foreach(PROD_DBG_UNLOCK_REQ_bit_cg[bt]) PROD_DBG_UNLOCK_REQ_bit_cg[bt] = new();
+ foreach(UDS_PROGRAM_REQ_bit_cg[bt]) UDS_PROGRAM_REQ_bit_cg[bt] = new();
+ foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_life_cycle
+ endclass : soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ
- // Reg - soc_ifc_reg::fuse_lms_verify
- class soc_ifc_reg__fuse_lms_verify extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_DBG_MANUF_SERVICE_REG_RSP
+ class soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_lms_verify_bit_cg lms_verify_bit_cg[1];
- soc_ifc_reg__fuse_lms_verify_fld_cg fld_cg;
- rand uvm_reg_field lms_verify;
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg MANUF_DBG_UNLOCK_SUCCESS_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg MANUF_DBG_UNLOCK_FAIL_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg MANUF_DBG_UNLOCK_IN_PROGRESS_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg PROD_DBG_UNLOCK_SUCCESS_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg PROD_DBG_UNLOCK_FAIL_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg PROD_DBG_UNLOCK_IN_PROGRESS_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg UDS_PROGRAM_SUCCESS_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg UDS_PROGRAM_FAIL_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg UDS_PROGRAM_IN_PROGRESS_bit_cg[1];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_bit_cg RSVD_bit_cg[23];
+ soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP_fld_cg fld_cg;
+ rand uvm_reg_field MANUF_DBG_UNLOCK_SUCCESS;
+ rand uvm_reg_field MANUF_DBG_UNLOCK_FAIL;
+ rand uvm_reg_field MANUF_DBG_UNLOCK_IN_PROGRESS;
+ rand uvm_reg_field PROD_DBG_UNLOCK_SUCCESS;
+ rand uvm_reg_field PROD_DBG_UNLOCK_FAIL;
+ rand uvm_reg_field PROD_DBG_UNLOCK_IN_PROGRESS;
+ rand uvm_reg_field UDS_PROGRAM_SUCCESS;
+ rand uvm_reg_field UDS_PROGRAM_FAIL;
+ rand uvm_reg_field UDS_PROGRAM_IN_PROGRESS;
+ rand uvm_reg_field RSVD;
- function new(string name = "soc_ifc_reg__fuse_lms_verify");
+ function new(string name = "soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1704,27 +2402,54 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.lms_verify = new("lms_verify");
- this.lms_verify.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.MANUF_DBG_UNLOCK_SUCCESS = new("MANUF_DBG_UNLOCK_SUCCESS");
+ this.MANUF_DBG_UNLOCK_SUCCESS.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0);
+ this.MANUF_DBG_UNLOCK_FAIL = new("MANUF_DBG_UNLOCK_FAIL");
+ this.MANUF_DBG_UNLOCK_FAIL.configure(this, 1, 1, "RW", 1, 'h0, 1, 1, 0);
+ this.MANUF_DBG_UNLOCK_IN_PROGRESS = new("MANUF_DBG_UNLOCK_IN_PROGRESS");
+ this.MANUF_DBG_UNLOCK_IN_PROGRESS.configure(this, 1, 2, "RW", 1, 'h0, 1, 1, 0);
+ this.PROD_DBG_UNLOCK_SUCCESS = new("PROD_DBG_UNLOCK_SUCCESS");
+ this.PROD_DBG_UNLOCK_SUCCESS.configure(this, 1, 3, "RW", 1, 'h0, 1, 1, 0);
+ this.PROD_DBG_UNLOCK_FAIL = new("PROD_DBG_UNLOCK_FAIL");
+ this.PROD_DBG_UNLOCK_FAIL.configure(this, 1, 4, "RW", 1, 'h0, 1, 1, 0);
+ this.PROD_DBG_UNLOCK_IN_PROGRESS = new("PROD_DBG_UNLOCK_IN_PROGRESS");
+ this.PROD_DBG_UNLOCK_IN_PROGRESS.configure(this, 1, 5, "RW", 1, 'h0, 1, 1, 0);
+ this.UDS_PROGRAM_SUCCESS = new("UDS_PROGRAM_SUCCESS");
+ this.UDS_PROGRAM_SUCCESS.configure(this, 1, 6, "RW", 1, 'h0, 1, 1, 0);
+ this.UDS_PROGRAM_FAIL = new("UDS_PROGRAM_FAIL");
+ this.UDS_PROGRAM_FAIL.configure(this, 1, 7, "RW", 1, 'h0, 1, 1, 0);
+ this.UDS_PROGRAM_IN_PROGRESS = new("UDS_PROGRAM_IN_PROGRESS");
+ this.UDS_PROGRAM_IN_PROGRESS.configure(this, 1, 8, "RW", 1, 'h0, 1, 1, 0);
+ this.RSVD = new("RSVD");
+ this.RSVD.configure(this, 23, 9, "RO", 1, 'h0, 0, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(lms_verify_bit_cg[bt]) lms_verify_bit_cg[bt] = new();
+ foreach(MANUF_DBG_UNLOCK_SUCCESS_bit_cg[bt]) MANUF_DBG_UNLOCK_SUCCESS_bit_cg[bt] = new();
+ foreach(MANUF_DBG_UNLOCK_FAIL_bit_cg[bt]) MANUF_DBG_UNLOCK_FAIL_bit_cg[bt] = new();
+ foreach(MANUF_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt]) MANUF_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt] = new();
+ foreach(PROD_DBG_UNLOCK_SUCCESS_bit_cg[bt]) PROD_DBG_UNLOCK_SUCCESS_bit_cg[bt] = new();
+ foreach(PROD_DBG_UNLOCK_FAIL_bit_cg[bt]) PROD_DBG_UNLOCK_FAIL_bit_cg[bt] = new();
+ foreach(PROD_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt]) PROD_DBG_UNLOCK_IN_PROGRESS_bit_cg[bt] = new();
+ foreach(UDS_PROGRAM_SUCCESS_bit_cg[bt]) UDS_PROGRAM_SUCCESS_bit_cg[bt] = new();
+ foreach(UDS_PROGRAM_FAIL_bit_cg[bt]) UDS_PROGRAM_FAIL_bit_cg[bt] = new();
+ foreach(UDS_PROGRAM_IN_PROGRESS_bit_cg[bt]) UDS_PROGRAM_IN_PROGRESS_bit_cg[bt] = new();
+ foreach(RSVD_bit_cg[bt]) RSVD_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_lms_verify
+ endclass : soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP
- // Reg - soc_ifc_reg::fuse_lms_revocation
- class soc_ifc_reg__fuse_lms_revocation extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_SOC_DBG_UNLOCK_LEVEL
+ class soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_lms_revocation_bit_cg lms_revocation_bit_cg[32];
- soc_ifc_reg__fuse_lms_revocation_fld_cg fld_cg;
- rand uvm_reg_field lms_revocation;
+ soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL_bit_cg LEVEL_bit_cg[32];
+ soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL_fld_cg fld_cg;
+ rand uvm_reg_field LEVEL;
- function new(string name = "soc_ifc_reg__fuse_lms_revocation");
+ function new(string name = "soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1734,27 +2459,27 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.lms_revocation = new("lms_revocation");
- this.lms_revocation.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.LEVEL = new("LEVEL");
+ this.LEVEL.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(lms_revocation_bit_cg[bt]) lms_revocation_bit_cg[bt] = new();
+ foreach(LEVEL_bit_cg[bt]) LEVEL_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_lms_revocation
+ endclass : soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL
- // Reg - soc_ifc_reg::fuse_soc_stepping_id
- class soc_ifc_reg__fuse_soc_stepping_id extends uvm_reg;
+ // Reg - soc_ifc_reg::SS_GENERIC_FW_EXEC_CTRL
+ class soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL extends uvm_reg;
protected uvm_reg_data_t m_current;
protected uvm_reg_data_t m_data;
protected bit m_is_read;
- soc_ifc_reg__fuse_soc_stepping_id_bit_cg soc_stepping_id_bit_cg[16];
- soc_ifc_reg__fuse_soc_stepping_id_fld_cg fld_cg;
- rand uvm_reg_field soc_stepping_id;
+ soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL_bit_cg go_bit_cg[32];
+ soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL_fld_cg fld_cg;
+ rand uvm_reg_field go;
- function new(string name = "soc_ifc_reg__fuse_soc_stepping_id");
+ function new(string name = "soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL");
super.new(name, 32, build_coverage(UVM_CVR_ALL));
endfunction : new
extern virtual function void sample_values();
@@ -1764,15 +2489,15 @@ package soc_ifc_reg_uvm;
uvm_reg_map map);
virtual function void build();
- this.soc_stepping_id = new("soc_stepping_id");
- this.soc_stepping_id.configure(this, 16, 0, "RW", 0, 'h0, 1, 1, 0);
+ this.go = new("go");
+ this.go.configure(this, 32, 0, "RW", 0, 'h0, 1, 1, 0);
if (has_coverage(UVM_CVR_REG_BITS)) begin
- foreach(soc_stepping_id_bit_cg[bt]) soc_stepping_id_bit_cg[bt] = new();
+ foreach(go_bit_cg[bt]) go_bit_cg[bt] = new();
end
if (has_coverage(UVM_CVR_FIELD_VALS))
fld_cg = new();
endfunction : build
- endclass : soc_ifc_reg__fuse_soc_stepping_id
+ endclass : soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL
// Reg - soc_ifc_reg::internal_obf_key
class soc_ifc_reg__internal_obf_key extends uvm_reg;
@@ -3761,20 +4486,42 @@ package soc_ifc_reg_uvm;
rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_0 CPTRA_iTRNG_ENTROPY_CONFIG_0;
rand soc_ifc_reg__CPTRA_iTRNG_ENTROPY_CONFIG_1 CPTRA_iTRNG_ENTROPY_CONFIG_1;
rand soc_ifc_reg__CPTRA_RSVD_REG CPTRA_RSVD_REG[2];
+ rand soc_ifc_reg__CPTRA_HW_CAPABILITIES CPTRA_HW_CAPABILITIES;
+ rand soc_ifc_reg__CPTRA_FW_CAPABILITIES CPTRA_FW_CAPABILITIES;
+ rand soc_ifc_reg__CPTRA_CAP_LOCK CPTRA_CAP_LOCK;
+ rand soc_ifc_reg__CPTRA_OWNER_PK_HASH CPTRA_OWNER_PK_HASH[12];
+ rand soc_ifc_reg__CPTRA_OWNER_PK_HASH_LOCK CPTRA_OWNER_PK_HASH_LOCK;
rand soc_ifc_reg__fuse_uds_seed fuse_uds_seed[16];
rand soc_ifc_reg__fuse_field_entropy fuse_field_entropy[8];
rand soc_ifc_reg__fuse_key_manifest_pk_hash fuse_key_manifest_pk_hash[12];
- rand soc_ifc_reg__fuse_key_manifest_pk_hash_mask fuse_key_manifest_pk_hash_mask;
- rand soc_ifc_reg__fuse_owner_pk_hash fuse_owner_pk_hash[12];
+ rand soc_ifc_reg__fuse_key_manifest_pk_hash_mask fuse_key_manifest_pk_hash_mask[8];
rand soc_ifc_reg__fuse_fmc_key_manifest_svn fuse_fmc_key_manifest_svn;
rand soc_ifc_reg__fuse_runtime_svn fuse_runtime_svn[4];
rand soc_ifc_reg__fuse_anti_rollback_disable fuse_anti_rollback_disable;
rand soc_ifc_reg__fuse_idevid_cert_attr fuse_idevid_cert_attr[24];
rand soc_ifc_reg__fuse_idevid_manuf_hsm_id fuse_idevid_manuf_hsm_id[4];
- rand soc_ifc_reg__fuse_life_cycle fuse_life_cycle;
- rand soc_ifc_reg__fuse_lms_verify fuse_lms_verify;
rand soc_ifc_reg__fuse_lms_revocation fuse_lms_revocation;
+ rand soc_ifc_reg__fuse_mldsa_revocation fuse_mldsa_revocation;
rand soc_ifc_reg__fuse_soc_stepping_id fuse_soc_stepping_id;
+ rand soc_ifc_reg__fuse_manuf_dbg_unlock_token fuse_manuf_dbg_unlock_token[4];
+ rand soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_L SS_CALIPTRA_BASE_ADDR_L;
+ rand soc_ifc_reg__SS_CALIPTRA_BASE_ADDR_H SS_CALIPTRA_BASE_ADDR_H;
+ rand soc_ifc_reg__SS_MCI_BASE_ADDR_L SS_MCI_BASE_ADDR_L;
+ rand soc_ifc_reg__SS_MCI_BASE_ADDR_H SS_MCI_BASE_ADDR_H;
+ rand soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_L SS_RECOVERY_IFC_BASE_ADDR_L;
+ rand soc_ifc_reg__SS_RECOVERY_IFC_BASE_ADDR_H SS_RECOVERY_IFC_BASE_ADDR_H;
+ rand soc_ifc_reg__SS_OTP_FC_BASE_ADDR_L SS_OTP_FC_BASE_ADDR_L;
+ rand soc_ifc_reg__SS_OTP_FC_BASE_ADDR_H SS_OTP_FC_BASE_ADDR_H;
+ rand soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_L SS_UDS_SEED_BASE_ADDR_L;
+ rand soc_ifc_reg__SS_UDS_SEED_BASE_ADDR_H SS_UDS_SEED_BASE_ADDR_H;
+ rand soc_ifc_reg__SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET;
+ rand soc_ifc_reg__SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES;
+ rand soc_ifc_reg__SS_DEBUG_INTENT SS_DEBUG_INTENT;
+ rand soc_ifc_reg__SS_STRAP_GENERIC SS_STRAP_GENERIC[4];
+ rand soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_REQ SS_DBG_MANUF_SERVICE_REG_REQ;
+ rand soc_ifc_reg__SS_DBG_MANUF_SERVICE_REG_RSP SS_DBG_MANUF_SERVICE_REG_RSP;
+ rand soc_ifc_reg__SS_SOC_DBG_UNLOCK_LEVEL SS_SOC_DBG_UNLOCK_LEVEL[2];
+ rand soc_ifc_reg__SS_GENERIC_FW_EXEC_CTRL SS_GENERIC_FW_EXEC_CTRL[4];
rand soc_ifc_reg__internal_obf_key internal_obf_key[8];
rand soc_ifc_reg__internal_iccm_lock internal_iccm_lock;
rand soc_ifc_reg__internal_fw_update_reset internal_fw_update_reset;
@@ -4023,6 +4770,33 @@ package soc_ifc_reg_uvm;
this.CPTRA_RSVD_REG[i0].build();
this.default_map.add_reg(this.CPTRA_RSVD_REG[i0], 'h120 + i0*'h4);
end
+ this.CPTRA_HW_CAPABILITIES = new("CPTRA_HW_CAPABILITIES");
+ this.CPTRA_HW_CAPABILITIES.configure(this);
+
+ this.CPTRA_HW_CAPABILITIES.build();
+ this.default_map.add_reg(this.CPTRA_HW_CAPABILITIES, 'h128);
+ this.CPTRA_FW_CAPABILITIES = new("CPTRA_FW_CAPABILITIES");
+ this.CPTRA_FW_CAPABILITIES.configure(this);
+
+ this.CPTRA_FW_CAPABILITIES.build();
+ this.default_map.add_reg(this.CPTRA_FW_CAPABILITIES, 'h12c);
+ this.CPTRA_CAP_LOCK = new("CPTRA_CAP_LOCK");
+ this.CPTRA_CAP_LOCK.configure(this);
+
+ this.CPTRA_CAP_LOCK.build();
+ this.default_map.add_reg(this.CPTRA_CAP_LOCK, 'h130);
+ foreach(this.CPTRA_OWNER_PK_HASH[i0]) begin
+ this.CPTRA_OWNER_PK_HASH[i0] = new($sformatf("CPTRA_OWNER_PK_HASH[%0d]", i0));
+ this.CPTRA_OWNER_PK_HASH[i0].configure(this);
+
+ this.CPTRA_OWNER_PK_HASH[i0].build();
+ this.default_map.add_reg(this.CPTRA_OWNER_PK_HASH[i0], 'h140 + i0*'h4);
+ end
+ this.CPTRA_OWNER_PK_HASH_LOCK = new("CPTRA_OWNER_PK_HASH_LOCK");
+ this.CPTRA_OWNER_PK_HASH_LOCK.configure(this);
+
+ this.CPTRA_OWNER_PK_HASH_LOCK.build();
+ this.default_map.add_reg(this.CPTRA_OWNER_PK_HASH_LOCK, 'h170);
foreach(this.fuse_uds_seed[i0]) begin
this.fuse_uds_seed[i0] = new($sformatf("fuse_uds_seed[%0d]", i0));
this.fuse_uds_seed[i0].configure(this);
@@ -4044,69 +4818,162 @@ package soc_ifc_reg_uvm;
this.fuse_key_manifest_pk_hash[i0].build();
this.default_map.add_reg(this.fuse_key_manifest_pk_hash[i0], 'h260 + i0*'h4);
end
- this.fuse_key_manifest_pk_hash_mask = new("fuse_key_manifest_pk_hash_mask");
- this.fuse_key_manifest_pk_hash_mask.configure(this);
-
- this.fuse_key_manifest_pk_hash_mask.build();
- this.default_map.add_reg(this.fuse_key_manifest_pk_hash_mask, 'h290);
- foreach(this.fuse_owner_pk_hash[i0]) begin
- this.fuse_owner_pk_hash[i0] = new($sformatf("fuse_owner_pk_hash[%0d]", i0));
- this.fuse_owner_pk_hash[i0].configure(this);
+ foreach(this.fuse_key_manifest_pk_hash_mask[i0]) begin
+ this.fuse_key_manifest_pk_hash_mask[i0] = new($sformatf("fuse_key_manifest_pk_hash_mask[%0d]", i0));
+ this.fuse_key_manifest_pk_hash_mask[i0].configure(this);
- this.fuse_owner_pk_hash[i0].build();
- this.default_map.add_reg(this.fuse_owner_pk_hash[i0], 'h294 + i0*'h4);
+ this.fuse_key_manifest_pk_hash_mask[i0].build();
+ this.default_map.add_reg(this.fuse_key_manifest_pk_hash_mask[i0], 'h290 + i0*'h4);
end
this.fuse_fmc_key_manifest_svn = new("fuse_fmc_key_manifest_svn");
this.fuse_fmc_key_manifest_svn.configure(this);
this.fuse_fmc_key_manifest_svn.build();
- this.default_map.add_reg(this.fuse_fmc_key_manifest_svn, 'h2c4);
+ this.default_map.add_reg(this.fuse_fmc_key_manifest_svn, 'h2b4);
foreach(this.fuse_runtime_svn[i0]) begin
this.fuse_runtime_svn[i0] = new($sformatf("fuse_runtime_svn[%0d]", i0));
this.fuse_runtime_svn[i0].configure(this);
this.fuse_runtime_svn[i0].build();
- this.default_map.add_reg(this.fuse_runtime_svn[i0], 'h2c8 + i0*'h4);
+ this.default_map.add_reg(this.fuse_runtime_svn[i0], 'h2b8 + i0*'h4);
end
this.fuse_anti_rollback_disable = new("fuse_anti_rollback_disable");
this.fuse_anti_rollback_disable.configure(this);
this.fuse_anti_rollback_disable.build();
- this.default_map.add_reg(this.fuse_anti_rollback_disable, 'h2d8);
+ this.default_map.add_reg(this.fuse_anti_rollback_disable, 'h2c8);
foreach(this.fuse_idevid_cert_attr[i0]) begin
this.fuse_idevid_cert_attr[i0] = new($sformatf("fuse_idevid_cert_attr[%0d]", i0));
this.fuse_idevid_cert_attr[i0].configure(this);
this.fuse_idevid_cert_attr[i0].build();
- this.default_map.add_reg(this.fuse_idevid_cert_attr[i0], 'h2dc + i0*'h4);
+ this.default_map.add_reg(this.fuse_idevid_cert_attr[i0], 'h2cc + i0*'h4);
end
foreach(this.fuse_idevid_manuf_hsm_id[i0]) begin
this.fuse_idevid_manuf_hsm_id[i0] = new($sformatf("fuse_idevid_manuf_hsm_id[%0d]", i0));
this.fuse_idevid_manuf_hsm_id[i0].configure(this);
this.fuse_idevid_manuf_hsm_id[i0].build();
- this.default_map.add_reg(this.fuse_idevid_manuf_hsm_id[i0], 'h33c + i0*'h4);
+ this.default_map.add_reg(this.fuse_idevid_manuf_hsm_id[i0], 'h32c + i0*'h4);
end
- this.fuse_life_cycle = new("fuse_life_cycle");
- this.fuse_life_cycle.configure(this);
-
- this.fuse_life_cycle.build();
- this.default_map.add_reg(this.fuse_life_cycle, 'h34c);
- this.fuse_lms_verify = new("fuse_lms_verify");
- this.fuse_lms_verify.configure(this);
-
- this.fuse_lms_verify.build();
- this.default_map.add_reg(this.fuse_lms_verify, 'h350);
this.fuse_lms_revocation = new("fuse_lms_revocation");
this.fuse_lms_revocation.configure(this);
this.fuse_lms_revocation.build();
- this.default_map.add_reg(this.fuse_lms_revocation, 'h354);
+ this.default_map.add_reg(this.fuse_lms_revocation, 'h340);
+ this.fuse_mldsa_revocation = new("fuse_mldsa_revocation");
+ this.fuse_mldsa_revocation.configure(this);
+
+ this.fuse_mldsa_revocation.build();
+ this.default_map.add_reg(this.fuse_mldsa_revocation, 'h344);
this.fuse_soc_stepping_id = new("fuse_soc_stepping_id");
this.fuse_soc_stepping_id.configure(this);
this.fuse_soc_stepping_id.build();
- this.default_map.add_reg(this.fuse_soc_stepping_id, 'h358);
+ this.default_map.add_reg(this.fuse_soc_stepping_id, 'h348);
+ foreach(this.fuse_manuf_dbg_unlock_token[i0]) begin
+ this.fuse_manuf_dbg_unlock_token[i0] = new($sformatf("fuse_manuf_dbg_unlock_token[%0d]", i0));
+ this.fuse_manuf_dbg_unlock_token[i0].configure(this);
+
+ this.fuse_manuf_dbg_unlock_token[i0].build();
+ this.default_map.add_reg(this.fuse_manuf_dbg_unlock_token[i0], 'h34c + i0*'h4);
+ end
+ this.SS_CALIPTRA_BASE_ADDR_L = new("SS_CALIPTRA_BASE_ADDR_L");
+ this.SS_CALIPTRA_BASE_ADDR_L.configure(this);
+
+ this.SS_CALIPTRA_BASE_ADDR_L.build();
+ this.default_map.add_reg(this.SS_CALIPTRA_BASE_ADDR_L, 'h500);
+ this.SS_CALIPTRA_BASE_ADDR_H = new("SS_CALIPTRA_BASE_ADDR_H");
+ this.SS_CALIPTRA_BASE_ADDR_H.configure(this);
+
+ this.SS_CALIPTRA_BASE_ADDR_H.build();
+ this.default_map.add_reg(this.SS_CALIPTRA_BASE_ADDR_H, 'h504);
+ this.SS_MCI_BASE_ADDR_L = new("SS_MCI_BASE_ADDR_L");
+ this.SS_MCI_BASE_ADDR_L.configure(this);
+
+ this.SS_MCI_BASE_ADDR_L.build();
+ this.default_map.add_reg(this.SS_MCI_BASE_ADDR_L, 'h508);
+ this.SS_MCI_BASE_ADDR_H = new("SS_MCI_BASE_ADDR_H");
+ this.SS_MCI_BASE_ADDR_H.configure(this);
+
+ this.SS_MCI_BASE_ADDR_H.build();
+ this.default_map.add_reg(this.SS_MCI_BASE_ADDR_H, 'h50c);
+ this.SS_RECOVERY_IFC_BASE_ADDR_L = new("SS_RECOVERY_IFC_BASE_ADDR_L");
+ this.SS_RECOVERY_IFC_BASE_ADDR_L.configure(this);
+
+ this.SS_RECOVERY_IFC_BASE_ADDR_L.build();
+ this.default_map.add_reg(this.SS_RECOVERY_IFC_BASE_ADDR_L, 'h510);
+ this.SS_RECOVERY_IFC_BASE_ADDR_H = new("SS_RECOVERY_IFC_BASE_ADDR_H");
+ this.SS_RECOVERY_IFC_BASE_ADDR_H.configure(this);
+
+ this.SS_RECOVERY_IFC_BASE_ADDR_H.build();
+ this.default_map.add_reg(this.SS_RECOVERY_IFC_BASE_ADDR_H, 'h514);
+ this.SS_OTP_FC_BASE_ADDR_L = new("SS_OTP_FC_BASE_ADDR_L");
+ this.SS_OTP_FC_BASE_ADDR_L.configure(this);
+
+ this.SS_OTP_FC_BASE_ADDR_L.build();
+ this.default_map.add_reg(this.SS_OTP_FC_BASE_ADDR_L, 'h518);
+ this.SS_OTP_FC_BASE_ADDR_H = new("SS_OTP_FC_BASE_ADDR_H");
+ this.SS_OTP_FC_BASE_ADDR_H.configure(this);
+
+ this.SS_OTP_FC_BASE_ADDR_H.build();
+ this.default_map.add_reg(this.SS_OTP_FC_BASE_ADDR_H, 'h51c);
+ this.SS_UDS_SEED_BASE_ADDR_L = new("SS_UDS_SEED_BASE_ADDR_L");
+ this.SS_UDS_SEED_BASE_ADDR_L.configure(this);
+
+ this.SS_UDS_SEED_BASE_ADDR_L.build();
+ this.default_map.add_reg(this.SS_UDS_SEED_BASE_ADDR_L, 'h520);
+ this.SS_UDS_SEED_BASE_ADDR_H = new("SS_UDS_SEED_BASE_ADDR_H");
+ this.SS_UDS_SEED_BASE_ADDR_H.configure(this);
+
+ this.SS_UDS_SEED_BASE_ADDR_H.build();
+ this.default_map.add_reg(this.SS_UDS_SEED_BASE_ADDR_H, 'h524);
+ this.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET = new("SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET");
+ this.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.configure(this);
+
+ this.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.build();
+ this.default_map.add_reg(this.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET, 'h528);
+ this.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES = new("SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES");
+ this.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.configure(this);
+
+ this.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.build();
+ this.default_map.add_reg(this.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES, 'h52c);
+ this.SS_DEBUG_INTENT = new("SS_DEBUG_INTENT");
+ this.SS_DEBUG_INTENT.configure(this);
+
+ this.SS_DEBUG_INTENT.build();
+ this.default_map.add_reg(this.SS_DEBUG_INTENT, 'h530);
+ foreach(this.SS_STRAP_GENERIC[i0]) begin
+ this.SS_STRAP_GENERIC[i0] = new($sformatf("SS_STRAP_GENERIC[%0d]", i0));
+ this.SS_STRAP_GENERIC[i0].configure(this);
+
+ this.SS_STRAP_GENERIC[i0].build();
+ this.default_map.add_reg(this.SS_STRAP_GENERIC[i0], 'h5a0 + i0*'h4);
+ end
+ this.SS_DBG_MANUF_SERVICE_REG_REQ = new("SS_DBG_MANUF_SERVICE_REG_REQ");
+ this.SS_DBG_MANUF_SERVICE_REG_REQ.configure(this);
+
+ this.SS_DBG_MANUF_SERVICE_REG_REQ.build();
+ this.default_map.add_reg(this.SS_DBG_MANUF_SERVICE_REG_REQ, 'h5c0);
+ this.SS_DBG_MANUF_SERVICE_REG_RSP = new("SS_DBG_MANUF_SERVICE_REG_RSP");
+ this.SS_DBG_MANUF_SERVICE_REG_RSP.configure(this);
+
+ this.SS_DBG_MANUF_SERVICE_REG_RSP.build();
+ this.default_map.add_reg(this.SS_DBG_MANUF_SERVICE_REG_RSP, 'h5c4);
+ foreach(this.SS_SOC_DBG_UNLOCK_LEVEL[i0]) begin
+ this.SS_SOC_DBG_UNLOCK_LEVEL[i0] = new($sformatf("SS_SOC_DBG_UNLOCK_LEVEL[%0d]", i0));
+ this.SS_SOC_DBG_UNLOCK_LEVEL[i0].configure(this);
+
+ this.SS_SOC_DBG_UNLOCK_LEVEL[i0].build();
+ this.default_map.add_reg(this.SS_SOC_DBG_UNLOCK_LEVEL[i0], 'h5c8 + i0*'h4);
+ end
+ foreach(this.SS_GENERIC_FW_EXEC_CTRL[i0]) begin
+ this.SS_GENERIC_FW_EXEC_CTRL[i0] = new($sformatf("SS_GENERIC_FW_EXEC_CTRL[%0d]", i0));
+ this.SS_GENERIC_FW_EXEC_CTRL[i0].configure(this);
+
+ this.SS_GENERIC_FW_EXEC_CTRL[i0].build();
+ this.default_map.add_reg(this.SS_GENERIC_FW_EXEC_CTRL[i0], 'h5d0 + i0*'h4);
+ end
foreach(this.internal_obf_key[i0]) begin
this.internal_obf_key[i0] = new($sformatf("internal_obf_key[%0d]", i0));
this.internal_obf_key[i0].configure(this);
diff --git a/src/soc_ifc/rtl/soc_ifc_subsystem_reg.rdl b/src/soc_ifc/rtl/soc_ifc_subsystem_reg.rdl
new file mode 100644
index 000000000..bcb3e1479
--- /dev/null
+++ b/src/soc_ifc/rtl/soc_ifc_subsystem_reg.rdl
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+////////////////////////////////////////////////////////////////
+// Subsystem Straps and Registers
+
+field strap {sw = rw; hw = rw; we; swwel; resetsignal = cptra_pwrgood;};
+
+reg {
+ name = "Subsystem Caliptra Base Address (Low)";
+ desc = "Subsystem Caliptra Base Address Lower 32 bits (from AXI).
+ [br]Indicates base address of Caliptra register set from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_l[32]=32'h0;
+} SS_CALIPTRA_BASE_ADDR_L @0x500;
+
+reg {
+ name = "Subsystem Caliptra Base Address (High)";
+ desc = "Subsystem Caliptra Base Address Upper 32 bits (from AXI).
+ [br]Indicates base address of Caliptra register set from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_h[32]=32'h0;
+} SS_CALIPTRA_BASE_ADDR_H;
+
+reg {
+ name = "Subsystem MCI Base Address (Low)";
+ desc = "Subsystem MCI Base Address Lower 32 bits (from AXI).
+ [br]Indicates base address of MCI register set from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_l[32]=32'h0;
+} SS_MCI_BASE_ADDR_L;
+
+reg {
+ name = "Subsystem MCI Base Address (High)";
+ desc = "Subsystem MCI Base Address Upper 32 bits (from AXI).
+ [br]Indicates base address of MCI register set from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_h[32]=32'h0;
+} SS_MCI_BASE_ADDR_H;
+
+reg {
+ name = "Subsystem Recovery Interface Base Address (Low)";
+ desc = "Subsystem Recovery Interface Base Address Lower 32 bits (from AXI).
+ [br]Indicates base address of OCP Recovery Interface register set from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_l[32]=32'h0;
+} SS_RECOVERY_IFC_BASE_ADDR_L;
+
+reg {
+ name = "Subsystem Recovery Interface Base Address (High)";
+ desc = "Subsystem Recovery Interface Base Address Upper 32 bits (from AXI).
+ [br]Indicates base address of OCP Recovery Interface register set from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_h[32]=32'h0;
+} SS_RECOVERY_IFC_BASE_ADDR_H;
+
+reg {
+ name = "Subsystem Fuse Controller Base Address (Low)";
+ desc = "Subsystem Fuse Controller Base Address Lower 32 bits (from AXI).
+ [br]Indicates base address of OTP Fuse Controller from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_l[32]=32'h0;
+} SS_OTP_FC_BASE_ADDR_L;
+
+reg {
+ name = "Subsystem Fuse Controller Base Address (High)";
+ desc = "Subsystem Fuse Controller Base Address Upper 32 bits (from AXI).
+ [br]Indicates base address of OTP Fuse Controller from AXI fabric.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_h[32]=32'h0;
+} SS_OTP_FC_BASE_ADDR_H;
+
+reg {
+ name = "Subsystem UDS Seed Destination Base Address (Low)";
+ desc = "Subsystem UDS Seed Destination Base Address Lower 32 bits (from AXI). Used as the write address when programming the UDS seed during manufacturing.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_l[32]=32'h0;
+} SS_UDS_SEED_BASE_ADDR_L;
+
+reg {
+ name = "Subsystem UDS Seed Destination Base Address (High)";
+ desc = "Subsystem UDS Seed Destination Base Address Upper 32 bits (from AXI). Used as the write address when programming the UDS seed during manufacturing.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap addr_h[32]=32'h0;
+} SS_UDS_SEED_BASE_ADDR_H;
+
+reg {
+ name = "Subsystem Production Debug Unlock Authentication Public Key Hash Offset";
+ desc = "Provides an offset in the destination register bank at which a set of Public Key Hashes may be found. The number of hashes available at this offset is indicated by
+ SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap offset[32]=32'h0;
+} SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET;
+
+reg {
+ name = "Subsystem Production Debug Unlock Authentication Public Key Hash Number";
+ desc = "Provides the number of Public Key Hashes that may be found at the offset in the destination register bank, specified in SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap num[32]=32'h8;
+} SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES;
+
+reg {
+ name = "DEBUG INTENT";
+ desc = "Strap from SoC in Subsystem configuration that indicates if this boot cycle will be used for debug. In passive mode this register always reflects a value of 0.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RO
+ [br]TAP Access [in debug/manuf mode]: RW";
+ field strap {sw = r; hw = rw; we; resetsignal = cptra_pwrgood;} debug_intent=1'b0;
+} SS_DEBUG_INTENT;
+
+reg {
+ name = "GENERIC STRAP";
+ desc = "Straps reserved for late-binding features for survivability.
+ [br]Strap that is initialized from Caliptra input port at cptra_pwrgood deassertion. May be overwritten by SoC prior to CPTRA_FUSE_WR_DONE. Locked by CPTRA_FUSE_WR_DONE.
+ [br]Caliptra Access: RO
+ [br]SOC Access: RWL-S";
+ strap data[32]=32'h0;
+} SS_STRAP_GENERIC[4] @0x5a0;
+
+reg {
+ name = "SUBSYSTEM DEBUG & MANUF SERVICE REG REQUEST";
+ desc = "JTAG in debug/manuf mode or SOC can write to this register for ROM/FW defined skips or services.
+ [br]This register is used to support Subsystem flows, and is disabled in Caliptra passive mode.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RW
+ [br]TAP Access [in debug/manuf mode]: RW";
+ field {desc="Manufacturing debug unlock request. Only writable when lifecycle state is MANUFACTURING and DEBUG_INTENT strap is set to 1."; sw=rw; hw=rw; swwe=true; we=true; resetsignal = cptra_rst_b;} MANUF_DBG_UNLOCK_REQ = 1'b0;
+ field {desc="Production debug unlock request. Only writable when lifecycle state is PRODUCTION and DEBUG_INTENT strap is set to 1." ; sw=rw; hw=rw; swwe=true; we=true; resetsignal = cptra_rst_b;} PROD_DBG_UNLOCK_REQ = 1'b0;
+ field {desc="UDS programming request." ; sw=rw; hw=rw; swwe=true; we=true; resetsignal = cptra_rst_b;} UDS_PROGRAM_REQ = 1'b0;
+ field {desc="RSVD" ; sw=r ; hw= w; } RSVD[29];
+} SS_DBG_MANUF_SERVICE_REG_REQ @0x5c0;
+
+reg {
+ name = "SUBSYSTEM DEBUG & MANUF SERVICE REG RESPONSE";
+ desc = "JTAG in debug/manuf mode or SOC can read from this register for ROM/FW defined skips or services.
+ [br]This register is used to support Subsystem flows, and is disabled in Caliptra passive mode.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RO
+ [br]TAP Access [in debug/manuf mode]: RO";
+ field {desc="Manufacturing debug unlock was successful. Only writable by Caliptra, and only when lifecycle state is MANUFACTURING and DEBUG_INTENT strap is set to 1. Sticky once set, until warm reset."; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} MANUF_DBG_UNLOCK_SUCCESS = 1'b0;
+ field {desc="Manufacturing debug unlock failed. Only writable by Caliptra, and only when lifecycle state is MANUFACTURING and DEBUG_INTENT strap is set to 1." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} MANUF_DBG_UNLOCK_FAIL = 1'b0;
+ field {desc="Manufacturing debug unlock is in progress. Only writable by Caliptra, and only when lifecycle state is MANUFACTURING and DEBUG_INTENT strap is set to 1." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} MANUF_DBG_UNLOCK_IN_PROGRESS = 1'b0;
+ field {desc="Production debug unlock was successful. Only writable by Caliptra, and only when lifecycle state is PRODUCTION and DEBUG_INTENT strap is set to 1. Sticky once set, until warm reset." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} PROD_DBG_UNLOCK_SUCCESS = 1'b0;
+ field {desc="Production debug unlock failed. Only writable by Caliptra, and only when lifecycle state is PRODUCTION and DEBUG_INTENT strap is set to 1." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} PROD_DBG_UNLOCK_FAIL = 1'b0;
+ field {desc="Production debug unlock is in progress. Only writable by Caliptra, and only when lifecycle state is PRODUCTION and DEBUG_INTENT strap is set to 1." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} PROD_DBG_UNLOCK_IN_PROGRESS = 1'b0;
+ field {desc="UDS Programming was successful. Only writable by Caliptra. Sticky once set, until warm reset." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} UDS_PROGRAM_SUCCESS = 1'b0;
+ field {desc="UDS Programming failed. Only writable by Caliptra." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} UDS_PROGRAM_FAIL = 1'b0;
+ field {desc="UDS Programming is in progress. Only writable by Caliptra." ; sw=rw; hw=rw; we; swwe=true; resetsignal = cptra_rst_b;} UDS_PROGRAM_IN_PROGRESS = 1'b0;
+ field {desc="RSVD" ; sw=r ; hw= w; } RSVD[23];
+} SS_DBG_MANUF_SERVICE_REG_RSP;
+
+reg {
+ name = "SUBSYSTEM SOC DEBUG UNLOCK LEVEL";
+ desc = "Individual bits indicating debug unlock level to multiple SoC endpoints. Writable only for Caliptra, and only when DEBUG_INTENT is set to 1.
+ [br]This register is used to support Subsystem flows, and is disabled in Caliptra passive mode.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RO
+ [br]TAP Access [in debug/manuf mode]: RO";
+ field {desc="Debug unlock level"; sw=rw; swwel=true/*soc_req || !debug_intent*/; hw=rw; we;} LEVEL[32] = 32'h0;
+} SS_SOC_DBG_UNLOCK_LEVEL[2];
+
+reg {
+ name = "Generic Firmware Execution Control";
+ desc = "Each bit may be optionally routed to a unique SoC core that requires a hardware enforced execution enablement.
+ For example, this bit may be used to block execution access to an instruction memory containing firmware updates.
+ Bits 0/1 are reserved. Bit 2 controls the MCU from the Caliptra Subsystem. All other bits are integrator-defined.
+ [br]These bits are only writable for Caliptra firmware.
+ [br]Caliptra Access: RW
+ [br]SOC Access: RO
+ [br]TAP Access [in debug/manuf mode]: RO";
+ field {sw=rw; swwel=soc_req; hw=r; } go[32] = 32'h0;
+} SS_GENERIC_FW_EXEC_CTRL[4];
diff --git a/src/soc_ifc/rtl/soc_ifc_top.sv b/src/soc_ifc/rtl/soc_ifc_top.sv
index fb37b05ae..f86c535c0 100644
--- a/src/soc_ifc/rtl/soc_ifc_top.sv
+++ b/src/soc_ifc/rtl/soc_ifc_top.sv
@@ -42,7 +42,7 @@ module soc_ifc_top
input logic cptra_rst_b,
output logic ready_for_fuses,
- output logic ready_for_fw_push,
+ output logic ready_for_mb_processing,
output logic ready_for_runtime,
output logic mailbox_data_avail,
@@ -106,6 +106,28 @@ module soc_ifc_top
output logic [`CLP_OBF_FE_DWORDS-1 :0][31:0] obf_field_entropy,
output logic [`CLP_OBF_UDS_DWORDS-1:0][31:0] obf_uds_seed,
+ // Subsystem mode straps
+ input logic [63:0] strap_ss_caliptra_base_addr,
+ input logic [63:0] strap_ss_mci_base_addr,
+ input logic [63:0] strap_ss_recovery_ifc_base_addr,
+ input logic [63:0] strap_ss_otp_fc_base_addr,
+ input logic [63:0] strap_ss_uds_seed_base_addr,
+ input logic [31:0] strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset,
+ input logic [31:0] strap_ss_num_of_prod_debug_unlock_auth_pk_hashes,
+ input logic [31:0] strap_ss_strap_generic_0,
+ input logic [31:0] strap_ss_strap_generic_1,
+ input logic [31:0] strap_ss_strap_generic_2,
+ input logic [31:0] strap_ss_strap_generic_3,
+ input logic ss_debug_intent,
+ output logic cptra_ss_debug_intent,
+
+ // Subsystem mode debug outputs
+ output logic ss_dbg_manuf_enable,
+ output logic [63:0] ss_soc_dbg_unlock_level,
+
+ // Subsystem mode firmware execution control
+ output logic [127:0] ss_generic_fw_exec_ctrl,
+
// NMI Vector
output logic [31:0] nmi_vector,
output logic nmi_intr,
@@ -221,10 +243,19 @@ logic BootFSM_BrkPoint_Latched;
logic BootFSM_BrkPoint_valid;
logic BootFSM_BrkPoint_Flag;
+logic cptra_uncore_dmi_locked_reg_en;
+logic cptra_uncore_dmi_unlocked_reg_en;
logic dmi_inc_rdptr;
+logic dmi_inc_wrptr;
logic cptra_uncore_dmi_reg_dout_access_f;
+logic cptra_uncore_dmi_reg_din_access_f;
mbox_dmi_reg_t mbox_dmi_reg;
-logic [31:0] cptra_uncore_dmi_reg_rdata_in;
+logic [31:0] cptra_uncore_dmi_locked_reg_rdata_in;
+logic [31:0] cptra_uncore_dmi_unlocked_reg_rdata_in;
+
+logic strap_we;
+logic cptra_uncore_dmi_unlocked_reg_wr_en;
+logic cptra_uncore_dmi_locked_reg_wr_en;
soc_ifc_reg__in_t soc_ifc_reg_hwif_in;
soc_ifc_reg__out_t soc_ifc_reg_hwif_out;
@@ -433,19 +464,14 @@ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.iTRNG_en.next = 1'b1;
`else
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.iTRNG_en.next = 1'b0;
`endif
-`ifdef CALIPTRA_INTERNAL_QSPI
-always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.QSPI_en.next = 1'b1;
-`else
-always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.QSPI_en.next = 1'b0;
-`endif
-always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.I3C_en.next = 1'b0;
-`ifdef CALIPTRA_INTERNAL_UART
-always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b1;
-`else
-always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.UART_en.next = 1'b0;
-`endif
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.RSVD_en.next = 3'b0;
// Hardcoded because all future revs will have LMS accelerator available
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.LMS_acc_en.next = 1'b1;
+`ifdef CALIPTRA_MODE_SUBSYSTEM
+ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.ACTIVE_MODE_en.next = 1'b1;
+`else
+ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.ACTIVE_MODE_en.next = 1'b1;
+`endif
//SOC Stepping ID update
always_comb begin
@@ -471,9 +497,9 @@ always_comb begin
end
//flow status
- mailbox_flow_done = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.mailbox_flow_done.value;
- ready_for_fw_push = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.ready_for_fw.value;
- ready_for_runtime = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.ready_for_runtime.value;
+ mailbox_flow_done = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.mailbox_flow_done.value;
+ ready_for_mb_processing = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.ready_for_mb_processing.value;
+ ready_for_runtime = soc_ifc_reg_hwif_out.CPTRA_FLOW_STATUS.ready_for_runtime.value;
soc_ifc_reg_hwif_in.CPTRA_FLOW_STATUS.ready_for_fuses.next = ready_for_fuses;
soc_ifc_reg_hwif_in.CPTRA_FLOW_STATUS.boot_fsm_ps.next = boot_fsm_ps;
soc_ifc_reg_hwif_in.CPTRA_SECURITY_STATE.device_lifecycle.next = security_state.device_lifecycle;
@@ -576,12 +602,12 @@ end
always_comb scan_mode_p = scan_mode & ~scan_mode_f;
-//Filtering by ID
+//Filtering by AXI_USER
always_comb begin
for (int i=0; i<5; i++) begin
//once locked, can't be cleared until reset
soc_ifc_reg_hwif_in.CPTRA_MBOX_AXI_USER_LOCK[i].LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_USER_LOCK[i].LOCK.value;
- //lock the writes to valid id field once lock is set
+ //lock the writes to valid user field once lock is set
soc_ifc_reg_hwif_in.CPTRA_MBOX_VALID_AXI_USER[i].AXI_USER.swwel = soc_ifc_reg_hwif_out.CPTRA_MBOX_AXI_USER_LOCK[i].LOCK.value;
//If integrator set AXI_USER values at integration time, pick it up from the define
valid_mbox_users[i] = CPTRA_SET_MBOX_AXI_USER_INTEG[i] ? CPTRA_MBOX_VALID_AXI_USER[i][AXI_USER_WIDTH-1:0] :
@@ -590,7 +616,7 @@ always_comb begin
end
end
-//can't write to trng valid id after it is locked
+//can't write to trng valid user after it is locked
always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value;
always_comb soc_ifc_reg_hwif_in.CPTRA_TRNG_AXI_USER_LOCK.LOCK.swwel = soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value;
@@ -620,7 +646,9 @@ always_comb begin
end
for (int i=0; i<12; i++) begin
soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash[i].hash.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
- soc_ifc_reg_hwif_in.fuse_owner_pk_hash[i].hash.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+ end
+ for (int i=0; i<8; i++) begin
+ soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash_mask[i].mask.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
end
for (int i=0; i < `CLP_OBF_FE_DWORDS; i++) begin
@@ -635,27 +663,218 @@ always_comb begin
soc_ifc_reg_hwif_in.fuse_idevid_manuf_hsm_id[i].hsm_id.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
end
- // Run-time SVN can be unlocked whenever fuse_wr_done is 'reset' which happens on a warm reset
for (int i=0; i<4; i++) begin
soc_ifc_reg_hwif_in.fuse_runtime_svn[i].svn.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
end
-
+
+ for (int i=0; i<4; i++) begin
+ soc_ifc_reg_hwif_in.fuse_manuf_dbg_unlock_token[i].token.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+ end
+end
+
+always_comb soc_ifc_reg_hwif_in.fuse_fmc_key_manifest_svn.svn.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.fuse_anti_rollback_disable.dis.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.fuse_lms_revocation.lms_revocation.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.fuse_mldsa_revocation.mldsa_revocation.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+
+// Lockable registers
+always_comb begin
+ soc_ifc_reg_hwif_in.CPTRA_HW_CAPABILITIES.cap.swwel = soc_ifc_reg_req_data.soc_req || soc_ifc_reg_hwif_out.CPTRA_CAP_LOCK.lock.value;
+ soc_ifc_reg_hwif_in.CPTRA_FW_CAPABILITIES.cap.swwel = soc_ifc_reg_req_data.soc_req || soc_ifc_reg_hwif_out.CPTRA_CAP_LOCK.lock.value;
+ for (int i=0; i<12; i++) begin
+ soc_ifc_reg_hwif_in.CPTRA_OWNER_PK_HASH[i].hash.swwel = soc_ifc_reg_hwif_out.CPTRA_OWNER_PK_HASH_LOCK.lock.value & ~soc_ifc_reg_req_data.soc_req;
+ end
+end
+
+
+//Uncore registers only open for debug unlock or manufacturing
+always_comb cptra_uncore_dmi_unlocked_reg_en = cptra_uncore_dmi_reg_en &
+ (~(security_state.debug_locked) |
+ (security_state.device_lifecycle == DEVICE_MANUFACTURING));
+//Uncore registers open for all cases
+always_comb cptra_uncore_dmi_locked_reg_en = cptra_uncore_dmi_reg_en;
+
+always_comb cptra_uncore_dmi_unlocked_reg_wr_en = (cptra_uncore_dmi_reg_wr_en & cptra_uncore_dmi_unlocked_reg_en);
+always_comb cptra_uncore_dmi_locked_reg_wr_en = (cptra_uncore_dmi_reg_wr_en & cptra_uncore_dmi_locked_reg_en);
+
+// Subsystem straps capture the initial value from input port on rising edge of cptra_pwrgood
+always_ff @(posedge clk or negedge cptra_pwrgood) begin
+ if(~cptra_pwrgood) begin
+ strap_we <= 1'b1;
+ end
+ else begin
+ strap_we <= 1'b0;
+ end
+end
+
+always_comb begin : ss_reg_hwwe
+ //SS STRAPS WITH TAP WRITE ACCESS
+ soc_ifc_reg_hwif_in.SS_CALIPTRA_BASE_ADDR_L.addr_l.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_CALIPTRA_BASE_ADDR_L));
+ soc_ifc_reg_hwif_in.SS_CALIPTRA_BASE_ADDR_H.addr_h.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_CALIPTRA_BASE_ADDR_H));
+ soc_ifc_reg_hwif_in.SS_MCI_BASE_ADDR_L.addr_l.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_MCI_BASE_ADDR_L));
+ soc_ifc_reg_hwif_in.SS_MCI_BASE_ADDR_H.addr_h.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_MCI_BASE_ADDR_H));
+ soc_ifc_reg_hwif_in.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_L));
+ soc_ifc_reg_hwif_in.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_H));
+ soc_ifc_reg_hwif_in.SS_OTP_FC_BASE_ADDR_L.addr_l.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_OTP_FC_BASE_ADDR_L));
+ soc_ifc_reg_hwif_in.SS_OTP_FC_BASE_ADDR_H.addr_h.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_OTP_FC_BASE_ADDR_H));
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[0].data.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_0));
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[1].data.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_1));
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[2].data.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_2));
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[3].data.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_3));
+ soc_ifc_reg_hwif_in.SS_DEBUG_INTENT.debug_intent.we = strap_we | (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DEBUG_INTENT));
+ //SS REGISTERS WITH TAP WRITE ACCESS
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.we = (cptra_uncore_dmi_locked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_REQ));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.we = (cptra_uncore_dmi_locked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_REQ));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.we = (cptra_uncore_dmi_locked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_REQ));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.we = (cptra_uncore_dmi_unlocked_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP));
+ soc_ifc_reg_hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[0].LEVEL.we = (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_UNLOCK_LEVEL0));
+ soc_ifc_reg_hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[1].LEVEL.we = (cptra_uncore_dmi_unlocked_reg_wr_en &
+ (cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_UNLOCK_LEVEL1));
+ //STRAPS WITH RO or NO TAP ACCESS
+ soc_ifc_reg_hwif_in.SS_UDS_SEED_BASE_ADDR_L.addr_l.we = strap_we; //RO by TAP
+ soc_ifc_reg_hwif_in.SS_UDS_SEED_BASE_ADDR_H.addr_h.we = strap_we; //RO by TAP
+ soc_ifc_reg_hwif_in.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.we = strap_we; //No TAP access
+ soc_ifc_reg_hwif_in.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.we = strap_we; //No TAP access
+end
+
+always_comb begin : ss_reg_next_vals
+ //SS STRAPS WITH TAP WRITE ACCESS
+ soc_ifc_reg_hwif_in.SS_CALIPTRA_BASE_ADDR_L.addr_l.next = strap_we ? strap_ss_caliptra_base_addr[31:0] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_CALIPTRA_BASE_ADDR_H.addr_h.next = strap_we ? strap_ss_caliptra_base_addr[63:32] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_MCI_BASE_ADDR_L.addr_l.next = strap_we ? strap_ss_mci_base_addr[31:0] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_MCI_BASE_ADDR_H.addr_h.next = strap_we ? strap_ss_mci_base_addr[63:32] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.next = strap_we ? strap_ss_recovery_ifc_base_addr[31:0] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.next = strap_we ? strap_ss_recovery_ifc_base_addr[63:32] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_OTP_FC_BASE_ADDR_L.addr_l.next = strap_we ? strap_ss_otp_fc_base_addr[31:0] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_OTP_FC_BASE_ADDR_H.addr_h.next = strap_we ? strap_ss_otp_fc_base_addr[63:32] : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[0].data.next = strap_we ? strap_ss_strap_generic_0 : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[1].data.next = strap_we ? strap_ss_strap_generic_1 : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[2].data.next = strap_we ? strap_ss_strap_generic_2 : cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[3].data.next = strap_we ? strap_ss_strap_generic_3 : cptra_uncore_dmi_reg_wdata;
+ //SS REGISTERS WITH TAP WRITE ACCESS
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.next = cptra_uncore_dmi_reg_wdata[0];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.next = cptra_uncore_dmi_reg_wdata[1];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.next = cptra_uncore_dmi_reg_wdata[2];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next[28:0] = 29'h0;
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.next = cptra_uncore_dmi_reg_wdata[0];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL.next = cptra_uncore_dmi_reg_wdata[1];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.next = cptra_uncore_dmi_reg_wdata[2];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.next = cptra_uncore_dmi_reg_wdata[3];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL.next = cptra_uncore_dmi_reg_wdata[4];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS.next = cptra_uncore_dmi_reg_wdata[5];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS.next = cptra_uncore_dmi_reg_wdata[6];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL.next = cptra_uncore_dmi_reg_wdata[7];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS.next = cptra_uncore_dmi_reg_wdata[8];
+ soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next[22:0] = 23'h0;
+ soc_ifc_reg_hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[0].LEVEL.next = cptra_uncore_dmi_reg_wdata;
+ soc_ifc_reg_hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[1].LEVEL.next = cptra_uncore_dmi_reg_wdata;
+ //STRAPS WITH RO or NO TAP ACCESS
+ soc_ifc_reg_hwif_in.SS_UDS_SEED_BASE_ADDR_L.addr_l.next = strap_ss_uds_seed_base_addr[31:0];
+ soc_ifc_reg_hwif_in.SS_UDS_SEED_BASE_ADDR_H.addr_h.next = strap_ss_uds_seed_base_addr[63:32];
+ soc_ifc_reg_hwif_in.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.next = strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset;
+ soc_ifc_reg_hwif_in.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.next = strap_ss_num_of_prod_debug_unlock_auth_pk_hashes;
+
+ // Debug intent is latched on rising edge of cptra_pwrgood and may not be modified until cold reset
+ // Debug intent register is only populated in Subsystem mode. Passive mode uses
+ // legacy debug unlock flow
+ `ifdef CALIPTRA_MODE_SUBSYSTEM
+ soc_ifc_reg_hwif_in.SS_DEBUG_INTENT.debug_intent.next = strap_we ? ss_debug_intent : cptra_uncore_dmi_reg_wdata[0];
+ `else
+ soc_ifc_reg_hwif_in.SS_DEBUG_INTENT.debug_intent.next = 1'b0;
+ `endif
+end
+
+always_comb cptra_ss_debug_intent = soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value;
+
+// Also RW-able by SW until CPTRA_FUSE_WR_DONE
+always_comb soc_ifc_reg_hwif_in.SS_CALIPTRA_BASE_ADDR_L.addr_l.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_CALIPTRA_BASE_ADDR_H.addr_h.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_MCI_BASE_ADDR_L.addr_l.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_MCI_BASE_ADDR_H.addr_h.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_OTP_FC_BASE_ADDR_L.addr_l.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_OTP_FC_BASE_ADDR_H.addr_h.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_UDS_SEED_BASE_ADDR_L.addr_l.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_UDS_SEED_BASE_ADDR_H.addr_h.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_PROD_DEBUG_UNLOCK_AUTH_PK_HASH_REG_BANK_OFFSET.offset.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_NUM_OF_PROD_DEBUG_UNLOCK_AUTH_PK_HASHES.num.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[0].data.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[1].data.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[2].data.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb soc_ifc_reg_hwif_in.SS_STRAP_GENERIC[3].data.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+
+// DEBUG service request signals are writable based on lifecycle state
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.swwe = soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_MANUFACTURING);
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.swwe = soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_PRODUCTION);
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.swwe = '0; //FIXME
+
+// DEBUG service response signals are writable based on lifecycle state; success bits are also sticky until reset
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS .swwe = !soc_ifc_reg_req_data.soc_req && soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_MANUFACTURING) && !soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value;
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL .swwe = !soc_ifc_reg_req_data.soc_req && soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_MANUFACTURING);
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS.swwe = !soc_ifc_reg_req_data.soc_req && soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_MANUFACTURING);
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS .swwe = !soc_ifc_reg_req_data.soc_req && soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_PRODUCTION) && !soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS.value;
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL .swwe = !soc_ifc_reg_req_data.soc_req && soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_PRODUCTION);
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS .swwe = !soc_ifc_reg_req_data.soc_req && soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value && (security_state.device_lifecycle == DEVICE_PRODUCTION);
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS .swwe = !soc_ifc_reg_req_data.soc_req; //FIXME
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL .swwe = !soc_ifc_reg_req_data.soc_req; //FIXME
+always_comb soc_ifc_reg_hwif_in.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS .swwe = !soc_ifc_reg_req_data.soc_req; //FIXME
+
+always_comb ss_dbg_manuf_enable = soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS.value;
+
+// DEBUG unlock level signal is only writable by Caliptra, and only when DEBUG_INTENT is 1
+always_comb begin
+ for (int i=0; i<2; i++) begin
+ soc_ifc_reg_hwif_in.SS_SOC_DBG_UNLOCK_LEVEL[i].LEVEL.swwel = soc_ifc_reg_req_data.soc_req || !soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value;
+ end
end
+always_comb ss_soc_dbg_unlock_level = {soc_ifc_reg_hwif_out.SS_SOC_DBG_UNLOCK_LEVEL[1].LEVEL.value,
+ soc_ifc_reg_hwif_out.SS_SOC_DBG_UNLOCK_LEVEL[0].LEVEL.value};
-always_comb soc_ifc_reg_hwif_in.fuse_key_manifest_pk_hash_mask.mask.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
-always_comb soc_ifc_reg_hwif_in.fuse_fmc_key_manifest_svn.svn.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
-always_comb soc_ifc_reg_hwif_in.fuse_anti_rollback_disable.dis.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
-always_comb soc_ifc_reg_hwif_in.fuse_life_cycle.life_cycle.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
-always_comb soc_ifc_reg_hwif_in.fuse_lms_verify.lms_verify.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
-always_comb soc_ifc_reg_hwif_in.fuse_lms_revocation.lms_revocation.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
-always_comb soc_ifc_reg_hwif_in.fuse_soc_stepping_id.soc_stepping_id.swwel = soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+always_comb ss_generic_fw_exec_ctrl = {soc_ifc_reg_hwif_out.SS_GENERIC_FW_EXEC_CTRL[3].go.value,
+ soc_ifc_reg_hwif_out.SS_GENERIC_FW_EXEC_CTRL[2].go.value,
+ soc_ifc_reg_hwif_out.SS_GENERIC_FW_EXEC_CTRL[1].go.value,
+ soc_ifc_reg_hwif_out.SS_GENERIC_FW_EXEC_CTRL[0].go.value};
-// Fuse write done can be written by SOC if it is already NOT '1. uController can only read this bit. The bit gets reset on cold reset
+// Fuse write done can be written by SOC if it is already NOT '1.
+// uController can only read this bit. The bit gets reset on cold reset
always_comb soc_ifc_reg_hwif_in.CPTRA_FUSE_WR_DONE.done.swwe = soc_ifc_reg_req_data.soc_req & ~soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value;
+// CPTRA_CAP_LOCK is a lockable register.
+// "lock" can be written by Caliptra if it is already NOT '1. SoC can only read this bit. The bit gets reset on warm reset
+always_comb soc_ifc_reg_hwif_in.CPTRA_CAP_LOCK.lock.swwel = soc_ifc_reg_req_data.soc_req || soc_ifc_reg_hwif_out.CPTRA_CAP_LOCK.lock.value;
+// OWNER PK HASH LOCK is a lockable register.
+// "lock" can be written by SOC if it is already NOT '1. uController can only read this bit. The bit gets reset on cold reset
+always_comb soc_ifc_reg_hwif_in.CPTRA_OWNER_PK_HASH_LOCK.lock.swwe = soc_ifc_reg_req_data.soc_req & ~soc_ifc_reg_hwif_out.CPTRA_OWNER_PK_HASH_LOCK.lock.value;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//When TRNG_AXI_USER_LOCK is one only allow valid users to write to TRNG
-//If TRNG_AXI_USER_LOCK is zero allow any id to write to TRNG
+//If TRNG_AXI_USER_LOCK is zero allow any user to write to TRNG
always_comb valid_trng_user = soc_ifc_reg_req_data.soc_req & (~soc_ifc_reg_hwif_out.CPTRA_TRNG_AXI_USER_LOCK.LOCK.value |
(soc_ifc_reg_req_data.user == soc_ifc_reg_hwif_out.CPTRA_TRNG_VALID_AXI_USER.AXI_USER.value[AXI_USER_WIDTH-1:0]));
@@ -879,6 +1098,10 @@ i_mbox (
.mbox_protocol_error(mbox_protocol_error),
.mbox_inv_axi_user_axs(mbox_inv_user_p),
.dmi_inc_rdptr(dmi_inc_rdptr),
+ .dmi_inc_wrptr(dmi_inc_wrptr),
+ .dmi_reg_wen(cptra_uncore_dmi_locked_reg_en & cptra_uncore_dmi_reg_wr_en),
+ .dmi_reg_addr(cptra_uncore_dmi_reg_addr),
+ .dmi_reg_wdata(cptra_uncore_dmi_reg_wdata),
.dmi_reg(mbox_dmi_reg)
);
@@ -1009,6 +1232,7 @@ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.crypto_err .next = 1'b1;
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next = 1'b1;
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next = 1'b1;
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin .next = 1'b1;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next[27:0] = 28'h0;
// Flag the write even if the field being written to is already set to 1 - this is a new occurrence of the error and should trigger a new interrupt
always_comb unmasked_hw_error_fatal_write = (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.crypto_err .we && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.crypto_err .next) ||
(soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.we && ~soc_ifc_reg_hwif_out.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next) ||
@@ -1023,6 +1247,7 @@ always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc .we =
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next = 1'b1;
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo .next = 1'b1;
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc .next = 1'b1;
+always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.rsvd.next[28:0] = 29'h0;
// Flag the write even if the field being written to is already set to 1 - this is a new occurrence of the error and should trigger a new interrupt
always_comb unmasked_hw_error_non_fatal_write = (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.we && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_no_lock.value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.next) ||
(soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo .we && ~soc_ifc_reg_hwif_out.internal_hw_error_non_fatal_mask.mask_mbox_prot_ooo .value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo .next) ||
@@ -1040,35 +1265,121 @@ always_comb begin
end
//DMI register writes
-always_comb soc_ifc_reg_hwif_in.CPTRA_BOOTFSM_GO.GO.we = cptra_uncore_dmi_reg_wr_en & cptra_uncore_dmi_reg_en &
+always_comb soc_ifc_reg_hwif_in.CPTRA_BOOTFSM_GO.GO.we = cptra_uncore_dmi_reg_wr_en & cptra_uncore_dmi_locked_reg_en &
(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO);
always_comb soc_ifc_reg_hwif_in.CPTRA_BOOTFSM_GO.GO.next = cptra_uncore_dmi_reg_wdata[0];
-always_comb soc_ifc_reg_hwif_in.CPTRA_DBG_MANUF_SERVICE_REG.DATA.we = cptra_uncore_dmi_reg_wr_en & cptra_uncore_dmi_reg_en &
+always_comb soc_ifc_reg_hwif_in.CPTRA_DBG_MANUF_SERVICE_REG.DATA.we = cptra_uncore_dmi_reg_wr_en & cptra_uncore_dmi_locked_reg_en &
(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG);
always_comb soc_ifc_reg_hwif_in.CPTRA_DBG_MANUF_SERVICE_REG.DATA.next = cptra_uncore_dmi_reg_wdata;
-//DMI register read mux
-always_comb cptra_uncore_dmi_reg_rdata_in = ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DLEN)}} & mbox_dmi_reg.MBOX_DLEN) |
- ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DOUT)}} & mbox_dmi_reg.MBOX_DOUT) |
- ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_STATUS)}} & mbox_dmi_reg.MBOX_STATUS) |
- ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOT_STATUS)}} & soc_ifc_reg_hwif_out.CPTRA_BOOT_STATUS.status.value) |
- ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_HW_ERRROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_ENC.error_code.value) |
- ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_FW_ERROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_ENC.error_code.value) |
- ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO)}} & {31'b0, soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value}) |
- ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG)}} & soc_ifc_reg_hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value) ;
+//DMI locked register read mux
+always_comb cptra_uncore_dmi_locked_reg_rdata_in = ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DLEN)}} & mbox_dmi_reg.MBOX_DLEN) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DOUT)}} & mbox_dmi_reg.MBOX_DOUT) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_STATUS)}} & mbox_dmi_reg.MBOX_STATUS) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOT_STATUS)}} & soc_ifc_reg_hwif_out.CPTRA_BOOT_STATUS.status.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_HW_ERRROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_ENC.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_FW_ERROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_ENC.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO)}} & {31'b0, soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG)}} & soc_ifc_reg_hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_FATAL.rsvd.next[27:0],
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.crypto_err.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.nmi_pin.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_FW_FATAL_ERROR)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_FATAL.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_NON_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_NON_FATAL.rsvd.next[28:0],
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_FW_NON_FATAL_ERROR)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_REQ)}} & {soc_ifc_reg_hwif_in .SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next[28:0],
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP)}} & {soc_ifc_reg_hwif_in .SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next[22:0],
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS}) ;
+
+//DMI unlocked register read mux
+always_comb cptra_uncore_dmi_unlocked_reg_rdata_in = ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DLEN)}} & mbox_dmi_reg.MBOX_DLEN) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DOUT)}} & mbox_dmi_reg.MBOX_DOUT) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_STATUS)}} & mbox_dmi_reg.MBOX_STATUS) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOT_STATUS)}} & soc_ifc_reg_hwif_out.CPTRA_BOOT_STATUS.status.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_HW_ERRROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_ENC.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_FW_ERROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_ENC.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO)}} & {31'b0, soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG)}} & soc_ifc_reg_hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_FATAL.rsvd.next[27:0],
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.crypto_err.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.nmi_pin.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_FW_FATAL_ERROR)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_FATAL.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_NON_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_NON_FATAL.rsvd.next[28:0],
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value,
+ soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_FW_NON_FATAL_ERROR)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_NON_FATAL.error_code.value) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_UDS_SEED_BASE_ADDR_L)}} & soc_ifc_reg_hwif_out.SS_UDS_SEED_BASE_ADDR_L.addr_l.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_UDS_SEED_BASE_ADDR_H)}} & soc_ifc_reg_hwif_out.SS_UDS_SEED_BASE_ADDR_H.addr_h.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_DEBUG_INTENT)}} & {31'b0, soc_ifc_reg_hwif_out.SS_DEBUG_INTENT.debug_intent.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_CALIPTRA_BASE_ADDR_L)}} & soc_ifc_reg_hwif_out.SS_CALIPTRA_BASE_ADDR_L.addr_l.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_CALIPTRA_BASE_ADDR_H)}} & soc_ifc_reg_hwif_out.SS_CALIPTRA_BASE_ADDR_H.addr_h.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_MCI_BASE_ADDR_L)}} & soc_ifc_reg_hwif_out.SS_MCI_BASE_ADDR_L.addr_l.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_MCI_BASE_ADDR_H)}} & soc_ifc_reg_hwif_out.SS_MCI_BASE_ADDR_H.addr_h.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_L)}} & soc_ifc_reg_hwif_out.SS_RECOVERY_IFC_BASE_ADDR_L.addr_l.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_RECOVERY_IFC_BASE_ADDR_H)}} & soc_ifc_reg_hwif_out.SS_RECOVERY_IFC_BASE_ADDR_H.addr_h.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_OTP_FC_BASE_ADDR_L)}} & soc_ifc_reg_hwif_out.SS_OTP_FC_BASE_ADDR_L.addr_l.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_OTP_FC_BASE_ADDR_H)}} & soc_ifc_reg_hwif_out.SS_OTP_FC_BASE_ADDR_H.addr_h.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_0)}} & soc_ifc_reg_hwif_out.SS_STRAP_GENERIC[0].data.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_1)}} & soc_ifc_reg_hwif_out.SS_STRAP_GENERIC[1].data.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_2)}} & soc_ifc_reg_hwif_out.SS_STRAP_GENERIC[2].data.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_STRAP_GENERIC_3)}} & soc_ifc_reg_hwif_out.SS_STRAP_GENERIC[3].data.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_REQ)}} & {soc_ifc_reg_hwif_in .SS_DBG_MANUF_SERVICE_REG_REQ.RSVD.next[28:0],
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.PROD_DBG_UNLOCK_REQ.value,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.MANUF_DBG_UNLOCK_REQ.value}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_MANUF_SERVICE_REG_RSP)}} & {soc_ifc_reg_hwif_in .SS_DBG_MANUF_SERVICE_REG_RSP.RSVD.next[22:0],
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_IN_PROGRESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_FAIL,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.PROD_DBG_UNLOCK_SUCCESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_IN_PROGRESS,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_FAIL,
+ soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.MANUF_DBG_UNLOCK_SUCCESS}) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_UNLOCK_LEVEL0)}} & soc_ifc_reg_hwif_out.SS_SOC_DBG_UNLOCK_LEVEL[0].LEVEL.value ) |
+ ({32{(cptra_uncore_dmi_reg_addr == DMI_REG_SS_DBG_UNLOCK_LEVEL1)}} & soc_ifc_reg_hwif_out.SS_SOC_DBG_UNLOCK_LEVEL[1].LEVEL.value ) ;
+
+
+
+
//Increment the read pointer when we had a dmi read to data out and no access this clock
//This assumes that reg_en goes low between read accesses
-always_comb dmi_inc_rdptr = cptra_uncore_dmi_reg_dout_access_f & ~cptra_uncore_dmi_reg_en;
+always_comb dmi_inc_rdptr = cptra_uncore_dmi_reg_dout_access_f & ~cptra_uncore_dmi_locked_reg_en;
+always_comb dmi_inc_wrptr = cptra_uncore_dmi_reg_din_access_f & ~cptra_uncore_dmi_locked_reg_en;
always_ff @(posedge rdc_clk_cg or negedge cptra_pwrgood) begin
if (~cptra_pwrgood) begin
cptra_uncore_dmi_reg_rdata <= '0;
cptra_uncore_dmi_reg_dout_access_f <= '0;
+ cptra_uncore_dmi_reg_din_access_f <= '0;
end
else begin
- cptra_uncore_dmi_reg_rdata <= cptra_uncore_dmi_reg_en ? cptra_uncore_dmi_reg_rdata_in : cptra_uncore_dmi_reg_rdata;
- cptra_uncore_dmi_reg_dout_access_f <= cptra_uncore_dmi_reg_en & ~cptra_uncore_dmi_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DOUT);
+ cptra_uncore_dmi_reg_rdata <= cptra_uncore_dmi_unlocked_reg_en ? cptra_uncore_dmi_unlocked_reg_rdata_in :
+ cptra_uncore_dmi_locked_reg_en ? cptra_uncore_dmi_locked_reg_rdata_in : cptra_uncore_dmi_reg_rdata;
+
+ cptra_uncore_dmi_reg_dout_access_f <= cptra_uncore_dmi_locked_reg_en & ~cptra_uncore_dmi_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DOUT);
+ cptra_uncore_dmi_reg_din_access_f <= cptra_uncore_dmi_locked_reg_en & cptra_uncore_dmi_reg_wr_en & (cptra_uncore_dmi_reg_addr == DMI_REG_MBOX_DIN);
end
end
diff --git a/src/soc_ifc/tb/fuse_reg_pauser_test.svh b/src/soc_ifc/tb/fuse_reg_pauser_test.svh
index 6a8a979fa..ffc535c34 100644
--- a/src/soc_ifc/tb/fuse_reg_pauser_test.svh
+++ b/src/soc_ifc/tb/fuse_reg_pauser_test.svh
@@ -21,30 +21,26 @@ logic [31:0] fuse_uds_seed [0:11];
logic [31:0] fuse_field_entropy [0:7];
logic [31:0] fuse_key_manifest_pk_hash [0:11];
logic [3:0] fuse_key_manifest_pk_hash_mask;
-logic [31:0] fuse_owner_pk_hash [0:11];
logic [31:0] fuse_fmc_key_manifest_svn;
logic [31:0] fuse_runtime_svn [0:3];
logic fuse_anti_rollback_disable;
logic [31:0] fuse_idevid_cert_attr [0:23];
logic [31:0] fuse_idevid_manuf_hsm_id [0:3];
-logic [1:0] fuse_life_cycle ;
-logic fuse_lms_verify ;
logic [31:0] fuse_lms_revocation;
+logic [31:0] fuse_mldsa_revocation;
`FORLOOP_COMB( 12 ) fuse_uds_seed[j] = `REG_HIER_PFX.fuse_uds_seed[j].seed.value;
`FORLOOP_COMB( 8 ) fuse_field_entropy[j] = `REG_HIER_PFX.fuse_field_entropy[j].seed.value;
`FORLOOP_COMB( 12 ) fuse_key_manifest_pk_hash[j] = `REG_HIER_PFX.fuse_key_manifest_pk_hash[j].hash.value;
always_comb fuse_key_manifest_pk_hash_mask = `REG_HIER_PFX.fuse_key_manifest_pk_hash_mask.mask.value;
-`FORLOOP_COMB( 12 ) fuse_owner_pk_hash[j] = `REG_HIER_PFX.fuse_owner_pk_hash[j].hash.value;
always_comb fuse_fmc_key_manifest_svn = `REG_HIER_PFX.fuse_fmc_key_manifest_svn.svn.value;
`FORLOOP_COMB( 4 ) fuse_runtime_svn[j] = `REG_HIER_PFX.fuse_runtime_svn[j].svn.value;
always_comb fuse_anti_rollback_disable = `REG_HIER_PFX.fuse_anti_rollback_disable.dis.value;
`FORLOOP_COMB( 24 ) fuse_idevid_cert_attr[j] = `REG_HIER_PFX.fuse_idevid_cert_attr[j].cert.value;
`FORLOOP_COMB( 4 ) fuse_idevid_manuf_hsm_id[j] = `REG_HIER_PFX.fuse_idevid_manuf_hsm_id[j].hsm_id.value;
- always_comb fuse_life_cycle = `REG_HIER_PFX.fuse_life_cycle.life_cycle.value;
- always_comb fuse_lms_verify = `REG_HIER_PFX.fuse_lms_verify.lms_verify.value;
always_comb fuse_lms_revocation = `REG_HIER_PFX.fuse_lms_revocation.lms_revocation.value;
+ always_comb fuse_mldsa_revocation = `REG_HIER_PFX.fuse_mldsa_revocation.mldsa_revocation.value;
//----------------------------------------------------------------
@@ -265,7 +261,7 @@ endtask // fuse_reg_pauser_test
//----------------------------------------------------------------
// function get_fuse_regval()
//
-// Probes to get the intenral fuse register value inside dut
+// Probes to get the internal fuse register value inside dut
//----------------------------------------------------------------
function dword_t get_fuse_regval(string rname);
@@ -274,16 +270,15 @@ function dword_t get_fuse_regval(string rname);
automatic int j;
strq_t prefixes = {"FUSE_UDS_SEED", "FUSE_FIELD_ENTROPY", "FUSE_KEY_MANIFEST_PK_HASH",
- "FUSE_OWNER_PK_HASH", "FUSE_RUNTIME_SVN", "FUSE_IDEVID_CERT_ATTR", "FUSE_IDEVID_MANUF_HSM_ID"};
+ "FUSE_RUNTIME_SVN", "FUSE_IDEVID_CERT_ATTR", "FUSE_IDEVID_MANUF_HSM_ID"};
begin
case (rname)
"FUSE_KEY_MANIFEST_PK_HASH_MASK" : regval = fuse_key_manifest_pk_hash_mask;
"FUSE_FMC_KEY_MANIFEST_SVN" : regval = fuse_fmc_key_manifest_svn;
"FUSE_ANTI_ROLLBACK_DISABLE" : regval = fuse_anti_rollback_disable;
- "FUSE_LIFE_CYCLE" : regval = fuse_life_cycle ;
- "FUSE_LMS_VERIFY" : regval = fuse_lms_verify ;
"FUSE_LMS_REVOCATION" : regval = fuse_lms_revocation;
+ "FUSE_MLDSA_REVOCATION" : regval = fuse_mldsa_revocation;
default: begin
foreach (prefixes[i]) begin
@@ -302,7 +297,6 @@ function dword_t get_fuse_regval(string rname);
regval = (pfx == "FUSE_UDS_SEED" ) ? fuse_uds_seed[j]:
(pfx == "FUSE_FIELD_ENTROPY" ) ? fuse_field_entropy[j] :
(pfx == "FUSE_KEY_MANIFEST_PK_HASH") ? fuse_key_manifest_pk_hash[j] :
- (pfx == "FUSE_OWNER_PK_HASH" ) ? fuse_owner_pk_hash[j] :
(pfx == "FUSE_RUNTIME_SVN" ) ? fuse_runtime_svn[j] :
(pfx == "FUSE_IDEVID_CERT_ATTR" ) ? fuse_idevid_cert_attr[j] :
(pfx == "FUSE_IDEVID_MANUF_HSM_ID" ) ? fuse_idevid_manuf_hsm_id[j] : 'x;
diff --git a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
index 2fcf9119f..bf1e83ff6 100644
--- a/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
+++ b/src/soc_ifc/tb/soc_ifc_tb_pkg.sv
@@ -108,10 +108,11 @@ package soc_ifc_tb_pkg;
"CPTRA_WDT_TIMER2_TIMEOUT_PERIOD" : 2,
"CPTRA_WDT_CFG" : 2,
"CPTRA_RSVD_REG" : 2,
+ "CPTRA_OWNER_PK_HASH" : 12,
"FUSE_UDS_SEED" : 12,
"FUSE_FIELD_ENTROPY" : 8,
"FUSE_KEY_MANIFEST_PK_HASH" : 12,
- "FUSE_OWNER_PK_HASH" : 12,
+ "FUSE_KEY_MANIFEST_PK_HASH_MASK" : 8,
"FUSE_RUNTIME_SVN" : 4,
"FUSE_IDEVID_CERT_ATTR" : 24,
"FUSE_IDEVID_MANUF_HSM_ID" : 4,
@@ -164,20 +165,20 @@ package soc_ifc_tb_pkg;
"CPTRA_ITRNG_ENTROPY_CONFIG_0" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_0, // 0x118 Caliptra iTRNG Entropy Configuration 0
"CPTRA_ITRNG_ENTROPY_CONFIG_1" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_ITRNG_ENTROPY_CONFIG_1, // 0x11c Caliptra iTRNG Entropy Configuration 1
"CPTRA_RSVD_REG" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_RSVD_REG_0, // 0x120 [2] Caliptra Reserved Registers
+ "CPTRA_OWNER_PK_HASH" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_OWNER_PK_HASH_0, // 0x140 [12] -
+ "CPTRA_OWNER_PK_HASH_LOCK" : SOCIFC_BASE + `SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK, // 0x170 [12] -
// 0x128..0x1fc
"FUSE_UDS_SEED" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_UDS_SEED_0, // 0x200 [12] Unique Device Secret
"FUSE_FIELD_ENTROPY" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FIELD_ENTROPY_0, // 0x230 [8] Field Entropy
"FUSE_KEY_MANIFEST_PK_HASH" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0, // 0x250 [12] -
- "FUSE_KEY_MANIFEST_PK_HASH_MASK" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK, // 0x280 -
- "FUSE_OWNER_PK_HASH" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_OWNER_PK_HASH_0, // 0x284 [12] -
+ "FUSE_KEY_MANIFEST_PK_HASH_MASK" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_0, // 0x280 -
"FUSE_FMC_KEY_MANIFEST_SVN" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_FMC_KEY_MANIFEST_SVN, // 0x2b4 -
"FUSE_RUNTIME_SVN" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_RUNTIME_SVN_0, // 0x2b8 [4] -
"FUSE_ANTI_ROLLBACK_DISABLE" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE, // 0x2c8 -
"FUSE_IDEVID_CERT_ATTR" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0, // 0x2cc [24] -
"FUSE_IDEVID_MANUF_HSM_ID" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0, // 0x32c [4] -
- "FUSE_LIFE_CYCLE" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LIFE_CYCLE, // 0x33c -
- "FUSE_LMS_VERIFY" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_VERIFY, // 0x340 -
- "FUSE_LMS_REVOCATION" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_REVOCATION, // 0x344 -
+ "FUSE_LMS_REVOCATION" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_LMS_REVOCATION, // 0x340 -
+ "FUSE_MLDSA_REVOCATION" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_MLDSA_REVOCATION, // 0x344 -
"FUSE_SOC_STEPPING_ID" : SOCIFC_BASE + `SOC_IFC_REG_FUSE_SOC_STEPPING_ID, // 0x348 -
// 0x34c..0x5fc
"INTERNAL_OBF_KEY" : SOCIFC_BASE + `SOC_IFC_REG_INTERNAL_OBF_KEY_0, // 0x600 [8] De-Obfuscation Key
@@ -291,15 +292,13 @@ package soc_ifc_tb_pkg;
"FUSE_FIELD_ENTROPY" : 32'hffff_ffff,
"FUSE_KEY_MANIFEST_PK_HASH" : 32'hffff_ffff ,
"FUSE_KEY_MANIFEST_PK_HASH_MASK" : 32'hf, // field 3:0
- "FUSE_OWNER_PK_HASH" : 32'hffff_ffff,
"FUSE_FMC_KEY_MANIFEST_SVN" : 32'hffff_ffff,
"FUSE_RUNTIME_SVN" : 32'hffff_ffff,
"FUSE_ANTI_ROLLBACK_DISABLE" : 32'h1, // field 0
"FUSE_IDEVID_CERT_ATTR" : 32'hffff_ffff,
"FUSE_IDEVID_MANUF_HSM_ID" : 32'hffff_ffff,
- "FUSE_LIFE_CYCLE" : 32'h3, // field 1:0
- "FUSE_LMS_VERIFY" : 32'h1, // field 0
"FUSE_LMS_REVOCATION" : 32'hffff_ffff,
+ "FUSE_MLDSA_REVOCATION" : 32'hf,
"FUSE_SOC_STEPPING_ID" : 32'hffff, // field 15:0
"CPTRA_HW_ERROR_" : 32'hffff_ffff, // FATAL, NON_FATAL, ENC
"CPTRA_FW_ERROR_" : 32'hffff_ffff, // FATAL, NON_FATAL, ENC
@@ -312,6 +311,8 @@ package soc_ifc_tb_pkg;
"CPTRA_FUSE_PAUSER_LOCK" : 32'h1,
"CPTRA_TIMER_CONFIG" : 32'hffff_ffff,
"CPTRA_WDT_CFG" : 32'hffff_ffff,
+ "CPTRA_OWNER_PK_HASH" : 32'hffff_ffff,
+ "CPTRA_OWNER_PK_HASH_LOCK" : 32'h1,
"INTERNAL_RV_MTIME" : 32'hffff_ffff, // for MTIME_L/H, MTIMECMP_L/H
"INTR_BRF_ERROR_INTERNAL_INTR_R" : 32'hff, // fields 5:0
"INTR_BRF_ERROR_INTERNAL_INTR_COUNT_R" : 32'hffff_ffff,
@@ -356,9 +357,9 @@ package soc_ifc_tb_pkg;
"CPTRA_WDT_STATUS" : (`SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK |
`SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK),
"CPTRA_FUSE_PAUSER_LOCK" : `SOC_IFC_REG_CPTRA_FUSE_PAUSER_LOCK_LOCK_MASK,
+ "CPTRA_OWNER_PK_HASH_LOCK" : `SOC_IFC_REG_CPTRA_OWNER_PK_HASH_LOCK_LOCK_MASK,
"FUSE_ANTI_ROLLBACK_DISABLE" : `SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE_DIS_MASK,
"FUSE_KEY_MANIFEST_PK_HASH_MASK" : `SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK_MASK_MASK,
- "FUSE_LIFE_CYCLE" : `SOC_IFC_REG_FUSE_LIFE_CYCLE_LIFE_CYCLE_MASK,
"FUSE_LMS_VERIFY" : `SOC_IFC_REG_FUSE_LMS_VERIFY_LMS_VERIFY_MASK,
"FUSE_SOC_STEPPING_ID" : `SOC_IFC_REG_FUSE_SOC_STEPPING_ID_SOC_STEPPING_ID_MASK,
"INTERNAL_ICCM_LOCK" : `SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK,
diff --git a/tools/scripts/reg_doc_gen.sh b/tools/scripts/reg_doc_gen.sh
index 56960b52b..f9b737eda 100755
--- a/tools/scripts/reg_doc_gen.sh
+++ b/tools/scripts/reg_doc_gen.sh
@@ -38,5 +38,4 @@ src/uart/data/uart.rdl
python3 tools/scripts/reg_doc_gen.py \
src/soc_ifc/rtl/caliptra_top_reg.rdl \
src/soc_ifc/rtl/soc_ifc_doc.rdl \
-src/soc_ifc/rtl/mbox_csr.rdl \
-src/soc_ifc/rtl/sha512_acc_csr_doc.rdl
+src/soc_ifc/rtl/mbox_csr.rdl
diff --git a/tools/scripts/reg_gen.py b/tools/scripts/reg_gen.py
index 2bb316453..37ad15844 100644
--- a/tools/scripts/reg_gen.py
+++ b/tools/scripts/reg_gen.py
@@ -42,8 +42,15 @@
import re
import rdl_post_process
+# Arg processing
+myargs = iter(sys.argv[1:])
+rdl_file = next(myargs)
+build_cov = 0
+if next(myargs,"empty") == "--cov":
+ build_cov = 1
+
#output directory for dumping files
-rtl_output_dir = os.path.abspath(os.path.dirname(sys.argv[1]))
+rtl_output_dir = os.path.abspath(os.path.dirname(rdl_file))
repo_root = os.environ.get('CALIPTRA_ROOT')
# Listener to retrieve the address width at the CPU IF and write as a param to the pkg
@@ -85,7 +92,7 @@ def get_regfile_name(self):
# Compile your RDL files
#compile the kv defines so that rdl files including kv controls have the definition
rdlc.compile_file(os.path.join(repo_root, "src/keyvault/rtl/kv_def.rdl"))
- rdlc.compile_file(sys.argv[1])
+ rdlc.compile_file(rdl_file)
# Elaborate the design
root = rdlc.elaborate()
@@ -100,14 +107,15 @@ def get_regfile_name(self):
# Export a UVM register model
exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/uvm"))
- exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_uvm.sv")
+ exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(rdl_file))[0]) + "_uvm.sv")
# The below lines are used to generate a baseline/starting point for the include files "_covergroups.svh" and "_sample.svh"
# The generated files will need to be hand-edited to provide the desired functionality.
- # Uncomment these lines and run this script directly on the target RDL file to generate the files.
-# exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/cov"))
-# exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_covergroups.svh")
-# exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/smp"))
-# exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_sample.svh")
+ # Run this script directly on the target RDL file, with the second argument "--cov" to generate the files.
+ if build_cov == 1:
+ exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/cov"))
+ exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(rdl_file))[0]) + "_covergroups.svh")
+ exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/smp"))
+ exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(rdl_file))[0]) + "_sample.svh")
# Traverse the register model!
walker = RDLWalker(unroll=True)