From 63d32bde3a2f89d4fea1940221a5b21fd2bc9ccb Mon Sep 17 00:00:00 2001
From: Jack Koenig <koenig@sifive.com>
Date: Fri, 9 Jul 2021 14:29:45 -0700
Subject: [PATCH] Fix chisel3 <> for Bundles that contain compatibility Bundles
 (Take 2) (#2031)

PR #2023 fixed a composition issue for chisel3 biconnects delegating to
FIRRTL partial connect when compatibility mode Bundles are elements of
chisel3 Bundles. It missed an important case though that caused
previously working code to break.

The bug is fixed by doing the automatic flipping for compatibility mode
Bundles that have "Input" as a direction in addition to those that are
"Flipped".

(cherry picked from commit 5183ef888274c1d9cc2e22aef95c0e90d86e5122)

# Conflicts:
#	src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
---
 .../src/main/scala/chisel3/internal/BiConnect.scala  |  3 ++-
 .../CompatibilityInteroperabilitySpec.scala          | 12 +++++++++++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala
index 76a831cb89a..714575a37b0 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala
@@ -122,9 +122,10 @@ private[chisel3] object BiConnect {
         if (notStrict) {
           // chisel3 <> is commutative but FIRRTL <- is not
           val flipped = {
+            import ActualDirection._
             // Everything is flipped when it's the port of a child
             val childPort = left_r._parent.get != context_mod
-            val isFlipped = left_r.direction == ActualDirection.Bidirectional(ActualDirection.Flipped)
+            val isFlipped = Seq(Bidirectional(Flipped), Input).contains(left_r.direction)
             isFlipped ^ childPort
           }
           val (newLeft, newRight) = if (flipped) pair.swap else pair
diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
index 17d933bb75d..30926910f72 100644
--- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala
@@ -294,17 +294,27 @@ class CompatibiltyInteroperabilitySpec extends ChiselFlatSpec {
     compile {
       object Compat {
         import Chisel._
-        class Foo extends Bundle {
+        class BiDir extends Bundle {
           val a = Input(UInt(8.W))
           val b = Output(UInt(8.W))
         }
+        class Struct extends Bundle {
+          val a = UInt(8.W)
+        }
       }
       import chisel3._
       import Compat._
       class Bar extends Bundle {
+<<<<<<< HEAD
         val foo1 = new Foo
         val foo2 = Flipped(new Foo)
         override def cloneType = (new Bar).asInstanceOf[this.type]
+=======
+        val bidir1 = new BiDir
+        val bidir2 = Flipped(new BiDir)
+        val struct1 = Output(new Struct)
+        val struct2 = Input(new Struct)
+>>>>>>> 5183ef88 (Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031))
       }
       // Check every connection both ways to see that chisel3 <>'s commutativity holds
       class Child extends RawModule {