Features of the new ChiselSim

[rameloni]

Hello, I have just read #3746 (comment) that chiseltest was not intended to be used after chisel 3.6 due to the migration to llvm/circt from SFC.

I was wondering what the features supported by ChiselSim are. For example, is there a way to dump trace waveform files? What are the backend simulators supported?

I am currently working on my thesis project, and my project relies on improving chisel testing and waveform viewers in the Tydi-Chisel context (I thought to use chiseltest as a starting point but now I think I need to study and test chiselSim first).

[seldridge]

ChiselSim only currently gives you that EphemeralSimulator environment which writes all results to a temporary directory. This is good enough for simple "check that it works" tests. This is missing an environment which writes outputs to a build area so you can inspect them. This other environment is needed. Once that is there, then waveform support can be added.

Separate from that, there needs to be more APIs for interacting with the DUT in more interesting ways. Namely, abilities to interact with Valid, Decoupled, and Irrevocable interfaces. ChiselTest provided enqueueSeq/dequeueSeq for this. There is also fork/join support. All of this can be added to ChiselSim in a mostly straightforward way.

Supported simulators (currently) are Verilator and VCS. There is a lot of work going on in llvm/circt on ARC dialect and arcillator. These allow you to go directly from core CIRCT dialects to LLVM IR and get a compiled simulation. This is expected to be an additional backend for ChiselSim once it is ready. Because the ARC flow targets LLVM IR, you will theoretically be able to have both JIT-compiled and interpreted versions of this. I.e., this is intended to be a Treadle-replacement and result in higher performance for small tests.

What is not supported in ChiselSim are ChiselTest's formal flows. These flows were built using custom passes and backends for SFC and cannot be decoupled from SFC without porting these to MFC. That said, Chisel 6 has support for more flavors of assertions and is closer to providing full SVA property support via chisel3.ltl (linear temporal logic) package. E.g., Chisel 6 allows you to generate SystemVerilog like assert property (s_eventually a |-> a ##1 b) (see: https://github.com/llvm/circt/blob/8a10c504e80d6b169351be4ff95d97a20a78f495/test/firtool/verif.fir#L52). This is more powerful, but also more manual. You would need to generate your Verilog and then run it through a formal tool yourself as opposed to the integrated solution that ChiselTest provides. There are three avenues of support here: (1) add the ability to have a formal test in ChiselSim, (2) efforts to do formal checking directly in CIRCT (see: circt-lec llvm/circt#3991), and (3) the ability to emit BTOR2 directly from CIRCT (llvm/circt#6378) which starts to replicate how ChiselTest approached the problem with SFC.