From 92e24774e1f3c80d8974efecf045affda0c9c5a1 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 5 Feb 2020 21:58:57 -0800 Subject: [PATCH 1/4] Printf: Add support for tabs, and give helpful error messages --- chiselFrontend/src/main/scala/chisel3/Printf.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/chiselFrontend/src/main/scala/chisel3/Printf.scala b/chiselFrontend/src/main/scala/chisel3/Printf.scala index b80d5eb5406..5003d9801a0 100644 --- a/chiselFrontend/src/main/scala/chisel3/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel3/Printf.scala @@ -19,13 +19,15 @@ object printf { // scalastyle:ignore object.name require(formatIn forall (c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values") def escaped(x: Char) = { - require(x.toInt >= 0) + require(x.toInt >= 0, s"char ${x} to Int ${x.toInt} must be >= 0") if (x == '"' || x == '\\') { s"\\${x}" } else if (x == '\n') { "\\n" - } else { - require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved + } else if (x == '\t') { + "\\t" + }else { + require(x.toInt >= 32, s"char ${x} to Int ${x.toInt} must be >= 32") // TODO \xNN once FIRRTL issue #59 is resolved x } } From effb797bc4370f1e1475c8bec69af6fb4d942f9f Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 6 Feb 2020 21:18:31 -0800 Subject: [PATCH 2/4] Update chiselFrontend/src/main/scala/chisel3/Printf.scala Co-Authored-By: Jack Koenig --- chiselFrontend/src/main/scala/chisel3/Printf.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chiselFrontend/src/main/scala/chisel3/Printf.scala b/chiselFrontend/src/main/scala/chisel3/Printf.scala index 5003d9801a0..0478e8899ea 100644 --- a/chiselFrontend/src/main/scala/chisel3/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel3/Printf.scala @@ -26,7 +26,7 @@ object printf { // scalastyle:ignore object.name "\\n" } else if (x == '\t') { "\\t" - }else { + } else { require(x.toInt >= 32, s"char ${x} to Int ${x.toInt} must be >= 32") // TODO \xNN once FIRRTL issue #59 is resolved x } From fdb4f72557a1c1bdc814aea1663513501836a36a Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 6 Feb 2020 21:23:43 -0800 Subject: [PATCH 3/4] Add a test for tab to PrintableSpec --- src/test/scala/chiselTests/PrintableSpec.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index aeb92532f22..a977387f29d 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -95,6 +95,16 @@ class PrintableSpec extends FlatSpec with Matchers { case e => fail() } } + it should "correctly emit tab" in { + class MyModule extends BasicTester { + printf(p"\t") + } + val firrtl = Driver.emit(() => new MyModule) + getPrintfs(firrtl) match { + case Seq(Printf("\t", Seq())) => + case e => fail() + } + } it should "support names of circuit elements including submodule IO" in { // Submodule IO is a subtle issue because the Chisel element has a different // parent module From 29fc974d4b4237d69b67d6dc50e3589d784db4e4 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 7 Feb 2020 16:44:45 -0800 Subject: [PATCH 4/4] update test for tabs in PrintableSpec.scala --- src/test/scala/chiselTests/PrintableSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index a977387f29d..4ecc073efd5 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -101,7 +101,7 @@ class PrintableSpec extends FlatSpec with Matchers { } val firrtl = Driver.emit(() => new MyModule) getPrintfs(firrtl) match { - case Seq(Printf("\t", Seq())) => + case Seq(Printf("\\t", Seq())) => case e => fail() } }