From 91e848f15c15bacc89e060e23b9304ee488697a2 Mon Sep 17 00:00:00 2001 From: Steve Burns Date: Tue, 2 Oct 2018 09:01:01 -0700 Subject: [PATCH 1/2] Modify noenq to set the input wires to DontCare. --- src/main/scala/chisel3/util/Decoupled.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index b90e87aca66..3722b9cfcc8 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -51,6 +51,7 @@ object ReadyValidIO { */ def noenq(): Unit = { target.valid := false.B + target.bits := DontCare } /** Assert ready on this port and return the associated data bits. From ec2400ec2fff901ac9bb175512927a50ab0fee22 Mon Sep 17 00:00:00 2001 From: edwardcwang Date: Wed, 3 Oct 2018 12:00:07 -0700 Subject: [PATCH 2/2] Comment nitpicks --- src/main/scala/chisel3/util/Decoupled.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 3722b9cfcc8..88ccd8926be 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -36,7 +36,7 @@ object ReadyValidIO { implicit class AddMethodsToReadyValid[T<:Data](target: ReadyValidIO[T]) { def fire(): Bool = target.ready && target.valid - /** push dat onto the output bits of this interface to let the consumer know it has happened. + /** Push dat onto the output bits of this interface to let the consumer know it has happened. * @param dat the values to assign to bits. * @return dat. */ @@ -47,7 +47,7 @@ object ReadyValidIO { } /** Indicate no enqueue occurs. Valid is set to false, and bits are - * connected to an uninitialized wire + * connected to an uninitialized wire. */ def noenq(): Unit = { target.valid := false.B @@ -56,14 +56,14 @@ object ReadyValidIO { /** Assert ready on this port and return the associated data bits. * This is typically used when valid has been asserted by the producer side. - * @return the data for this device, + * @return The data bits. */ def deq(): T = { target.ready := true.B target.bits } - /** Indicate no dequeue occurs. Ready is set to false + /** Indicate no dequeue occurs. Ready is set to false. */ def nodeq(): Unit = { target.ready := false.B