Chisel v3.4.1

Highlights

• Repo moved to https://github.com/chipsalliance
• Naming improvements
  • More naming enhancements and performance improvements when using features with large designs (#1606) (#1617) (#1628)
  • When prefixing with a data, eagerly get local name (#1614)
  • Use Data refs for name prefixing with aggregate elements (#1616)
  • Added Force Name API (#1634)
  • Refine autonaming to have more intuitive behavior, Last name in an Expression wins, while the first Statement to name wins(#1660)

Fixes

• Provide user source locators in Builder.error errors (#1618)
• Enable Cat of Zero Element Vec (#1623) (#1627)
• Fixed package chisel3 to improve the pointing of reported errors (#1621)
• Make "(one file per module)" -e option work properly (#1630) (#1631)
• Bugfix - module name collision for injecting aspect (#1635)
• Fix bug where refs may not get set for Records (#1645)
• Bugfix - adding external modules was broken (#1649)
• Fixed ExtModule's lack of support built in support for providing verilog source (#1154)
• Change to use .transform as the correct API for ChiselStage (#1651)
• SeqUtils asUInt endian-ness: hi/lo instead of right/left (#1647)
• For HasId.setRef, have first set win (with force override) (#1655)

Miscellany

• Fixes to mdoc (#1600)
• Move Chisel3 to SPDX license conventions (#1604)
• Move more docs as part of CI process (#1601)
• Add MiMa binary compatibility checking to 3.4.x (#1608)
• Waive MiMa failures on package private methods (#1615)
• Add additional function for backwards compatibility. (#1639)
• Ignore tests using System.setSecurityManager, caused problems in test suite (#1661)

Documentation

• Fix website building issues, delete index.md (#1613)
• Fixed broken link to type hierarchy diagram (#1611)
• Fix crosslinks in mdoc. Can't use md suffix (#1640)
• Fix broken links in docs (#1643) (#1644)
• Update some README links to chipsalliance (#1673) (#1681)
• Updated readme: simplify sbt snippet and update to the latest stable release (#1686) (#1687)

Chisel v3.4.0

Highlights

• A new Chisel compiler plug-in significantly improves generated names (#1448)

Generated names can be automatically prefixed with names based on their use and scope. Users
have new options to control naming. These names will be more stable as changes are made to generators.

• There is a new basic model checking API (#1499)

Adds assert(), assume(), cover() statements to a new chisel3.experimental.verification library.
These statements generate their FIRRTL counterparts, which in turn emit their Verilog counterparts.
Note that only SystemVerilog's immediate statements are supported.
These new statements form the foundation of a new model checking interface that may be extended in future releases.

• Upgrade FIRRTL to v1.4.0. See the release notes.

Deprecations

• Move LFSR16 to Compatibility Mode (Deprecated in 3.2), - Remove deprecated LFSR16 utility (#1476)
• Deprecate Module.io and BlackBox.io virtual methods (future 2.13 compatibility) (#1550)
• Remove use of deprecated PreservesAll, cleanup dependencies, all phases are converted to be more canonical in there specification of dependencies (#1558)
• Restore and deprecate Chisel.Driver, until we also remove underlying chisel3.Driver (#1571)
• Bump 'removed in 3.3' deprecations to 3.4 (#1439)
• Remove Deprecated Usages of chisel3.Driver, CircuitForm (#1481)
• (#1551) Deprecate support for Scala 2.11

API Modification

• Better Building of FIRRTL From Source, Use sbt-sriracha for firrtl and treadle source deps (#1563)

• Add new annotation for Chisel Circuit serialization, --chisel-output-file is added to the ChiselCli. (#1580)

Fixes

• Relax plugin scalac phase order (#1568)

• Switch to HowToSerialize for Emission (#1405)

  Fix emit{Firrtl,Verilog} for CustomFileEmission
  Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
  Verilog (emitVerilog) to look for Circuit and Verilog annotations
  instead of DeletedAnnotations. This is needed after migrating to the
  CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
  emitter annotations.

• update Select.get(IntermediateAnd)Leafs to work with records (#1525)

• Allow a counter to be manually reset (#1527)

• Check whether signals escape their when scopes, Include and check when scoping as part of reg/mem/wire/node bindings (#1518)

• bug fix for build.sc (#1579)

Feature

• Allow a counter to be instantiated using a Scala range (#1515)
• Canonicalize construction of Decoupled with no payload (#785)
• Memoize the hashcode of the ChiselCircuitAnnotation, improves performance of multi-phase generators (#1485)
• Grouping Chisel API, added a chisel annotation API for triggering the firrtl.transforms.GroupComponents transformation. (#1073)
• Add support for ScalaFix. (#1203)
• Provide an implementation of litOption() for BundleLits (#1280)
• Chisel3 can use treadle to run tests (faster), only depends on Treadle dependency in tests (#1554)
• make parameters for util modules public (#1452)
• Recursively generate one-hot multiplexers for aggregates (#1557)
• Move multi-clock to explanations (#1561)
• Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ChiselStage$ helpers (#1566)
• Add chisel plugin to mill build system. This enables better, more stable naming capabilities in Chisel3 (#1572)
• Add documentation of new plugin. (#1573)
• Fix load memory from file to work with binary (#1583)
• Improved speed of ChiselPlugin (#1590)
• Support using switch without importing SwitchContext (#1595)
• Added website docs and mdoc. (#1560)
  Added living documentation with repository. This will enable us to enforce better documentation of new features as part of their upstream process.

Miscellany

The removal of unstable methods from chisel3.core from the public API has been delayed. They will be removed with the version 3.4.0 release.

• README: add link to website source. Now easier to figure out how to help enhance the content (#1420)(#1570)
• Updated PR template to include checklist and documentation updates (#1562)
• Update sbt-site to 1.4.0 (#1395)
• Update scalacheck-1-14 to 3.1.1.1 (#1413)
• Update sbt to 1.3.10 (#1415)
• Update Mergify rules to backport to 3.3.x (#1429)
• Update scalatest 3.1.2 (#1430)
• verilator_4_016 --> v4.016 (#1459)
• Restore backporting to 3.2.x (#1460)
• Have defaultVersions specify complete ModuleIDs. (#1479)
• Fix Mergify Backport labeling for 3.2.x (#1489)
• Don't run FIRRTL in FlattenSpec's ChiselStage (#1493)
• Add .scala-steward.conf (#1495)
• fix treadle dependency for mill (#1504)
• Update Development Meetings Info (#1511)
• Add Treadle to CI builds (#1516)
• Update build instructions in README (#1524)
• Instance API for Importing Modules (#1530)
• Select: update to work with records, Instances work, next need to add plugin (#1525)
• Update OneHot.scala (#1539)
• Remove ChiselLegacyAnnotation It was private and unused (#1544)
• Bump Scala to 2.12.12 (#1553)

v3.4.0-RC1

API Modification

(#1476) Move LFSR16 to Compatibility Mode (Deprecated in 3.2), - Remove deprecated LFSR16 utility
(#1550) Deprecate Module.io and BlackBox.io virtual methods (future 2.13 compatibility)

Fix

(#1425) Report Builder.error errors as exceptions outside hardware context
Some errors that were previously hidden when calling Chisel API methods outside of an active hardware generation context (see #1422) will now be immediately thrown as exception.

(#1426) Fix Double Elaboration Backportably
Fix double elaboration
Expose ChiselStage's PhaseManager, rm extra wraps
Remove the requirement that FirrtlStage runs elaboration (this should
be implicit) and remove the unneeded invalidation of elaboration by
the Emitter. Due to Convert currently NOT invalidating Elaborate (when
it should), add an optionalPrerequisiteOf to ensure that the Emitter
runs before the Convert phase.

(#1480) Fix broken auto-clonetype on Scala 2.11.12 and add test

(#1496) Fix TesterDriver.scala regression #1481

(#1538) Bug fix for manipulating submodules in aspects
Adds functionality for modules' parents to be translated into their corresponding aspect so they can be manipulated in an aspect that injects into the parent module.

(#1546) Counter.n API
Includes special case support for Counter(0) which has identical
behavior to Counter(1) except for the value of n.

(#1534) Add emitSystemVerilog method to ChiselStage
Adds a method for emitting SystemVerilog to the top level API, which previously required a workaround of a few lines of code.

Feature

(#1448) Improved Chisel Naming via Compiler Plugins + Prefixing

(#1499) Basic model checking API
Adds assert(), assume(), cover() statements to a new chisel3.experimental.verification library. These statements generate their FIRRTL counterparts, which in turn emit their Verilog counterparts. Note that only SystemVerilog's immediate statements are supported. These new statements form the foundation of a new model checking interface that may be extended in future releases.

• Add check(...) affordance
• Add assert (renamed from check and fixed)
• Add verification statements
• Move formal to experimental.verification

(#1515) Allow a counter to be instantiated using a Scala range

(#785) Canonicalize construction of Decoupled with no payload

(#1485) Memoize the hashcode of the ChiselCircuitAnnotation, improves performance of multi-phase generators

(#1073) Grouping Chisel API, added a chisel annotation API for triggering the firrtl.transforms.GroupComponents transformation.

(#1203) Add support for ScalaFix.

(#1280) Provide an implementation of litOption() for BundleLits

(#1405) Switch to HowToSerialize for Emission
Fix emit{Firrtl,Verilog} for CustomFileEmission
Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
Verilog (emitVerilog) to look for Circuit and Verilog annotations
instead of DeletedAnnotations. This is needed after migrating to the
CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
emitter annotations.

(#1525) update Select.get(IntermediateAnd)Leafs to work with records

(#1527) Allow a counter to be manually reset

(#1420) README: add link to website source. Now easier to figure out how to help enhance the content

(#1518) Check whether signals escape their when scopes
Include and check when scoping as part of reg/mem/wire/node bindings
Allow outdated 'when' behavior of CHIRRTL memory ports with enables
Extend cross-module / when-visibility checks to all data refs

• E.g. delayed evaluation of printf / assert args
• Remove illegal cross-module references from existing tests
  Add basic test cases for cross-module refs / signals escaping when scopes

(#1554) Chisel3 can use treadle to run tests (faster), only depends on Treadle dependency in tests
Makes TesterDriver Backend API extensible, then define a TreadleBackend in the test project

Miscellany

(#1439) Bump 'removed in 3.3' deprecations to 3.4
The removal of unstable methods from chisel3.core from the public API has been delayed. They will be removed with the version 3.4.0 release.

(#1395) Update sbt-site to 1.4.0
(#1413) Update scalacheck-1-14 to 3.1.1.1
(#1415) Update sbt to 1.3.10
(#1429) Update Mergify rules to backport to 3.3.x
(#1430) Update scalatest 3.1.2

(#1459) verilator_4_016 --> v4.016
(#1460) Restore backporting to 3.2.x
(#1479) Have defaultVersions specify complete ModuleIDs.
(#1481) Remove Deprecated Usages of chisel3.Driver, CircuitForm
(#1489) Fix Mergify Backport labeling for 3.2.x
(#1493) Don't run FIRRTL in FlattenSpec's ChiselStage
(#1495) Add .scala-steward.conf
(#1504) fix treadle dependency for mill
(#1511) Update Development Meetings Info
(#1516) Add Treadle to CI builds
(#1524) Update build instructions in README
(#1530) Instance API for Importing Modules
(#1525) Select: update to work with records, Instances work, next need to add plugin
(#1539) Update OneHot.scala
(#1544) Remove ChiselLegacyAnnotation It was private and unused
(#1551) Deprecate support for Scala 2.11
(#1553) Bump Scala to 2.12.12

v3.3.2

(#1461) Bump Mima check to 3.3.1
(#1464) Change verilator version from verilator_4_016 --> v4.016
(#1469) Grouping Chisel API (bp #1073)
(#1468) Added Group API Chisel API (bp #1073)
(#1470) Report Builder.error errors as exceptions outside hardware context
(#1487) Memoize the hashcode of the ChiselCircuitAnnotation
(#1488) Bump 'removed in 3.3' deprecations to 3.4
(#1491) Canonicalize construction of Decoupled with no payload
(#1492) Remove Deprecated Usages of chisel3.Driver, CircuitForm
(#1498) Fix TesterDriver.scala regression #1481

v3.2.7

(#1462) Bump Mima check to 3.2.6
(#1463) Change verilator version name verilator_4_016 --> v4.016
(#1468) Added Group API Chisel API (bp #1073)
(#1486) Memoize the hashcode of the ChiselCircuitAnnotation
(#1490) Canonicalize construction of Decoupled with no payload

v3.3.1

Fix

(#1431) Fix Double Elaboration Backportably (bp #1426)

Feature

(#1428) [3.3.x] Add binary compatibility checking to CI
(#1437) Update sbt-site to 1.4.0 (bp #1395)
(#1438) Update scalacheck-1-14 to 3.1.1.1 (bp #1413)
(#1440) Update sbt to 1.3.10 (bp #1415)
(#1442) Scala steward+1432 - Update scalatest to 3.1.2 (bp #1441)

v3.2.6

Feature

(#1392) Java API Documents Linking (bp #1367)
(#1416) Add tests for async reset regs of non-UInt types (bp #1414)

v3.3.0

API Modification

(#1201) Don't use MuxLookup default for full mapping
(#1315) Emit FIRRTL andr, orr for Bits.{andR, orR}
(#1359) Cleanup aspects
(#1384) No more compile internal

Fix

(#1136) Make Queue.irrevocable work properly in chisel3 - Close #1134
(#1224) Improve naming of anonymous/class-in-function Modules
(#1246) Fix mergify to backports: omit jenkins CI
(#1252) Fix bidirectional Wire with Analog
(#1256) Fix deprecation warning that leaks into user code
(#1258) Fix asTypeOf for Clock
(#1274) Bug fixes to support code for Interval
(#1275) Fixed problem creating Interval literals with full ranges
(#1283) BitPat supports whitespace and underscores
(#1294) Fixed code example typo in comment
(#1303) Bugfix: Select.instances now works with blackboxes
(#1324) fix mill build
(#1336) Fix := of Reset and AsyncReset to DontCare
(#1346) Patch fix #1109
(#1374) Dont wrap elaboration annotations
(#1380) Use innermost builder cause to trim stack trace
(#1387) Propagate user compile options for Chisel.Module
(#1399) Fix mill build

Feature

(#1180) Add brief description of (current) chisel versioning and version recommendations.
(#1183) Add read-under-write parameter to SyncReadMem
(#1209) Enable @chiselName on non-module classes
(#1213) Deprecate Driver methods in favor of ChiselStage
(#1215) Add ChiselEnum to BundleLiterals
(#1225) Support literals cast to aggregates as async reset reg init values
(#1227) Bump master SNAPSHOT version.
(#1236) Add MiMa and CI checks for binary compatibility
(#1237) Remove over design
(#1239) Improve error message when assigning from Seq to Vec
(#1243) Add CCC20 Info at README top
(#1244) Create .mergify.yml
(#1253) Compat compile options macro
(#1260) Update README to reflect CCC20 Extension
(#1264) Remove Jenkins CI from .mergify.yml
(#1268) Revert "Compat compile options macro"
(#1270) Migrate to Dependency Wrapper
(#1273) Remove unused WriteEmitted phase
(#1277) Band aid until litOption is implemented for Aggregates.
(#1284) Provides Double and BigDecimal methods to access literal values for FixedPoint and Interval
(#1285) Add method asBool to Clock.
(#1296) Remove redundancy code
(#1305) specifying type of targets field in ChiselStage
(#1308) Change when/switch thunk type to Any
(#1309) Big decimal methods for num types.2
(#1318) Add Scaladoc about RegNext Unset/Inferred Widths
(#1325) README: have a link to the classic tutorial
(#1326) Printf: Add support for tabs, and give helpful error messages (#1323)
(#1329) Clone child elements lazily in Vec
(#1332) Bump sbt and tool/plugin dependencies.
(#1340) Update sbt-site to 1.3.3
(#1341) Update junit to 4.13
(#1342) Update paradise to 2.1.1
(#1345) Upcoming Events: Remove CCC, add Dev Meetings
(#1356) sbt compatible publish for mill
(#1357) add testOnly
(#1360) Make implicit clock and reset final vals
(#1361) Provide API to set concrete type of implicit reset
(#1365) Retain default version assignment
(#1367) Java API Documents Linking
(#1372) Make mergify open backport PRs & signal on failed cherry-picks
(#1373) [mergify] Update match string for labeling backported PRs
(#1377) Remove toNamed (and friends) deprecation.
(#1382) Set StageError cause in ChiselStage
(#1383) Add NoChiselNamePrefix to ignore instances in @chiselName
(#1389) Bump to Scala 2.12.11
(#1390) Add publishSettings to subprojects.
(#1394) Scalasteward scalatest 3.1.0
(#1397) Mux1H: note results unspecified unless exactly one select signal is high
(#1400) Change BundleLiteral to RecordLiteral
(#1402) expose typeEquivalent
(#1404) Use thread local storage for ChiselContext.
(#1408) Make Counter emit valid FIRRTL
(#1414) Add tests for async reset regs of non-UInt types
(#1417) Revert "Make uselessly public fields in utils private"

v3.3.0-RC3

Fix

(#1408) Make Counter emit valid FIRRTL

Feature

(#1394) Scalasteward scalatest 3.1.0
(#1397) Mux1H: note results unspecified unless exactly one select signal is high
(#1402) expose typeEquivalent
(#1414) Add tests for async reset regs of non-UInt types
(#1417) Revert "Make uselessly public fields in utils private"

v3.2.5

Fix

(#1407) Use thread local storage for ChiselContext. (#1404) Fixes #1334
(#1411) Make Counter emit valid FIRRTL (bp #1408)

Feature

(#1375) Update MiMa check to include all 3.2.x releases
(#1378) Don't wrap elaboration annotations (bp #1374)
(#1381) Use innermost builder cause to trim stack trace (bp #1380)
(#1388) Propagate user compile options for Chisel.Module (bp #1387)