v3.0-SNAPSHOT_2017-06-22

• Fix a small typo in the README (#627)
• Add dontTouch for annotating Data to not be removed (#620)
• Don't try to instantiate firrtl.Transform from Annotation (#620)

v3.0-SNAPSHOT_2017-05-30

• Correct misleading example code
• Support updated scalatest/scalacheck; bump sbt and Scala versions. (#605)
• Update comments describing Decoupled/ReadyValid - fix #437. (#493)

v3.0-SNAPSHOT_2017-05-25

• Update internal Pipe wiring - fixes #615 (#616)

v3.0-SNAPSHOT_2017-05-16

• Changed multiplication of SInt and UInt (#611)
• Scope resources - move them down into chisel3 directory - fixes #549 (#610)
• Add implicit CompileOptions to Record and Bundle (#595)
• Connecting basic types wrong should error in chisel (#497)
• Clear clock and reset scope for RawModule (#607)

v3.0-SNAPSHOT_2017-05-03

• Update instructions for installing firrtl. (#597)
• Deprecate fromBits and clock/reset constructors (#583)
• Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)
• Remove explicit import of NotStrict - fixes #492 (#494)
• Remove VecLike/IndexedSeq from Mem type (#589)
• Fix assignment from 0-entry Vec: add test (#580)
• Fix macOS install instructions for homebrew package manager (#575)
• Module Hierarchy Refactor (#469)
• Fix one hot mux (#573)
• Change Enum to emit minimum widths of 1 (#574)

v3.0-SNAPSHOT_2017-04-12

• Use input element to decide if Vec of values has direction. (#570)
• Define CompileOptions case class to support CompileOptions manipulation. (#572)
• Make Module instantiations draw clock from Builder instead of parent (#568)
• Creating FixedPoint literals was throwing away width when specifically provided. This caused one hot muxing problems in dsptools FixedPoint spec fixed based on error uncovered by this change. (#564)
• Support Vec(0) fields in Bundles, just like Option[Data]; add test (#562)
• Fix getWidth on empty Vecs; add test (#561)
• Fixed fix, allow Mux of different binary points and widths (#559)

v3.0-SNAPSHOT_2017-03-23

• The register creation API has been changed to offer clearer functional choices. (#553)
  • RegInit should be used to create a register with a specified initializer.
  • RegNext should be used to create a register with a specified next value.
• log2Up and log2Down have been deprecated, users should now use log2Ceil and log2Floor. Internal references to these functions have been fixed.. (#528)
• QueueIO and ArbiterIO work proper when given zero entries.
• Support has been added for field names that begin with a number in the new aggregate type Record. (#531)
• New warnings on inappropriate parameters for a number of chisel constructs. (#455)
  • Vec creation warns when type given is a literal. (#530)
• If OHToUInt is given only one argument it always returns that. (#546)
• Custom transforms are executed in the order they are specified in the options manager. (#532)
• ShiftRegister applies the enable to all registers created. (#370)
• Fixed a bug where compile errors were caused by assertions containing %. (#500)
• Fixed an an inconsistency in Chisel, a UInt -& UInt now returns an SInt. (#502)
• There is a new low level API for creating elements of a given type asTypeOf. (#450)
  • fromBits currently untouched but will be chisel3-deprecated if possible as a future PR.
  • Code that needs to create a super-type of several types into cloneSupertype See. #446
    • This should be the only thing that changes externally visible API, in that the checks are now more consistent.
    • oneHotMux now checks against inconsistent input types.
    • Mux now checks that each branch is of equivalent type.
  • Simplify Vec construction using above.
  • Move cloneTypeWidth from Data to Bits. It used to silently drop the width parameter when called on any non-Bits, this makes uses of it explicit and always correct, minus the Bool case.
  • Eventually want to get rid of cloneTypeWidth. The only stragglers are Bits.pad (which can instead create a new UInt/etc from scratch) and Reg (which clears widths behind the scenes for you). Not sure how to address the Reg case.
• Deprecate flatten, hopefully will remove it eventually using more local operations.