From 25a0500dca7e83381739483886c462d7a87721a0 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Tue, 18 Apr 2017 11:12:13 -0700
Subject: [PATCH] "Scope" test resource (top.cpp). (#398)

Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp.
---
 src/test/resources/{top.cpp => firrtl/testTop.cpp} | 0
 src/test/scala/firrtlTests/FirrtlSpec.scala        | 6 ++++--
 src/test/scala/firrtlTests/IntegrationSpec.scala   | 4 ++--
 src/test/scala/firrtlTests/StringSpec.scala        | 2 +-
 4 files changed, 7 insertions(+), 5 deletions(-)
 rename src/test/resources/{top.cpp => firrtl/testTop.cpp} (100%)

diff --git a/src/test/resources/top.cpp b/src/test/resources/firrtl/testTop.cpp
similarity index 100%
rename from src/test/resources/top.cpp
rename to src/test/resources/firrtl/testTop.cpp
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala
index 6bf73a800d..f77b47f314 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/FirrtlSpec.scala
@@ -16,7 +16,9 @@ import firrtl.annotations
 import firrtl.util.BackendCompilationUtilities
 
 trait FirrtlRunners extends BackendCompilationUtilities {
-  lazy val cppHarness = new File(s"/top.cpp")
+
+  val cppHarnessResourceName: String = "/firrtl/testTop.cpp"
+
   /** Compiles input Firrtl to Verilog */
   def compileToVerilog(input: String, annotations: AnnotationMap = AnnotationMap(Seq.empty)): String = {
     val circuit = Parser.parse(input.split("\n").toIterator)
@@ -64,7 +66,7 @@ trait FirrtlRunners extends BackendCompilationUtilities {
       annotations: AnnotationMap = new AnnotationMap(Seq.empty)) = {
     val testDir = compileFirrtlTest(prefix, srcDir, customTransforms, annotations)
     val harness = new File(testDir, s"top.cpp")
-    copyResourceToFile(cppHarness.toString, harness)
+    copyResourceToFile(cppHarnessResourceName, harness)
 
     // Note file copying side effect
     val verilogFiles = verilogPrefixes map { vprefix =>
diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala
index f4173143a4..6ac45b6de2 100644
--- a/src/test/scala/firrtlTests/IntegrationSpec.scala
+++ b/src/test/scala/firrtlTests/IntegrationSpec.scala
@@ -37,8 +37,8 @@ class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec {
     topFile should exist
 
     // Copy harness over
-    val harness = new File(testDir, s"top.cpp")
-    copyResourceToFile(cppHarness.toString, harness)
+    val harness = new File(testDir, s"testTop.cpp")
+    copyResourceToFile(cppHarnessResourceName, harness)
 
     // topFile will be compiled by Verilator command by default but we need to also include dutFile
     verilogToCpp(top, testDir, Seq(dutFile), harness).!
diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala
index b3f6523d95..7e7c040e5c 100644
--- a/src/test/scala/firrtlTests/StringSpec.scala
+++ b/src/test/scala/firrtlTests/StringSpec.scala
@@ -18,7 +18,7 @@ class PrintfSpec extends FirrtlPropSpec {
     val prefix = "Printf"
     val testDir = compileFirrtlTest(prefix, "/features")
     val harness = new File(testDir, s"top.cpp")
-    copyResourceToFile(cppHarness.toString, harness)
+    copyResourceToFile(cppHarnessResourceName, harness)
 
     verilogToCpp(prefix, testDir, Seq(), harness).!
     cppToExe(prefix, testDir).!