From 014eb9cb76c031ba4270bc012c244824cca78342 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 8 Dec 2016 10:10:46 -0800 Subject: [PATCH 1/2] "Scope" test resource (top.cpp). Jar resources (unlike classes) are typically not scoped. This can create collisions if we have similarly named resources in multiple jars, especially when merging multiple projects in an IDE. Give this resource a distinct name to avoid colliding with chisel3 top.cpp (and shouldn't that resource move to chisel-testers?). --- src/test/resources/{top.cpp => firrtl/testTop.cpp} | 0 src/test/scala/firrtlTests/FirrtlSpec.scala | 4 ++-- src/test/scala/firrtlTests/StringSpec.scala | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) rename src/test/resources/{top.cpp => firrtl/testTop.cpp} (100%) diff --git a/src/test/resources/top.cpp b/src/test/resources/firrtl/testTop.cpp similarity index 100% rename from src/test/resources/top.cpp rename to src/test/resources/firrtl/testTop.cpp diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index a2c880c3bb..db0a8efa0f 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -108,7 +108,7 @@ trait BackendCompilationUtilities { trait FirrtlRunners extends BackendCompilationUtilities { def parse(str: String) = Parser.parse(str.split("\n").toIterator, IgnoreInfo) - lazy val cppHarness = new File(s"/top.cpp") + val cppHarnessResourceName: String = "/firrtl/testTop.cpp" /** Compiles input Firrtl to Verilog */ def compileToVerilog(input: String, annotations: AnnotationMap = AnnotationMap(Seq.empty)): String = { val circuit = Parser.parse(input.split("\n").toIterator) @@ -155,7 +155,7 @@ trait FirrtlRunners extends BackendCompilationUtilities { annotations: AnnotationMap = new AnnotationMap(Seq.empty)) = { val testDir = compileFirrtlTest(prefix, srcDir, customTransforms, annotations) val harness = new File(testDir, s"top.cpp") - copyResourceToFile(cppHarness.toString, harness) + copyResourceToFile(cppHarnessResourceName, harness) // Note file copying side effect val verilogFiles = verilogPrefixes map { vprefix => diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index b3f6523d95..7e7c040e5c 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -18,7 +18,7 @@ class PrintfSpec extends FirrtlPropSpec { val prefix = "Printf" val testDir = compileFirrtlTest(prefix, "/features") val harness = new File(testDir, s"top.cpp") - copyResourceToFile(cppHarness.toString, harness) + copyResourceToFile(cppHarnessResourceName, harness) verilogToCpp(prefix, testDir, Seq(), harness).! cppToExe(prefix, testDir).! From 7d1d7312b99fe540e26438847544a22e324391dc Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Tue, 18 Apr 2017 11:02:51 -0700 Subject: [PATCH 2/2] Fix problems with merge --- src/test/scala/firrtlTests/FirrtlSpec.scala | 1 - src/test/scala/firrtlTests/IntegrationSpec.scala | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index b9c1c87b5c..f77b47f314 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -17,7 +17,6 @@ import firrtl.util.BackendCompilationUtilities trait FirrtlRunners extends BackendCompilationUtilities { - def parse(str: String) = Parser.parse(str.split("\n").toIterator, IgnoreInfo) val cppHarnessResourceName: String = "/firrtl/testTop.cpp" /** Compiles input Firrtl to Verilog */ diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala index f4173143a4..6ac45b6de2 100644 --- a/src/test/scala/firrtlTests/IntegrationSpec.scala +++ b/src/test/scala/firrtlTests/IntegrationSpec.scala @@ -37,8 +37,8 @@ class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec { topFile should exist // Copy harness over - val harness = new File(testDir, s"top.cpp") - copyResourceToFile(cppHarness.toString, harness) + val harness = new File(testDir, s"testTop.cpp") + copyResourceToFile(cppHarnessResourceName, harness) // topFile will be compiled by Verilator command by default but we need to also include dutFile verilogToCpp(top, testDir, Seq(dutFile), harness).!