{"payload":{"header_redesign_enabled":false,"results":[{"id":"270950839","archived":false,"color":"#DAE1C2","followers":59,"has_funding_file":false,"hl_name":"chipsalliance/uvm-verilator","hl_trunc_description":null,"language":"SystemVerilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":270950839,"name":"uvm-verilator","owner_id":46612642,"owner_login":"chipsalliance","updated_at":"2023-09-20T11:28:22.526Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":65,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Achipsalliance%252Fuvm-verilator%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/chipsalliance/uvm-verilator/star":{"post":"1_gLNsAsiM-9gkk1enp76tVd-tKpiFuQKp0TZF7FJz3CmQ4iq7nwsxTl9kcam5URfsEn1VnmbPRAmeAmSDBbWA"},"/chipsalliance/uvm-verilator/unstar":{"post":"YnjszPSrCFo2KWVbyhTuNYg_PEejqI56RjIhn59lHJ6J9zvY7NxSoCwyFkbPDOJnZgrEu4y8IHTA36DcyEf0fw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"sFh5ZOQM9t-ushNttL3VamQ1pqHOL6a_mhHz2J4doPSaMRUIw_PXw-uFqS3Ss9UIqI2-AqmzNnGDUL8GXqaeFA"}}},"title":"Repository search results"}