From 70056c8a748c86f01596687382514271f6a7a649 Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Wed, 31 Mar 2021 20:23:12 -0700 Subject: [PATCH] Flex: Switch off dependencies on header and isatty() Working towards a more platform-independent build. Issues #260 #307 #726 Signed-off-by: Henner Zeller --- common/analysis/command_file.lex | 6 ++++-- verilog/parser/verilog.lex | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/common/analysis/command_file.lex b/common/analysis/command_file.lex index 55500e5d9..3dcc8b365 100644 --- a/common/analysis/command_file.lex +++ b/common/analysis/command_file.lex @@ -20,12 +20,14 @@ #define yy_set_top_state(state) { yy_pop_state(); yy_push_state(state); } %} +%option c++ +%option never-interactive %option nodefault +%option nounistd %option noyywrap %option prefix="veribleCommandFile" -%option c++ -%option yylineno %option yyclass="verible::CommandFileLexer" +%option yylineno LineTerminator \r|\n|\r\n InputCharacter [^\r\n\0] diff --git a/verilog/parser/verilog.lex b/verilog/parser/verilog.lex index 873d2ab9d..ad67a46b3 100644 --- a/verilog/parser/verilog.lex +++ b/verilog/parser/verilog.lex @@ -54,15 +54,16 @@ %} %option 8bit +%option c++ %option case-sensitive %option never-interactive +%option nounistd %option nounput %option noyywrap %option prefix="verilog" -%option c++ -%option yyclass="verilog::VerilogLexer" /* to enable stack of initial condition states: */ %option stack +%option yyclass="verilog::VerilogLexer" /* various lexer states, INITIAL = 0 */ %x TIMESCALE_DIRECTIVE