From 5dc4379765409225bd7cb4daa40c22c6a38287b3 Mon Sep 17 00:00:00 2001
From: Joakim Andersson <joerchan@gmail.com>
Date: Tue, 3 Sep 2024 16:09:04 +0200
Subject: [PATCH] drivers: clock_control: Add clock sources to common
 enabled_clock check

Add clock sources PLL2CLK, PLL3CLK and EXT_HSE.
Needed to check that these clocks are enabled in MCO code.

(cherry picked from commit 807ccf5b0337975fad7f3c6ca1312f0dd132a99b)

Original-Signed-off-by: Joakim Andersson <joerchan@gmail.com>
GitOrigin-RevId: 807ccf5b0337975fad7f3c6ca1312f0dd132a99b
Cr-Build-Id: 8736554896755799505
Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8736554896755799505
Copybot-Job-Name: zephyr-main-copybot-downstream
Change-Id: I3ec554d6f18456ea6ab1e9c5762696fc91941f79
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5870299
Tested-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
---
 drivers/clock_control/clock_stm32_ll_common.c | 21 +++++++++++++++++++
 drivers/clock_control/clock_stm32f1.c         |  9 ++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index dc81015949e..de185f026ec 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -133,6 +133,13 @@ int enabled_clock(uint32_t src_clk)
 		}
 		break;
 #endif /* STM32_SRC_HSE */
+#if defined(STM32_SRC_EXT_HSE)
+	case STM32_SRC_EXT_HSE:
+		/* EXT_HSE is the raw OSC_IN signal, so it is always
+		 * available, regardless of the clocks configuration.
+		 */
+		break;
+#endif /* STM32_SRC_HSE */
 #if defined(STM32_SRC_HSI)
 	case STM32_SRC_HSI:
 		if (!IS_ENABLED(STM32_HSI_ENABLED)) {
@@ -210,6 +217,20 @@ int enabled_clock(uint32_t src_clk)
 		}
 		break;
 #endif /* STM32_SRC_PLLI2S_R */
+#if defined(STM32_SRC_PLL2CLK)
+	case STM32_SRC_PLL2CLK:
+		if (!IS_ENABLED(STM32_PLL2_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif
+#if defined(STM32_SRC_PLL3CLK)
+	case STM32_SRC_PLL3CLK:
+		if (!IS_ENABLED(STM32_PLL3_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif
 	default:
 		return -ENOTSUP;
 	}
diff --git a/drivers/clock_control/clock_stm32f1.c b/drivers/clock_control/clock_stm32f1.c
index 760e417eaab..752d29aba9f 100644
--- a/drivers/clock_control/clock_stm32f1.c
+++ b/drivers/clock_control/clock_stm32f1.c
@@ -23,6 +23,15 @@
 
 #if defined(STM32_PLL_ENABLED)
 
+uint32_t get_pllout_frequency(void)
+{
+	/* Stub implementation for compatibility with clock_stm32_ll_common.
+	 * The PLL domain clock is only used for MCO configuration, but the
+	 * MCO driver never queries the PLL output clock frequency.
+	 */
+	return 0;
+}
+
 /*
  * Select PLL source for STM32F1 Connectivity line devices (STM32F105xx and
  * STM32F107xx).