Error adding a TTA load/store instruction

[claubersouza]

I'm trying to add ldw and stw instruction in LSU. I'm using adf from start.adf, from the RISC-V Tutorial tutorial. I tried running the command "generateprocessor -o riscv-proc -t start.adf". The following error is returned:

generateprocessor -o riscv-proc -t start.adf
generateprocessor: FUGen.cc:1112: void FUGen::scheduleOperations(): Assertion `accessCycle >= 0 && "Failure likely due to mis-selected operation " "implementation"' failed.
Aborted (core dumped)

[karihepola]

Hi, ProGe most likely fails, since you might have configured ldw to have a latency of 1 cycle. Due to the hand-shaking protocol used in the FUGen-generated load store units, load operations must have at least a two-cycle latency. I can see how this is confusing to users and the processor generator should be able to emit a more meaningful error when this happens.

May I ask what is the motivation for adding the big endian memory operations? The base architecture definition file start.adf already has the memory operations (base+offset little endian) correctly set for RISC-V. In addition, RISC-V custom operations must follow the RISC-V R-format (two input and one output register operand) so you would not be able to use these big endian operations anyhow.

[claubersouza]

Actually, I'm trying to make an example to learn from. I took a snippet of the Fibonacci algorithm

#include<stdio.h>

int main() {

int n = 10;
int a = 0 , b =1;

for (int i = 2 ; i < n ; i++) {
    int temp = a + b;
    a = b;
    b = temp;
    printf(" %d",b);
}
printf("\n");

return 0;

}

I'm wanting to create an custom ISA for following snippet:
int temp = a + b;
a = b;
b = temp;

with help from the website https://godbolt.org/. I put the algorithm in C and configured the Compiler to be gcc 12.1.0. Which ended up generating the following assembly instruction

    lw      a4,-20(s0)
    lw      a5,-24(s0)
    add     a5,a4,a5
    sw      a5,-28(s0)
    lw      a5,-24(s0)
    sw      a5,-20(s0)
    lw      a5,-28(s0)
    sw      a5,-24(s0)

Now I'm trying to create a DAG that provides a description of the algorithm I selected. The big question is how to pass a memory address to the ldw or stw instruction. OP(stw,#temp,a); I was trying to use it like this but it's not working

[karihepola]

Actually, I'm trying to make an example to learn from. I took a snippet of the Fibonacci algorithm

#include<stdio.h>

int main() {

int n = 10;
int a = 0 , b =1;

for (int i = 2 ; i < n ; i++) {
    int temp = a + b;
    a = b;
    b = temp;
    printf(" %d",b);
}
printf("\n");

return 0;

}

I'm wanting to create an custom ISA for following snippet: int temp = a + b; a = b; b = temp;

with help from the website https://godbolt.org/. I put the algorithm in C and configured the Compiler to be gcc 12.1.0. Which ended up generating the following assembly instruction

    lw      a4,-20(s0)
    lw      a5,-24(s0)
    add     a5,a4,a5
    sw      a5,-28(s0)
    lw      a5,-24(s0)
    sw      a5,-20(s0)
    lw      a5,-28(s0)
    sw      a5,-24(s0)

Now I'm trying to create a DAG that provides a description of the algorithm I selected. The big question is how to pass a memory address to the ldw or stw instruction. OP(stw,#temp,a); I was trying to use it like this but it's not working

Couple of comments:

1. The little endian base+offset memory operations are named ast<n> (store) and ald<n> (load) in OpenASIP. For example, ast32 and ald32.
2. I assume you are trying to describe the operation pattern in osed with a DAG. The tool does not have any visibility to your C-application, hence, you must use input and output operands to describe your operation behaviour. For example, OP(AST32, IO(1), IO(2), IO(3));
3. I don't think the tool is able to generate a load-store unit that can chain memory operations. So I suggest you start with operation chains that don't use memory operations since those are much more simple to implement.
4. If you want to stick to RISC-V, you must make sure your custom operation can be described with 2 input and 1 output operands.

[claubersouza]

Right,

I'm trying to understand how to use the DAG description and use of ast32 and al32. As I said, I have the following algorithm in C:

int temp = a + b;
a = b;
b = temp;

I'm trying to create a description of the DAG, of this algorithm:
Var c;
OP(add,IO(1),IO(2),c);
OP(ald32,c, IO(3));

One question, do you have a group on Discord to ask questions?

[karihepola]

Right,

I'm trying to understand how to use the DAG description and use of ast32 and al32. As I said, I have the following algorithm in C:

int temp = a + b; a = b; b = temp;

I'm trying to create a description of the DAG, of this algorithm: Var c; OP(add,IO(1),IO(2),c); OP(ald32,c, IO(3));

One question, do you have a group on Discord to ask questions?

Designing a custom operation for this algorithm is tricky, since just based on this C example, you do not know whether you have a and b stored in the processor's register file or in memory in the compiled code.

I suppose the only approach for this is to assume they are in memory and take addresses of a and b as input to the operation chain. Then first load a and b using ld32 (32-bit little endian load without offset), do the add operation and then store them back to memory with st32 (32-bit little endian store without offset)

I want to stress that if you want to implement such custom operations that chain memory operations, you will find limited support for it in the toolset, and you will have to, at least, add hardware generation support for it.

As for the Discord, we do not have such a live channel for support currently, and we lack the resources to provide live support for users for the time being.

[claubersouza]

Thank you very much for your feedback. I managed to put the instruction in VHDL and have the expected output. But I realized that the cycle didn't slow down. Does this decrease depend on the complexity of the algorithm?

[karihepola]

Difficult to say, it also depends on your implementation. I would assume in this scenario it is very difficult to get any benefits since you are limited by the memory accesses (those will be serial in HW without parallel memories).

[claubersouza]

In this case I used the Fibonacci algorithm that I posted here previously:

int n = 10;
int a = 0 , b =1;

for (int i = 2 ; i < n ; i++) {
int temp = a + b;
a = b;
b = temp;
printf(" %d",b);
}
printf("\n");

return 0;

then So I made an operator on the ALU, with the following excerpt in vhdl:

      if counter < 9 then
      b <= std_logic_vector(signed(a) + signed(b));
      a <= b;
      counter <= counter + 1;
      reflect8_op3 <= b
      else 
      reflect8_op3 <= b;
        
      end if;

I used the rv32im.adf file, I just added one more operand. In both I had the result of:
TOTAL CYCLES: 3109
STALL CYCLES: 1135

Can you tell me any other metric to compare and see the advantage of my customized instruction?