[Language Design] Towards Higher-Level Synthesis and Co-design with Python

[VitorRamos]

Author(s): Vitor Ramos @VitorRamos and Alexandre Quenon @Arkh42
Paper PDF: https://capra.cs.cornell.edu/latte21/paper/20.pdf
Talk Recording: https://www.youtube.com/watch?v=YB0WdSEOXT8

[joaobispo]

It was not very clear if what is being proposed is a Python VM implemented in FPGA. If this is the case, this means that we would have a Python HW interpreter? How would this compare with transpilation, e.g. as sometimes is done in MATLAB-to-HDL.

[Arkh42]

To be clear, does the Python Virtual Machine that you mentioned related to the first proposed solution, i.e., the direct execution of the Python bytecode?

[VitorRamos]

What we are proposing is some solutions to push higher-level languages in HW design, this includes a Python interpreter in HW, transpilers, and accelerators. Each one has its drawbacks. In the end, the best solution depends on the project's demand.
The comparison really depends on how optimized is each solution, I believe the transpiler can always achieve better results if implemented well, but this would probably require a lot more engineering than writing a good VM.

[joaobispo]

How do you plan to deal with the dynamic typing of Python? In transpilation approaches, this is dealt with by defining the input types, and statically assigning types to all variables. I imagine it is possible to maintain the dynamic typing in a HW Python VM, but are we not losing when compared with a transpiled solution?

[VitorRamos]

Yes, I agree with that, the transpiler solution is the one that could theoretically yield the highest speedups since it implements a specific solution rather than a generic one like the interpreter, the problem as we mentioned is that writing a good transpiler that will be able to generate optimized code for most cases seems a way harder problem than writing an optimized python interpreter in HW.