[Language Design] Towards Higher-Level Synthesis and Co-design with Python #13
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It was not very clear if what is being proposed is a Python VM implemented in FPGA. If this is the case, this means that we would have a Python HW interpreter? How would this compare with transpilation, e.g. as sometimes is done in MATLAB-to-HDL. |
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How do you plan to deal with the dynamic typing of Python? In transpilation approaches, this is dealt with by defining the input types, and statically assigning types to all variables. I imagine it is possible to maintain the dynamic typing in a HW Python VM, but are we not losing when compared with a transpiled solution? |
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Author(s): Vitor Ramos @VitorRamos and Alexandre Quenon @Arkh42
Paper PDF: https://capra.cs.cornell.edu/latte21/paper/20.pdf
Talk Recording: https://www.youtube.com/watch?v=YB0WdSEOXT8
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