v2.0.0

Production version

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ISO sha1sum

365b650cba0150f80c108fe883ef1c9d5bf73149

v1.98.8

[Build]

• [x86_64] AlmaLinux 9.5 (Teal Serval) compilation fix
• [UI] Fix System Registers window for a 3 digits CPU id number

[Doc]

• SSH how to run the UI

[AArch64]

• Checking specification of Memory Model Feature Registers
• Aggregate and display ISA features of ID_AA64ISAR3_EL1
• Instruction Set Attribute Register 3 ID_AA64ISAR3_EL1
• Processor Feature Register 2 AA64PFR2_EL1
• Display FP and SIMD bits from MVFR
• Added remaining CLRBHB and PCDPHINT of ISAR2
• Display the Streaming Vector Control Register SVCR
• Query and export the Media and VFP Feature Registers MVFR
• Display, export Floating-point Control Register FPCR
• Architectural Feature Access Control Register CPACR
• Display the Hypervisor Configuration Register HCR_EL2 based on CurrentEL

[AMD]

• [VERMEER] Adding Ryzen 5 5600XT and 5600T processors
• [Zen 5c] Fixed EPYC Turin-Dense series

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CoreFreq ISO

Instructions in Wiki / LiveCD
SHA1 of the attached image

b696f1d7de5871d72bf1c177b7cce5ef490b4711

v1.98.7

[AMD]

• [Family 1Ah][Granite Ridge]
  • P-State programming fix
  • Merge PCI identifier lists
• Reserve the BTC-NOBR aggregation to Zen2 architecture

[AArch64]

• Query and JSON export Hypervisor Configuration Register HCR_EL2
  • Experimental mode required

---

CoreFreq ISO

Instructions in Wiki / LiveCD
SHA1 of the attached image

dd583e8855f98d9c62dba1b25a099c5f22dd2738

v1.98.6

[AMD]

• [V2000 Series] Adding the Ryzen Embedded V2A46
• [Family 1Ah][All Families] Refactoring topology for CCD cluster
  Confirmed 7950X, 3950X

[Intel]

• ODCM is confirmed working on Raptor Lake architecture
  Confirmed i9-14900K

[UI]

• Increased max ratio in HWP condition to avoid a zero frequency
  Confirmed i9-14900K

[Build]

• Print other variables from Makefile recipe info
  CORE_COUNT
TASK_ORDER
MAX_FREQ_HZ
HWM_CHIPSET

[CI]

• [AArch64] Commenting out the debian-testing and alpine-latest

[Doc]

• Mention the AMD family 1Ah support in README

---

CoreFreq ISO

Instructions in Wiki / LiveCD
SHA1 of the attached image

41492ffb91a987b34b71f021d7a4d19aca24a276

v1.98.5

[UI]

• Debugging a target clock ratio selector issue

[Build]

• Makefile compliant with the -s silent option
• [CI] Disable the unfound arm64v8/ubuntu:rolling

[AMD]

• [Strix Point] Adding PRO series
• [Zen5][Zen5c] Introducing the TURIN architecture
• Supply a fallback thermal junction max to various Zen series
• [Zen5] Mitigation mechanisms and Features bits
  • SBPB,
  • SRSO_NO,
  • SRSO_USR_KNL_NO,
  • ERMSB,
  • FSRS,
  • FSRC_CMPSB,
  • PREFETCHI
• [Zen] Added remaining X3D processor models
• [PHOENIX2] Added the unlocked for overclocking Ryzen 5 8500GE
• [PHOENIX2] Added the unlocked for overclocking Ryzen 3 8300GE
• [SIENA] Added the EPYC Embedded 8004 Series
• [GENOA] Added a left over EPYC Embedded 9534
• [Turin] Employed the Genoa UMC decoder
• [Family 1Ah] Updated the PStateDef MSR
• [Zen] Completed CPUID leaf 0x80000021 from PPR 57238
• [Zen5/Granite Ridge] Added Ryzen 7 9800X3D processor

[Intel]

• [ARL] Declare PCI ids to probe the IMC as a MTL controller
• [ARL][IMC] DDR5: tWR = tWRPRE - tCWL - 10
• [ADL-X/ADL-N] Declare PCI ids to probe the memory controller
• [LNL] Added PCI ids to probe any IMC and SMBUS
• [ARL] Completed with SMBUS PCI id
• [MTL-M] Declare PCI ids to probe the IMC and TCO
• [MTL-M] Set PCI ids into Daemon
• [RPL] Added remaining PX and H processor line platforms

---

CoreFreq ISO

Instructions in Wiki / LiveCD
SHA1 of the attached image

d02b0a3d92961512ed04985ac5d0bdea5227cb02

v1.98.4

[Build]

• Prevent a collision with macro WRMSRNS within kernel 6.11

[x86_64]

• [Virtualization] Switch to the HCF or VP_RUNTIME counters depending on the detected hypervisor

[ISO]

• image: archlinux-corefreq.iso
• sha1sums: 7b647372b77cefc888872aeb29c4b0696afb4212

v1.98.3

[AMD]

• [VMR/RPL/GNR] Voltage Curve Optimizer (VCO)
  • Provide a specific VCO formula based on HWM_CHIPSET=AMD_VCO build parameter
  • The standard voltage formulas are restored to these architectures
• Zen5: Guessed a new P-State MSR bits specification to fix the Coefficient Of Frequency (COF)

---

CoreFreq ISO

Wiki / LiveCD
SHA1 of the attached image

c5bd08bb57fa9b55e649ad857dd34c74051ca4d8

v1.98.2

[Intel]

• [WDT] Adding multiple devices to probe TCO
  • C620 Series Chipset Production SKUs (0xa1a3)
  • C620 Series Chipset Super SKUs (0xa223)
  • Sunrise Point/H (0xa123)
  • Cannon Lake/LP (0x9da3)
  • Comet Lake/H (0x06a3)
  • Ice Lake/LP (0x34a3)
  • Tiger Lake/H (0x43a3)
  • Elkhart Lake (0x4b23)
  • Kaby Lake/H (0xa2a3)
  • Cannon Lake (0xa323)
  • Comet Lake/V (0xa3a3)
  • Ice Lake/NG (0x38a3)
  • Alder lake/M (0x54a3)
  • Arrow Lake/S (0x7f23)
  • Jasper Lake SMBus (0x4da3)
  • Sunrise Point-LP SMBus (0x9d23)
  • Comet Lake PCH-LP SMBus (0x02a3)
• MSR_FLEX_RATIO register
  • Grant access to Alder Lake/H (06_9A)
  • Deny access to Nehalem/Bloomfield (06_1A)
  • Removed a condition in access function

---

CoreFreq ISO

Wiki / LiveCD
SHA1 of the attached image

c67628a2c574d43c8790acdf098ac396aa4c3b04

v1.98.1

[AMD]

• [Zen] Inject threshold events when thermal is out of bounds
• Generic Zen architectures renamed with their Family number
• Added a generic entry for the 1A family
• Configure TjMax for multiple Ryzen and Threadripper
• [CR] Optimize AMD temperature filtering function
• [Zen5] Introducing the Eldora architecture aka "Granite Ridge"
• [Zen5] Adding entries for Strix Point

[Intel]

• Feature-bits of Core Ultra architecture
• [TGL][ADL][RPL] New devices to probe IMC and Watchdog
• [Raptor Lake-E] Adding the IMC probing entries
• Grant full MSR_FLEX_RATIO access to Raptor Lake (06_B7)
• Added Host Bridge DIDs of Raptor Lake-E
• [ADL ... MTL] Code review of IMC decoders
• [ADL] Compute DIMM Bank and Columns on both channels
• [ADL] Process channels differently depending on DDR4 or DDR5
• 12th to 14th generation IMC decoder refactoring
• [ADL ... MTL] Adding Memory Controller Virtual Channel Count
• [ADL ... MTL] Channel count as a function of DDPCD DDR_TYPE
• [ADL ... MTL] Keep all enabled memory controllers
• [12th and superior] Compute tWR quantity as a function of DDR version

[Build]

• Now leave version number in Makefile
• Pretty print the build and the clean of outputs
  • Allow the V=n option increase the verbose level (incl. kernel)
• CPU-Freq build against Linux Kernel version 6.11

[Documentation]

• Refreshed README and Makefile

---

ISO of CoreFreq

Wiki / LiveCD

SHA1 of the attached image

sha1sum archlinux-corefreq.iso

730444ace8c0e3d59f6619534a181a5e1d9b40a9

v1.98.0

[Build]

• Change dkms configuration to install into /usr/bin/
• Solved compilation with Fedora using RHEL MINOR version number 99
• [CR] Fixed some compilation warnings
• [CR] Fix memory allocation in kernel pages for the SysGate
• Workaround to musl change in basename (#494)
• aarch64: Build with Redhat RHEL version 9
• [CR] x86_64: Prevent array size overflow
• dkms and ckms configuration files upgraded to version 1.98

[Intel]

• [Raptor Lake] Adding the HB DID of i7-14700K' IMC
• Mitigation mechanism: GDS_NO; RFDS_NO; MONITOR_MITG_NO
• Apply some SDM Documentation Changes
• [MTL] Fix CMD Stretch bit range width
• Added method CLOCK_FLEX_MAX with Xeon's Nehalem & Core 2
  • Grants full MSR_FLEX_RATIO access to tested architectures:
  • Alder Lake/S
  • Tiger Lake/U
  • Westmere/Gulftown
• Provides the overclocking bins with unlocked processors
• Query the Overclocking bit (OC) from Capabilities
• Adding technologies: VMD, HDCP, IPU and VPU
  • Volume Management Device
  • High-Bandwidth Digital Content Protection
  • Image Processing Unit
  • Vision Processing Unit
• Gaussian & Neural Accelerator - GNA technology
• [CR] Renamed Gemini Lake structures
• [Meteor Lake] Introducing memory controller decoder

[AArch64]

• Optimizing the Vcore seek
• Workaround to Package discrete voltage: the highest Vcore
• Improving computation of Euclidean division
• Adjust frequency division in CNTFRQ and PMU counters
• Scale a frequency factor from the interval
• Refactoring the frequency ratios for decimal precision
• Compile dev_pm_opp_put if Kernel greater or equal 4.11
• Get the voltage core of CPUs from OPP

[AMD]

• [Zen4][Raphael] Adding the EPYC 4004 Series
• [Zen4] Clarify Hawk Point and Phoenix-Refresh architectures
• [Family 19h] New voltage formula assigned to model 61h
  • Vcore activated
  • Voltage SoC deactivated
• [Zen] Prevent the calculation of negative temperature (issue #496)
• [Family 18h] Documented Hygon C86 7375
• [Family 19h] PStateDef specification: Adding VID[8] bit 32
  • Specification of MSR HW_PSTATE_STATUS

[CLI]

• aarch64: Display the state of the Memory Management Unit (MMU)
• aarch64: State of Instruction Cache Unit I$ and Data Cache Unit D$
• Added UI_RULER_MINIMUM & UI_RULER_MAXIMUM building constraints
• Revert "[CLI] Responsive ruler to architectural context"
  • This reverts commit 4bc38d6.
• x86_64: AMD Boost and P-States redesigned
• [UI] Hardening missing console/terminal size
• Responsive ruler to architectural context
• x86_64: Make HDCP meaning string shorter

[Driver]

• Created C2U_Enable as a parameter alias of C1U_Enable