examp_regs.json

{
    "name": "examp_regs",
    "desc": "Description of this example register map",
    "long_desc": "This is the long description for this register map. As you can clearly see, this verbose description is much more wordy than the regular description, and it is allowed to span many lines. It is optional to add this, but highly recommended.",
    "addr_width": 8,
    "data_width": 32, 
    "reggie_version": "0.1.0",
    "regs": [
        {
            "name": "reg0",
            "desc": "This is an example of a RW register",
            "long_desc": "This is the long description for this register. As you can clearly see, this verbose description is much more wordy than the regular description, and it is allowed to span many lines.",
            "access": "RW",
            "addr_offset": "0x0",
            "fields": [
                {
                    "name": "fld0",
                    "desc": "Description of fld0",
                    "bit_width": 1,
                    "bit_offset": 0,
                    "reset_value": "0x0",
                    "enums": [
                        {
                            "name": "on",
                            "value": "1"
                        },
                        {
                            "name": "off",
                            "value": "0"
                        }
                    ]
                },
                {
                    "name": "fld1",
                    "desc": "Description of fld1",
                    "bit_width": 4,
                    "bit_offset": 8,
                    "reset_value": "0xA"
                }
            ]
        },
        {
            "name": "reg1_arr",
            "desc": "This is an example of a RW register array",
            "array_length": 2,
            "access": "RW",
            "addr_offset": "0x4",
            "fields": [
                {
                    "name": "fld0",
                    "bit_width": 2,
                    "bit_offset": 2
                },
                {
                    "name": "fld1",
                    "desc": "Description of fld1",
                    "bit_width": 8,
                    "bit_offset": 8,
                    "reset_value": "000"
                }
            ]
        },
        {
            "name": "reg2",
            "desc": "This is an example of an RO register",
            "access": "RO",
            "addr_offset": "0b1100",
            "fields": [
                {
                    "name": "fld0",
                    "desc": "Description of fld0",
                    "bit_width": 32,
                    "bit_offset": 0
                }
            ]
        },
        {
            "name": "reg3",
            "desc": "This is an example of a RWV register",
            "access": "RWV",
            "addr_offset": "0x68",
            "fields": [
                {
                    "name": "fld0",
                    "desc": "Description of fld0",
                    "bit_width": 24,
                    "bit_offset": 0,
                    "reset_value": "0x23_ABCD"
                }
            ]
        }
    ]
}