[Issue riscv-non-isa#33] rv32si/ma_fetch fix

debs-sifive · Feb 6, 2019 · 248c633 · 248c633
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diff --git a/ChangeLog b/ChangeLog
@@ -1,3 +1,6 @@
+2019-02-05 Deborah Soung <debs@sifive.com>
+    * [Issue #33] rv32si/ma_fetch fix
+
 2019-02-01 Lee Moore <moore@imperas.com>
     * updated Infrastructure macros to support non-volatile registers
     * updated riscvOVPsim

diff --git a/doc/ChangeLog b/doc/ChangeLog
@@ -1,3 +1,6 @@
+2019-02-05  Deborah Soung  <debs@sifive.com>
+	* README.adoc: Update documentation for rocket chip as target (fixed rv32si/ma_fetch.S).
+
 2019-01-29  Deborah Soung  <debs@sifive.com>
 	* README.adoc: Documentation for rocket chip as target.
 

diff --git a/doc/README.adoc b/doc/README.adoc
@@ -361,7 +361,7 @@ Additional environment variables:
 
 Before running the compliance test, make sure that the correct emulator is built, following the link:https://github.com/freechipsproject/rocket-chip#emulator[instructions in the Rocket Chip repository].
 
-**Note**: Rocket Chip's `DefaultRV32Config` is currently failing the following tests — link:https://github.com/riscv/riscv-compliance/issues/31[rv32i/I-MISALIGN_JMP-01.S], link:https://github.com/riscv/riscv-compliance/issues/32[rv32mi/breakpoint.S], link:https://github.com/riscv/riscv-compliance/issues/33[rv32si/ma_fetch.S].
+**Note**: Rocket Chip's `DefaultRV32Config` is currently failing the following tests — link:https://github.com/riscv/riscv-compliance/issues/31[rv32i/I-MISALIGN_JMP-01.S], link:https://github.com/riscv/riscv-compliance/issues/32[rv32mi/breakpoint.S].
 
 === SiFive Freedom Unleashed 540 board (tbd)
 

diff --git a/riscv-test-suite/rv32si/rv64si/ma_fetch.S b/riscv-test-suite/rv32si/rv64si/ma_fetch.S
@@ -199,7 +199,7 @@ stvec_handler:
   bne a0, t0, fail
 1:
 
-  addi a1, a1, 12
+  addi a1, a1, 8
   csrw sepc, a1
   sret