suart_rx.pio

.program suart_rx
.wrap_target
start:
    wait 0 pin 0        ; Stall until start bit is asserted
    set x, 7    [10]    ; Preload bit counter, then delay until halfway through
bitloop:                ; the first data bit (12 cycles incl wait, set).
    in pins, 1          ; Shift data bit into ISR
    jmp x-- bitloop [6] ; Loop 8 times, each loop iteration is 8 cycles
    jmp pin good_stop   ; Check stop bit (should be high)

    irq 4 rel           ; Either a framing error or a break. Set a sticky flag,
    wait 1 pin 0        ; and wait for line to return to idle state.
    jmp start           ; Don't push data if we didn't see good framing.

good_stop:              ; No delay before returning to start; a little slack is
    push                ; important in case the TX clock is slightly too fast.
.wrap

% c-sdk {
#include "hardware/clocks.h"

static inline int __time_critical_func(suart_rx_program_init)(PIO pio, uint sm, uint offset, uint rxbase, uint baud) {
    uint32_t i;

    pio_sm_set_consecutive_pindirs(pio, sm, rxbase, 1, false);
    pio_gpio_init(pio, rxbase);
    gpio_pull_up(rxbase);

    pio_sm_config c = suart_rx_program_get_default_config(offset);
    sm_config_set_in_pins(&c, rxbase); // for WAIT, IN
    sm_config_set_jmp_pin(&c, rxbase); // for JMP

    // Shift to right, autopush disabled
    sm_config_set_in_shift(&c, true, false, 32);

    // Deeper FIFO as we're not doing any TX
    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);

    // SM transmits 1 bit per 8 execution cycles.
    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
    sm_config_set_clkdiv(&c, div);

    pio_sm_init(pio, sm, offset, &c);
    pio_sm_set_enabled(pio, sm, true);

    return clock_get_hz(clk_sys) / div;
}

static inline uint16_t __time_critical_func(suart_rx_program_get)(PIO pio, uint sm) {
    if (pio_sm_is_rx_fifo_empty(pio, sm))
        return 0xFFFF;

    uint32_t data = pio_sm_get_blocking(pio, sm);

    return data & 0xFF;
}

%}