****** START compiling test.Program:M8(ubyte):uint (MethodHash=d6309904) Generating code for Windows arm64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: optimizer should use profile data IL to import: IL_0000 17 ldc.i4.1 IL_0001 80 02 00 00 04 stsfld 0x4000002 IL_0006 7e 02 00 00 04 ldsfld 0x4000002 IL_000b 65 neg IL_000c d2 conv.u1 IL_000d 10 00 starg.s 0x0 IL_000f 02 ldarg.0 IL_0010 02 ldarg.0 IL_0011 5f and IL_0012 28 10 00 00 0a call 0xA000010 IL_0017 16 ldc.i4.0 IL_0018 2a ret Arg #0 passed in register(s) x0 lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace. Local V01 should not be enregistered because: it is address exposed ; Initial local variable assignments ; ; V00 arg0 ubyte ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" *************** In compInitDebuggingInfo() for test.Program:M8(ubyte):uint getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 1 VarNum LVNum Name Beg End 0: 00h 00h V00 arg0 000h 019h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for test.Program:M8(ubyte):uint Jump targets: none New Basic Block BB01 [0000] created. BB01 [000..019) IL Code Size,Instr 25, 12, Basic Block count 1, Local Variable Num,Ref count 2, 3 for method test.Program:M8(ubyte):uint OPTIONS: opts.MinOpts() == false Basic block list for 'test.Program:M8(ubyte):uint' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) *************** Finishing PHASE Profile incorporation [no changes] *************** Starting PHASE Importation impImportBlockPending for BB01 Importing BB01 (PC=000) of 'test.Program:M8(ubyte):uint' [ 0] 0 (0x000) ldc.i4.1 1 [ 1] 1 (0x001) stsfld 04000002 STMT00000 ( 0x000[E-] ... ??? ) [000003] -A--G------ * ASG short [000002] ----G--N--- +--* IND short [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] ----------- \--* CNS_INT int 1 [ 0] 6 (0x006) ldsfld 04000002 [ 1] 11 (0x00b) neg [ 1] 12 (0x00c) conv.u1 [ 1] 13 (0x00d) starg.s 0 STMT00001 ( 0x006[E-] ... ??? ) [000009] -A--G------ * ASG ubyte [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 [000007] ----G------ \--* CAST int <- ubyte <- int [000006] ----G------ \--* NEG int [000005] ----G------ \--* IND short [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [ 0] 15 (0x00f) ldarg.0 [ 1] 16 (0x010) ldarg.0 [ 2] 17 (0x011) and [ 1] 18 (0x012) call 0A000010 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 Named Intrinsic System.Console.WriteLine: Not recognized INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'test.Program:M8(ubyte):uint' calling 'System.Console:WriteLine(int)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' STMT00002 ( 0x00F[E-] ... ??? ) [000013] --C-G------ * CALL void System.Console:WriteLine(int) [000012] ----------- arg0 \--* AND int [000010] ----------- +--* LCL_VAR ubyte V00 arg0 [000011] ----------- \--* LCL_VAR ubyte V00 arg0 [ 0] 23 (0x017) ldc.i4.0 0 [ 1] 24 (0x018) ret STMT00003 ( 0x017[E-] ... ??? ) [000015] ----------- * RETURN int [000014] ----------- \--* CNS_INT int 0 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G------ * ASG short [000002] ----G--N--- +--* IND short [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] ----------- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G------ * ASG ubyte [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 [000007] ----G------ \--* CAST int <- ubyte <- int [000006] ----G------ \--* NEG int [000005] ----G------ \--* IND short [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --C-G------ * CALL void System.Console:WriteLine(int) [000012] ----------- arg0 \--* AND int [000010] ----------- +--* LCL_VAR ubyte V00 arg0 [000011] ----------- \--* LCL_VAR ubyte V00 arg0 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) [000015] ----------- * RETURN int [000014] ----------- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import [no changes] *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** Finishing PHASE Morph - Init [no changes] *************** Starting PHASE Morph - Inlining INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'test.Program:M8(ubyte):uint' calling 'System.Console:WriteLine(int)' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' **************** Inline Tree Inlines into 06000006 [via ExtendedDefaultPolicy] test.Program:M8(ubyte):uint: [INL00 IL=0018 TR=000013 06000091] [FAILED: callee: noinline per IL/cached result] System.Console:WriteLine(int) Budget: initialTime=135, finalTime=135, initialBudget=1350, currentBudget=1350 Budget: initialSize=701, finalSize=701 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty =============== No blocks renumbered! *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G------ * ASG short [000002] ----G--N--- +--* IND short [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] ----------- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G------ * ASG ubyte [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 [000007] ----G------ \--* CAST int <- ubyte <- int [000006] ----G------ \--* NEG int [000005] ----G------ \--* IND short [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --C-G------ * CALL void System.Console:WriteLine(int) [000012] ----------- arg0 \--* AND int [000010] ----------- +--* LCL_VAR ubyte V00 arg0 [000011] ----------- \--* LCL_VAR ubyte V00 arg0 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) [000015] ----------- * RETURN int [000014] ----------- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks [no changes] *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Tail merge *************** Finishing PHASE Tail merge [no changes] *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass *************** Finishing PHASE Update flow graph early pass [no changes] *************** Starting PHASE Morph - Promote Structs lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 arg0 ubyte ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" struct promotion of V01 is disabled because it has already been marked address exposed *************** Finishing PHASE Morph - Promote Structs [no changes] *************** Starting PHASE Morph - Structs/AddrExp LocalAddressVisitor visiting statement: STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G------ * ASG short [000002] ----G--N--- +--* IND short [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] ----------- \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G------ * ASG ubyte [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 [000007] ----G------ \--* CAST int <- ubyte <- int [000006] ----G------ \--* NEG int [000005] ----G------ \--* IND short [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] LocalAddressVisitor visiting statement: STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --C-G------ * CALL void System.Console:WriteLine(int) [000012] ----------- arg0 \--* AND int [000010] ----------- +--* LCL_VAR ubyte V00 arg0 [000011] ----------- \--* LCL_VAR ubyte V00 arg0 LocalAddressVisitor visiting statement: STMT00003 ( 0x017[E-] ... ??? ) [000015] ----------- * RETURN int [000014] ----------- \--* CNS_INT int 0 *************** Finishing PHASE Morph - Structs/AddrExp [no changes] *************** Starting PHASE Early liveness Local V01 should not be enregistered because: struct size does not match reg size Tracked variable (1 out of 2) table: V00 arg0 [ ubyte]: refCnt = 3, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(0)={ } DEF(1)={V00} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (0)={} OUT(0)={} *************** Finishing PHASE Early liveness Trees after Early liveness ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G------ * ASG short [000002] ----G--N--- +--* IND short [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] ----------- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G------ * ASG ubyte [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 [000007] ----G------ \--* CAST int <- ubyte <- int [000006] ----G------ \--* NEG int [000005] ----G------ \--* IND short [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --C-G------ * CALL void System.Console:WriteLine(int) [000012] ----------- arg0 \--* AND int [000010] ----------- +--* LCL_VAR ubyte V00 arg0 [000011] ----------- \--* LCL_VAR ubyte V00 arg0 (last use) ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) [000015] ----------- * RETURN int [000014] ----------- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Forward Substitution ===> BB01 [000009]: mismatched types (assignment) *************** Finishing PHASE Forward Substitution [no changes] *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs [no changes] *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'test.Program:M8(ubyte):uint' fgMorphTree BB01, STMT00000 (before) [000003] -A--G------ * ASG short [000002] ----G--N--- +--* IND short [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] ----------- \--* CNS_INT int 1 fgMorphTree BB01, STMT00001 (before) [000009] -A--G------ * ASG ubyte [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 [000007] ----G------ \--* CAST int <- ubyte <- int [000006] ----G------ \--* NEG int [000005] ----G------ \--* IND short [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] fgMorphTree BB01, STMT00001 (after) [000009] -A--G+----- * ASG ubyte [000008] D----+-N--- +--* LCL_VAR ubyte V00 arg0 [000006] ----G+----- \--* NEG int [000005] n---G+----- \--* IND short [000004] H----+----- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] fgMorphTree BB01, STMT00002 (before) [000013] --C-G------ * CALL void System.Console:WriteLine(int) [000012] ----------- arg0 \--* AND int [000010] ----------- +--* LCL_VAR ubyte V00 arg0 [000011] ----------- \--* LCL_VAR ubyte V00 arg0 (last use) Initializing arg info for 13.CALL: Args for call [000013] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000012].AND int (By value), 1 reg: x0, byteAlignment=8] Morphing args for 13.CALL: Sorting the arguments: Deferred argument ('x0'): [000016] -----+----- * CAST int <- ubyte <- int [000012] ----------- \--* AND int [000010] -----+----- +--* LCL_VAR int V00 arg0 [000011] -----+----- \--* LCL_VAR int V00 arg0 (last use) Moved to late list Register placement order: x0 Args for [000013].CALL after fgMorphArgs: CallArg[[000016].CAST int (By value), 1 reg: x0, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 fgMorphTree BB01, STMT00002 (after) [000013] --CXG+----- * CALL void System.Console:WriteLine(int) [000016] -----+----- arg0 in x0 \--* CAST int <- ubyte <- int [000012] ----------- \--* AND int [000010] -----+----- +--* LCL_VAR int V00 arg0 [000011] -----+----- \--* LCL_VAR int V00 arg0 (last use) fgMorphTree BB01, STMT00003 (before) [000015] ----------- * RETURN int [000014] ----------- \--* CNS_INT int 0 *************** In fgMarkDemotedImplicitByRefArgs() *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G+----- * ASG short [000002] n---G+-N--- +--* IND short [000001] H----+----- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] -----+----- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G+----- * ASG ubyte [000008] D----+-N--- +--* LCL_VAR ubyte V00 arg0 [000006] ----G+----- \--* NEG int [000005] n---G+----- \--* IND short [000004] H----+----- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --CXG+----- * CALL void System.Console:WriteLine(int) [000016] -----+----- arg0 in x0 \--* CAST int <- ubyte <- int [000012] ----------- \--* AND int [000010] -----+----- +--* LCL_VAR int V00 arg0 [000011] -----+----- \--* LCL_VAR int V00 arg0 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) [000015] -----+----- * RETURN int [000014] -----+----- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie [no changes] *************** Starting PHASE Compute edge weights (1, false) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing or no profile data, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) [no changes] *************** Starting PHASE Create EH funclets *************** Finishing PHASE Create EH funclets [no changes] *************** Starting PHASE Invert loops *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty =============== No blocks renumbered! *************** Finishing PHASE Invert loops [no changes] *************** Starting PHASE Optimize control flow *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize control flow Trees after Optimize control flow ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G+----- * ASG short [000002] n---G+-N--- +--* IND short [000001] H----+----- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] -----+----- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G+----- * ASG ubyte [000008] D----+-N--- +--* LCL_VAR ubyte V00 arg0 [000006] ----G+----- \--* NEG int [000005] n---G+----- \--* IND short [000004] H----+----- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --CXG+----- * CALL void System.Console:WriteLine(int) [000016] -----+----- arg0 in x0 \--* CAST int <- ubyte <- int [000012] ----------- \--* AND int [000010] -----+----- +--* LCL_VAR int V00 arg0 [000011] -----+----- \--* LCL_VAR int V00 arg0 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) [000015] -----+----- * RETURN int [000014] -----+----- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Post-morph tail merge *************** Finishing PHASE Post-morph tail merge [no changes] *************** Starting PHASE Compute blocks reachability Return blocks: BB01 Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty =============== No blocks renumbered! Enter blocks: BB01 Dominator computation start blocks (those blocks with no incoming edges): BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 *************** In fgComputeDoms *************** In fgDebugCheckBBlist ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 Inside fgBuildDomTree After computing the Dominance Tree: After numbering the dominator tree: BB01: pre=01, post=01 *************** Finishing PHASE Compute blocks reachability [no changes] *************** Starting PHASE Set block weights *************** Finishing PHASE Set block weights [no changes] *************** Starting PHASE Find loops *************** In optFindLoops() *************** In optMarkLoopHeads() 0 loop heads marked *************** Finishing PHASE Find loops Trees after Find loops ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G+----- * ASG short [000002] n---G+-N--- +--* IND short [000001] H----+----- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] -----+----- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G+----- * ASG ubyte [000008] D----+-N--- +--* LCL_VAR ubyte V00 arg0 [000006] ----G+----- \--* NEG int [000005] n---G+----- \--* IND short [000004] H----+----- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --CXG+----- * CALL void System.Console:WriteLine(int) [000016] -----+----- arg0 in x0 \--* CAST int <- ubyte <- int [000012] ----------- \--* AND int [000010] -----+----- +--* LCL_VAR int V00 arg0 [000011] -----+----- \--* LCL_VAR int V00 arg0 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) [000015] -----+----- * RETURN int [000014] -----+----- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Clone loops *************** In optCloneLoops() No loops to clone *************** Finishing PHASE Clone loops [no changes] *************** Starting PHASE Unroll loops *************** Finishing PHASE Unroll loops [no changes] *************** Starting PHASE Clear loop info *************** Finishing PHASE Clear loop info [no changes] *************** Starting PHASE Morph array ops No multi-dimensional array references in the function *************** Finishing PHASE Morph array ops [no changes] *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1) STMT00000 ( 0x000[E-] ... 0x001 ) [000003] -A--G+----- * ASG short [000002] n---G+-N--- +--* IND short [000001] H----+----- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] [000000] -----+----- \--* CNS_INT int 1 STMT00001 ( 0x006[E-] ... 0x00D ) [000009] -A--G+----- * ASG ubyte [000008] D----+-N--- +--* LCL_VAR ubyte V00 arg0 [000006] ----G+----- \--* NEG int [000005] n---G+----- \--* IND short [000004] H----+----- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] New refCnts for V00: refCnt = 1, refCntWtd = 1 V00 needs explicit zero init. Disqualified as a single-def register candidate. STMT00002 ( 0x00F[E-] ... 0x018 ) [000013] --CXG+----- * CALL void System.Console:WriteLine(int) [000016] -----+----- arg0 in x0 \--* CAST int <- ubyte <- int [000012] ----------- \--* AND int [000010] -----+----- +--* LCL_VAR int V00 arg0 [000011] -----+----- \--* LCL_VAR int V00 arg0 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 3, refCntWtd = 3 STMT00003 ( 0x017[E-] ... ??? ) [000015] -----+----- * RETURN int [000014] -----+----- \--* CNS_INT int 0 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V00: refCnt = 5, refCntWtd = 5 *************** Finishing PHASE Mark local vars [no changes] *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order Trees after Find oper order ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) ( 9, 18) [000003] -A--G---R-- * ASG short ( 7, 15) [000002] n---G--N--- +--* IND short ( 3, 12) [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ( 1, 2) [000000] ----------- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) ( 8, 16) [000009] -A--G---R-- * ASG ubyte ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 ( 8, 16) [000006] ----G------ \--* NEG int ( 7, 15) [000005] n---G------ \--* IND short ( 3, 12) [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) ( 20, 10) [000013] --CXG------ * CALL void System.Console:WriteLine(int) ( 6, 7) [000016] ----------- arg0 in x0 \--* CAST int <- ubyte <- int ( 5, 5) [000012] ----------- \--* AND int ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) ( 2, 3) [000015] ----------- * RETURN int ( 1, 2) [000014] ----------- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 5 tree nodes *************** Finishing PHASE Set block order Trees after Set block order ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) N004 ( 9, 18) [000003] -A--G---R-- * ASG short N003 ( 7, 15) [000002] n---G--N--- +--* IND short N002 ( 3, 12) [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] N001 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) N005 ( 8, 16) [000009] -A--G---R-- * ASG ubyte N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 N003 ( 8, 16) [000006] ----G------ \--* NEG int N002 ( 7, 15) [000005] n---G------ \--* IND short N001 ( 3, 12) [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) N005 ( 20, 10) [000013] --CXG------ * CALL void System.Console:WriteLine(int) N004 ( 6, 7) [000016] ----------- arg0 in x0 \--* CAST int <- ubyte <- int N003 ( 5, 5) [000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) N002 ( 2, 3) [000015] ----------- * RETURN int N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 2. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Local V01 should not be enregistered because: struct size does not match reg size Tracked variable (1 out of 2) table: V00 arg0 [ ubyte]: refCnt = 5, refCntWtd = 5 *************** In fgPerBlockLocalVarLiveness() BB01 USE(0)={ } + ByrefExposed + GcHeap DEF(1)={V00} + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} *************** In optRemoveRedundantZeroInits() Marking V00 as having an explicit init *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: *************** In SsaBuilder::RenameVariables() V00.1: defined in BB00 0 uses (local) V00.2: defined in BB01 2 uses (local) *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) N004 ( 9, 18) [000003] -A--G---R-- * ASG short N003 ( 7, 15) [000002] n---G--N--- +--* IND short N002 ( 3, 12) [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] N001 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) N005 ( 8, 16) [000009] -A--G---R-- * ASG ubyte N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 N003 ( 8, 16) [000006] ----G------ \--* NEG int N002 ( 7, 15) [000005] n---G------ \--* IND short N001 ( 3, 12) [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) N005 ( 20, 10) [000013] --CXG------ * CALL void System.Console:WriteLine(int) N004 ( 6, 7) [000016] ----------- arg0 in x0 \--* CAST int <- ubyte <- int N003 ( 5, 5) [000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) N002 ( 2, 3) [000015] ----------- * RETURN int N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE Early Value Propagation no arrays or null checks in the method *************** Finishing PHASE Early Value Propagation [no changes] *************** Starting PHASE Do value numbering *************** In fgValueNumber() Memory Initial Value in BB01 is: $c0 The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($41)} The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($41)} ***** BB01, STMT00000(before) N004 ( 9, 18) [000003] -A--G---R-- * ASG short N003 ( 7, 15) [000002] n---G--N--- +--* IND short N002 ( 3, 12) [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] N001 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 N001 [000000] CNS_INT 1 => $42 {IntCns 1} N002 [000001] CNS_INT(h) 0xd1ffab1e static Fseq[s_2] => $100 {Hnd const: 0x00000000D1FFAB1E} N003 [000002] IND => $VN.Void VNForHandle(s_2) is $101, fieldType is short, size = 2 VNForMapStore($c0, $101, $42):heap in BB01 returns $140 {$c0[$101 := $42]} fgCurMemoryVN[GcHeap] assigned for StoreField at [000003] to VN: $140. N004 [000003] ASG => $VN.Void ***** BB01, STMT00000(after) N004 ( 9, 18) [000003] -A--G---R-- * ASG short $VN.Void N003 ( 7, 15) [000002] n---G--N--- +--* IND short $VN.Void N002 ( 3, 12) [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 N001 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 $42 --------- ***** BB01, STMT00001(before) N005 ( 8, 16) [000009] -A--G---R-- * ASG ubyte N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 N003 ( 8, 16) [000006] ----G------ \--* NEG int N002 ( 7, 15) [000005] n---G------ \--* IND short N001 ( 3, 12) [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] N001 [000004] CNS_INT(h) 0xd1ffab1e static Fseq[s_2] => $100 {Hnd const: 0x00000000D1FFAB1E} VNForHandle(s_2) is $101, fieldType is short, size = 2 AX1: select([$c0]store($140, $101, $42), $101) ==> $42. VNForMapSelect($140, $101):short returns $42 {IntCns 1} VNForLoadStoreBitcast returns $42 {IntCns 1} N002 [000005] IND => N003 [000006] NEG => N004 [000008] LCL_VAR V00 arg0 d:2 => $VN.Void Tree [000009] assigned VN to local var V00/2: N005 [000009] ASG => $VN.Void ***** BB01, STMT00001(after) N005 ( 8, 16) [000009] -A--G---R-- * ASG ubyte $VN.Void N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 $VN.Void N003 ( 8, 16) [000006] ----G------ \--* NEG int N002 ( 7, 15) [000005] n---G------ \--* IND short N001 ( 3, 12) [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 --------- ***** BB01, STMT00002(before) N005 ( 20, 10) [000013] --CXG------ * CALL void System.Console:WriteLine(int) N004 ( 6, 7) [000016] ----------- arg0 in x0 \--* CAST int <- ubyte <- int N003 ( 5, 5) [000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) N001 [000010] LCL_VAR V00 arg0 u:2 => N002 [000011] LCL_VAR V00 arg0 u:2 (last use) => N003 [000012] AND => N004 [000016] CAST => fgCurMemoryVN[GcHeap] assigned for CALL at [000013] to VN: $c1. N005 [000013] CALL => $VN.Void ***** BB01, STMT00002(after) N005 ( 20, 10) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void N004 ( 6, 7) [000016] ----------- arg0 in x0 \--* CAST int <- ubyte <- int N003 ( 5, 5) [000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) --------- ***** BB01, STMT00003(before) N002 ( 2, 3) [000015] ----------- * RETURN int N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 N001 [000014] CNS_INT 0 => $40 {IntCns 0} N002 [000015] RETURN => $VN.Void ***** BB01, STMT00003(after) N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 $40 finish(BB01). *************** Finishing PHASE Do value numbering Trees after Do value numbering ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) N004 ( 9, 18) [000003] -A--G---R-- * ASG short $VN.Void N003 ( 7, 15) [000002] n---G--N--- +--* IND short $VN.Void N002 ( 3, 12) [000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 N001 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 $42 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) N005 ( 8, 16) [000009] -A--G---R-- * ASG ubyte $VN.Void N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 $VN.Void N003 ( 8, 16) [000006] ----G------ \--* NEG int N002 ( 7, 15) [000005] n---G------ \--* IND short N001 ( 3, 12) [000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) N005 ( 20, 10) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void N004 ( 6, 7) [000016] ----------- arg0 in x0 \--* CAST int <- ubyte <- int N003 ( 5, 5) [000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist SSA checks completed successfully *************** In fgDebugCheckLoopTable *************** Starting PHASE Hoist loop code No loops; no hoisting *************** Finishing PHASE Hoist loop code [no changes] *************** Starting PHASE VN based copy prop Copy Assertion for BB01 curSsaName stack: { } Live vars after [000008]: {} => {V00} Live vars after [000011]: {V00} => {} *************** Finishing PHASE VN based copy prop [no changes] *************** Starting PHASE Redundant branch opts ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Redundant branch opts [no changes] *************** Starting PHASE Optimize Valnum CSEs Candidate CSE #01, key=K_00000000D1FFAB1E in BB01, [cost= 3, size=12]: N001 ( 3, 12) CSE #01 (use)[000004] H---------- * CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 Candidate CSE #02, key=$46 in BB01, [cost= 6, size= 7]: N004 ( 6, 7) CSE #02 (use)[000016] ----------- * CAST int <- ubyte <- int N003 ( 5, 5) CSE #02 (use)[000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) Blocks that generate CSE def/uses BB01 cseGen = 0000000000000005 CSE #01, CSE #02 SSA checks completed successfully Performing DataFlow for ValnumCSE's After performing DataFlow for ValnumCSE's BB01 in: 0000000000000000 gen: 0000000000000005 CSE #01, CSE #02 out: 0000000000000005 CSE #01, CSE #02 Labeling the CSEs with Use/Def information BB01 [000001] Def of CSE #01 [weight=1] BB01 [000004] Use of CSE #01 [weight=1] BB01 [000012] Def of CSE #02 [weight=1] BB01 [000016] Use of CSE #02 [weight=1] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) N004 ( 9, 18) [000003] -A--G---R-- * ASG short $VN.Void N003 ( 7, 15) [000002] n---G--N--- +--* IND short $VN.Void N002 ( 3, 12) CSE #01 (def)[000001] H---------- | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 N001 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 $42 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) N005 ( 8, 16) [000009] -A--G---R-- * ASG ubyte $VN.Void N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 $VN.Void N003 ( 8, 16) [000006] ----G------ \--* NEG int N002 ( 7, 15) [000005] n---G------ \--* IND short N001 ( 3, 12) CSE #01 (use)[000004] H---------- \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) N005 ( 20, 10) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void N004 ( 6, 7) CSE #02 (use)[000016] ----------- arg0 in x0 \--* CAST int <- ubyte <- int N003 ( 5, 5) CSE #02 (def)[000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- Aggressive CSE Promotion cutoff is 200.000000 Moderate CSE Promotion cutoff is 100.000000 enregCount is 1 Framesize estimate is 0x0000 We have a small frame Sorted CSE candidates: CSE #02, {$46 , $2 } useCnt=1: [def=100.000000, use=100.000000, cost= 5 ] :: N003 ( 5, 5) CSE #02 (def)[000012] ----------- * AND int CSE #01, {K_00000000D1FFAB1E} useCnt=1: [def=100.000000, use=100.000000, cost= 3 ] :: N002 ( 3, 12) CSE #01 (def)[000001] H---------- * CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 Considering CSE #02 {$46 , $2 } [def=100.000000, use=100.000000, cost= 5 ] CSE Expression : N003 ( 5, 5) CSE #02 (def)[000012] ----------- * AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) Aggressive CSE Promotion (300.000000 >= 200.000000) cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000 defCnt=100.000000, useCnt=100.000000, cost=5, size=5 def_cost=1, use_cost=1, extra_no_cost=8, extra_yes_cost=0 CSE cost savings check (508.000000 >= 200.000000) passes Promoting CSE: lvaGrabTemp returning 2 (V02 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #02 is single-def, so associated CSE temp V02 will be in SSA New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 3, refCntWtd = 3 CSE #02 def at [000012] replaced in BB01 with def of V02 ReMorphing args for 13.CALL: Args for [000013].CALL after fgMorphArgs: CallArg[[000016].CAST int (By value), 1 reg: x0, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 optValnumCSE morphed tree: N009 ( 21, 11) [000013] -ACXG------ * CALL void System.Console:WriteLine(int) $VN.Void N008 ( 7, 8) CSE #02 (use)[000016] -A--------- arg0 in x0 \--* CAST int <- ubyte <- int N007 ( 6, 6) [000021] -A--------- \--* COMMA int N005 ( 5, 5) CSE #02 (def)[000019] -A------R-- +--* ASG int $VN.Void N004 ( 1, 1) [000018] D------N--- | +--* LCL_VAR int V02 cse0 d:1 $VN.Void N003 ( 5, 5) [000012] ----------- | \--* AND int N001 ( 2, 2) [000010] ----------- | +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- | \--* LCL_VAR int V00 arg0 u:2 (last use) N006 ( 1, 1) [000020] ----------- \--* LCL_VAR int V02 cse0 u:1 Working on the replacement of the CSE #02 use at [000016] in BB01 This CSE use has side effects and/or nested CSE defs. The sideEffectList: N005 ( 5, 5) CSE #02 (def)[000019] -A------R-- * ASG int $VN.Void N004 ( 1, 1) [000018] D------N--- +--* LCL_VAR int V02 cse0 d:1 $VN.Void N003 ( 5, 5) [000012] ----------- \--* AND int N001 ( 2, 2) [000010] ----------- +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- \--* LCL_VAR int V00 arg0 u:2 (last use) ReMorphing args for 13.CALL: Args for [000013].CALL after fgMorphArgs: CallArg[[000023].COMMA int (By value), 1 reg: x0, byteAlignment=8, isLate, processed] OutgoingArgsStackSize is 0 optValnumCSE morphed tree: N008 ( 20, 9) [000013] -ACXG------ * CALL void System.Console:WriteLine(int) $VN.Void N007 ( 6, 6) [000023] -A--------- arg0 in x0 \--* COMMA int N005 ( 5, 5) CSE #02 (def)[000019] -A------R-- +--* ASG int $VN.Void N004 ( 1, 1) [000018] D------N--- | +--* LCL_VAR int V02 cse0 d:1 $VN.Void N003 ( 5, 5) [000012] ----------- | \--* AND int N001 ( 2, 2) [000010] ----------- | +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- | \--* LCL_VAR int V00 arg0 u:2 (last use) N006 ( 1, 1) [000022] ----------- \--* LCL_VAR int V02 cse0 u:1 Considering CSE #01 {K_00000000D1FFAB1E} [def=100.000000, use=100.000000, cost= 3 ] CSE Expression : N002 ( 3, 12) CSE #01 (def)[000001] H---------- * CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 Aggressive CSE Promotion (300.000000 >= 200.000000) cseRefCnt=300.000000, aggressiveRefCnt=200.000000, moderateRefCnt=100.000000 defCnt=100.000000, useCnt=100.000000, cost=3, size=12 def_cost=1, use_cost=1, extra_no_cost=22, extra_yes_cost=0 CSE cost savings check (322.000000 >= 200.000000) passes Promoting CSE: lvaGrabTemp returning 3 (V03 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #01 is single-def, so associated CSE temp V03 will be in SSA New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 CSE #01 def at [000001] replaced in BB01 with def of V03 optValnumCSE morphed tree: N008 ( 10, 19) [000003] -A--G------ * ASG short $VN.Void N006 ( 8, 16) [000002] nA--G--N--- +--* IND short $VN.Void N005 ( 4, 13) [000027] -A--------- | \--* COMMA long $100 N003 ( 3, 12) CSE #01 (def)[000025] -A------R-- | +--* ASG long $VN.Void N002 ( 1, 1) [000024] D------N--- | | +--* LCL_VAR long V03 cse1 d:1 $VN.Void N001 ( 3, 12) [000001] H---------- | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 N004 ( 1, 1) [000026] ----------- | \--* LCL_VAR long V03 cse1 u:1 $100 N007 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 $42 Working on the replacement of the CSE #01 use at [000004] in BB01 optValnumCSE morphed tree: N005 ( 5, 4) [000009] -A--G---R-- * ASG ubyte $VN.Void N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 $VN.Void N003 ( 5, 4) [000006] ----G------ \--* NEG int N002 ( 4, 3) [000005] n---G------ \--* IND short N001 ( 1, 1) [000028] ----------- \--* LCL_VAR long V03 cse1 u:1 $100 *************** Finishing PHASE Optimize Valnum CSEs Trees after Optimize Valnum CSEs ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) N008 ( 10, 19) [000003] -A--G------ * ASG short $VN.Void N006 ( 8, 16) [000002] nA--G--N--- +--* IND short $VN.Void N005 ( 4, 13) [000027] -A--------- | \--* COMMA long $100 N003 ( 3, 12) [000025] -A------R-- | +--* ASG long $VN.Void N002 ( 1, 1) [000024] D------N--- | | +--* LCL_VAR long V03 cse1 d:1 $VN.Void N001 ( 3, 12) [000001] H---------- | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 N004 ( 1, 1) [000026] ----------- | \--* LCL_VAR long V03 cse1 u:1 $100 N007 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 $42 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) N005 ( 5, 4) [000009] -A--G---R-- * ASG ubyte $VN.Void N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 $VN.Void N003 ( 5, 4) [000006] ----G------ \--* NEG int N002 ( 4, 3) [000005] n---G------ \--* IND short N001 ( 1, 1) [000028] ----------- \--* LCL_VAR long V03 cse1 u:1 $100 ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) N008 ( 20, 9) [000013] -ACXG------ * CALL void System.Console:WriteLine(int) $VN.Void N007 ( 6, 6) [000023] -A--------- arg0 in x0 \--* COMMA int N005 ( 5, 5) [000019] -A------R-- +--* ASG int $VN.Void N004 ( 1, 1) [000018] D------N--- | +--* LCL_VAR int V02 cse0 d:1 $VN.Void N003 ( 5, 5) [000012] ----------- | \--* AND int N001 ( 2, 2) [000010] ----------- | +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- | \--* LCL_VAR int V00 arg0 u:2 (last use) N006 ( 1, 1) [000022] ----------- \--* LCL_VAR int V02 cse0 u:1 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist [info] NumUses overestimated for V02.1: IR 1 SSA 2 SSA checks completed successfully *************** In fgDebugCheckLoopTable Disabling SSA checking before assertion prop *************** Starting PHASE Assertion prop *************** Finishing PHASE Assertion prop [no changes] *************** Starting PHASE Optimize index checks *************** Finishing PHASE Optimize index checks [no changes] *************** Starting PHASE VN-based dead store removal Considering [000009] for removal... -- no; 'explicit init' *************** Finishing PHASE VN-based dead store removal [no changes] *************** Starting PHASE Stress gtSplitTree *************** Finishing PHASE Stress gtSplitTree [no changes] *************** Starting PHASE Expand runtime lookups *************** Finishing PHASE Expand runtime lookups [no changes] *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Optimize bools *************** In optOptimizeBools() optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes *************** Finishing PHASE Optimize bools [no changes] *************** Starting PHASE If conversion *************** Finishing PHASE If conversion [no changes] *************** Starting PHASE Optimize layout *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout Trees after Optimize layout ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} ***** BB01 STMT00000 ( 0x000[E-] ... 0x001 ) N008 ( 10, 19) [000003] -A--G------ * ASG short $VN.Void N006 ( 8, 16) [000002] nA--G--N--- +--* IND short $VN.Void N005 ( 4, 13) [000027] -A--------- | \--* COMMA long $100 N003 ( 3, 12) [000025] -A------R-- | +--* ASG long $VN.Void N002 ( 1, 1) [000024] D------N--- | | +--* LCL_VAR long V03 cse1 d:1 $VN.Void N001 ( 3, 12) [000001] H---------- | | \--* CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 N004 ( 1, 1) [000026] ----------- | \--* LCL_VAR long V03 cse1 u:1 $100 N007 ( 1, 2) [000000] ----------- \--* CNS_INT int 1 $42 ***** BB01 STMT00001 ( 0x006[E-] ... 0x00D ) N005 ( 5, 4) [000009] -A--G---R-- * ASG ubyte $VN.Void N004 ( 2, 2) [000008] D------N--- +--* LCL_VAR ubyte V00 arg0 d:2 $VN.Void N003 ( 5, 4) [000006] ----G------ \--* NEG int N002 ( 4, 3) [000005] n---G------ \--* IND short N001 ( 1, 1) [000028] ----------- \--* LCL_VAR long V03 cse1 u:1 $100 ***** BB01 STMT00002 ( 0x00F[E-] ... 0x018 ) N008 ( 20, 9) [000013] -ACXG------ * CALL void System.Console:WriteLine(int) $VN.Void N007 ( 6, 6) [000023] -A--------- arg0 in x0 \--* COMMA int N005 ( 5, 5) [000019] -A------R-- +--* ASG int $VN.Void N004 ( 1, 1) [000018] D------N--- | +--* LCL_VAR int V02 cse0 d:1 $VN.Void N003 ( 5, 5) [000012] ----------- | \--* AND int N001 ( 2, 2) [000010] ----------- | +--* LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- | \--* LCL_VAR int V00 arg0 u:2 (last use) N006 ( 1, 1) [000022] ----------- \--* LCL_VAR int V02 cse0 u:1 ***** BB01 STMT00003 ( 0x017[E-] ... ??? ) N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void N001 ( 1, 2) [000014] ----------- \--* CNS_INT int 0 $40 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Determine first cold block No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block [no changes] *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 /--* t1 long N003 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 N004 ( 1, 1) [000026] ----------- t26 = LCL_VAR long V03 cse1 u:1 $100 N007 ( 1, 2) [000000] ----------- t0 = CNS_INT int 1 $42 /--* t26 long +--* t0 int [000030] -A--G------ * STOREIND short [000031] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 $100 /--* t28 long N002 ( 4, 3) [000005] n---G------ t5 = * IND short /--* t5 short N003 ( 5, 4) [000006] ----G------ t6 = * NEG int /--* t6 int N005 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 [000032] ----------- IL_OFFSET void INLRT @ 0x00F[E-] N001 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 (last use) /--* t10 int +--* t11 int N003 ( 5, 5) [000012] ----------- t12 = * AND int /--* t12 int N005 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 N006 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 /--* t22 int arg0 in x0 N008 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void [000033] ----------- IL_OFFSET void INLRT @ 0x017[E-] N001 ( 1, 2) [000014] ----------- t14 = CNS_INT int 0 $40 /--* t14 int N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Do 'simple' lowering *************** Finishing PHASE Do 'simple' lowering [no changes] *************** Starting PHASE Lowering nodeinfo lowering store lcl var/field (before): N001 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 /--* t1 long N003 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 lowering store lcl var/field (after): N001 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 /--* t1 long N003 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 $100 /--* t28 long N002 ( 4, 3) [000005] n---G------ t5 = * IND short /--* t5 short N003 ( 5, 4) [000006] ----G------ t6 = * NEG int /--* t6 int N005 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 $100 /--* t28 long N002 ( 4, 3) [000005] n---G------ t5 = * IND short /--* t5 short N003 ( 5, 4) [000006] ----G------ t6 = * NEG int /--* t6 int N005 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 ..could not turn [000010] or [000011] into a def of flags, bailing lowering store lcl var/field (before): N001 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 (last use) /--* t10 int +--* t11 int N003 ( 5, 5) [000012] ----------- t12 = * AND int /--* t12 int N005 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 lowering store lcl var/field (after): N001 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 (last use) /--* t10 int +--* t11 int N003 ( 5, 5) [000012] ----------- t12 = * AND int /--* t12 int N005 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 lowering call (before): N006 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 /--* t22 int arg0 in x0 N008 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void args: ====== late: ====== lowering arg : N006 ( 1, 1) [000022] ----------- * LCL_VAR int V02 cse0 u:1 new node is : [000034] ----------- * PUTARG_REG int REG x0 results of lowering call: N001 ( 3, 12) [000035] H---------- t35 = CNS_INT(h) long 0xd1ffab1e ftn /--* t35 long N002 ( 6, 14) [000036] ----------- t36 = * IND long lowering call (after): N006 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 /--* t22 int [000034] ----------- t34 = * PUTARG_REG int REG x0 N001 ( 3, 12) [000035] H---------- t35 = CNS_INT(h) long 0xd1ffab1e ftn /--* t35 long N002 ( 6, 14) [000036] ----------- t36 = * IND long /--* t34 int arg0 in x0 +--* t36 long control expr N008 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void lowering GT_RETURN N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void ============Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 /--* t1 long N003 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 N004 ( 1, 1) [000026] ----------- t26 = LCL_VAR long V03 cse1 u:1 $100 N007 ( 1, 2) [000000] ----------- t0 = CNS_INT int 1 $42 /--* t26 long +--* t0 int [000030] -A--G------ * STOREIND short [000031] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 $100 /--* t28 long N002 ( 4, 3) [000005] n---G------ t5 = * IND short /--* t5 short N003 ( 5, 4) [000006] ----G------ t6 = * NEG int /--* t6 int N005 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 [000032] ----------- IL_OFFSET void INLRT @ 0x00F[E-] N001 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 (last use) /--* t10 int +--* t11 int N003 ( 5, 5) [000012] ----------- t12 = * AND int /--* t12 int N005 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 N006 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 /--* t22 int [000034] ----------- t34 = * PUTARG_REG int REG x0 N001 ( 3, 12) [000035] H---------- t35 = CNS_INT(h) long 0xd1ffab1e ftn /--* t35 long N002 ( 6, 14) [000036] ----------- t36 = * IND long /--* t34 int arg0 in x0 +--* t36 long control expr N008 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void [000033] ----------- IL_OFFSET void INLRT @ 0x017[E-] N001 ( 1, 2) [000014] ----------- t14 = CNS_INT int 0 $40 /--* t14 int N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V00: refCnt = 5, refCntWtd = 5 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 arg0 ubyte ; V01 OutArgs struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 cse0 int "CSE - aggressive" ; V03 cse1 long "CSE - aggressive" In fgLocalVarLivenessInit Local V01 should not be enregistered because: struct size does not match reg size Tracked variable (3 out of 4) table: V00 arg0 [ ubyte]: refCnt = 5, refCntWtd = 5 V03 cse1 [ long]: refCnt = 3, refCntWtd = 3 V02 cse0 [ int]: refCnt = 2, refCntWtd = 2 *************** In fgPerBlockLocalVarLiveness() BB01 USE(0)={ } + ByrefExposed + GcHeap DEF(3)={V00 V03 V02} + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgRemoveDeadBlocks() Removing unreachable blocks for fgRemoveDeadBlocks iteration #1 *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V00: refCnt = 5, refCntWtd = 5 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] $100 /--* t1 long N003 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 N004 ( 1, 1) [000026] ----------- t26 = LCL_VAR long V03 cse1 u:1 $100 N007 ( 1, 2) [000000] ----------- t0 = CNS_INT int 1 $42 /--* t26 long +--* t0 int [000030] -A--G------ * STOREIND short [000031] ----------- IL_OFFSET void INLRT @ 0x006[E-] N001 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 (last use) $100 /--* t28 long N002 ( 4, 3) [000005] n---G------ t5 = * IND short /--* t5 short N003 ( 5, 4) [000006] ----G------ t6 = * NEG int /--* t6 int N005 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 [000032] ----------- IL_OFFSET void INLRT @ 0x00F[E-] N001 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 N002 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 (last use) /--* t10 int +--* t11 int N003 ( 5, 5) [000012] ----------- t12 = * AND int /--* t12 int N005 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 N006 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 (last use) /--* t22 int [000034] ----------- t34 = * PUTARG_REG int REG x0 N001 ( 3, 12) [000035] H---------- t35 = CNS_INT(h) long 0xd1ffab1e ftn /--* t35 long N002 ( 6, 14) [000036] ----------- t36 = * IND long /--* t34 int arg0 in x0 +--* t36 long control expr N008 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) $VN.Void [000033] ----------- IL_OFFSET void INLRT @ 0x017[E-] N001 ( 1, 2) [000014] ----------- t14 = CNS_INT int 0 $40 /--* t14 int N002 ( 2, 3) [000015] ----------- * RETURN int $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use: {} def: {V00 V02 V03} in: {} out: {} Interval 0: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 0: (V00) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 1: int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 1: (V02) int RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 2: long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] Interval 2: (V03) long RefPositions {} physReg:NA Preferences=[x0-xip1 x19-x28] FP callee save candidate vars: None floatVarCount = 0; hasLoops = false, singleExit = true ; Decided to create an EBP based frame for ETW stackwalking (Temporary ARM64 force frame pointer) *************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT) Setting genSaveFpLrWithAllCalleeSavedRegisters to false Assign V00 arg0, size=4, stkOffs=-0x54 Assign V02 cse0, size=4, stkOffs=-0x58 Pad V03 cse1, size=8, stkOffs=-0x5f, pad=7 Assign V03 cse1, size=8, stkOffs=-0x67 --- delta bump 152 for FP frame --- virtual stack offset to actual stack offset delta is 152 -- V00 was -84, now 68 -- V01 was 0, now 152 -- V02 was -88, now 64 -- V03 was -103, now 49 compRsvdRegCheck frame size = 152 compArgSize = 8 Returning true (ARM64) Reserved REG_OPT_RSVD (xip1) due to large frame TUPLE STYLE DUMP BEFORE LSRA Start LSRA Block Sequence: Current block: BB01 Final LSRA Block Sequence: BB01 ( 1 ) BB01 [000..019) (return), preds={} succs={} ===== N000. IL_OFFSET INLRT @ 0x000[E-] N001. t1 = CNS_INT(h) 0xd1ffab1e static Fseq[s_2] N003. V03(t25); t1 N004. V03(t26) N007. t0 = CNS_INT 1 N000. STOREIND ; t26,t0 N000. IL_OFFSET INLRT @ 0x006[E-] N001. V03(t28*) N002. t5 = IND ; t28* N003. t6 = NEG ; t5 N005. V00(t9); t6 N000. IL_OFFSET INLRT @ 0x00F[E-] N001. V00(t10) N002. V00(t11*) N003. t12 = AND ; t10,t11* N005. V02(t19); t12 N006. V02(t22*) N000. t34 = PUTARG_REG; t22* N001. t35 = CNS_INT(h) 0xd1ffab1e ftn N002. t36 = IND ; t35 N008. CALL ; t34,t36 N000. IL_OFFSET INLRT @ 0x017[E-] N001. t14 = CNS_INT 0 N002. RETURN ; t14 buildIntervals second part ======== Int arg V00 in reg x0 BB00 regmask=[x0] minReg=1 fixed wt=100.00> NEW BLOCK BB01 DefList: { } N003 (???,???) [000029] ----------- * IL_OFFSET void INLRT @ 0x000[E-] REG NA DefList: { } N005 ( 3, 12) [000001] H---------- * CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] REG NA $100 Interval 3: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N005.t1. CNS_INT } N007 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> DefList: { } N009 ( 1, 1) [000026] ----------- * LCL_VAR long V03 cse1 u:1 NA REG NA $100 DefList: { } N011 ( 1, 2) [000000] ----------- * CNS_INT int 1 REG NA $42 Interval 4: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N011.t0. CNS_INT } N013 (???,???) [000030] -A--G------ * STOREIND short REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> DefList: { } N015 (???,???) [000031] ----------- * IL_OFFSET void INLRT @ 0x006[E-] REG NA DefList: { } N017 ( 1, 1) [000028] ----------- * LCL_VAR long V03 cse1 u:1 NA (last use) REG NA $100 DefList: { } N019 ( 4, 3) [000005] n---G------ * IND short REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> Interval 5: short RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N019.t5. IND } N021 ( 5, 4) [000006] ----G------ * NEG int REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Interval 6: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] NEG BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N021.t6. NEG } N023 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> DefList: { } N025 (???,???) [000032] ----------- * IL_OFFSET void INLRT @ 0x00F[E-] REG NA DefList: { } N027 ( 2, 2) [000010] ----------- * LCL_VAR int V00 arg0 u:2 NA REG NA DefList: { } N029 ( 2, 2) [000011] ----------- * LCL_VAR int V00 arg0 u:2 NA (last use) REG NA DefList: { } N031 ( 5, 5) [000012] ----------- * AND int REG NA LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> Interval 7: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] AND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N031.t12. AND } N033 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 NA REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=200.00> DefList: { } N035 ( 1, 1) [000022] ----------- * LCL_VAR int V02 cse0 u:1 NA (last use) REG NA DefList: { } N037 (???,???) [000034] ----------- * PUTARG_REG int REG x0 BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=200.00> Interval 8: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> DefList: { N037.t34. PUTARG_REG } N039 ( 3, 12) [000035] H---------- * CNS_INT(h) long 0xd1ffab1e ftn REG NA Interval 9: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N037.t34. PUTARG_REG; N039.t35. CNS_INT } N041 ( 6, 14) [000036] ----------- * IND long REG NA BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> Interval 10: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N037.t34. PUTARG_REG; N041.t36. IND } N043 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) REG NA $VN.Void BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x1] minReg=1 wt=100.00> BB01 regmask=[x2] minReg=1 wt=100.00> BB01 regmask=[x3] minReg=1 wt=100.00> BB01 regmask=[x4] minReg=1 wt=100.00> BB01 regmask=[x5] minReg=1 wt=100.00> BB01 regmask=[x6] minReg=1 wt=100.00> BB01 regmask=[x7] minReg=1 wt=100.00> BB01 regmask=[x8] minReg=1 wt=100.00> BB01 regmask=[x9] minReg=1 wt=100.00> BB01 regmask=[x10] minReg=1 wt=100.00> BB01 regmask=[x11] minReg=1 wt=100.00> BB01 regmask=[x12] minReg=1 wt=100.00> BB01 regmask=[x13] minReg=1 wt=100.00> BB01 regmask=[x14] minReg=1 wt=100.00> BB01 regmask=[x15] minReg=1 wt=100.00> BB01 regmask=[xip0] minReg=1 wt=100.00> BB01 regmask=[xip1] minReg=1 wt=100.00> BB01 regmask=[lr] minReg=1 wt=100.00> DefList: { } N045 (???,???) [000033] ----------- * IL_OFFSET void INLRT @ 0x017[E-] REG NA DefList: { } N047 ( 1, 2) [000014] ----------- * CNS_INT int 0 REG NA $40 Interval 11: int RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> DefList: { N047.t14. CNS_INT } N049 ( 2, 3) [000015] ----------- * RETURN int REG NA $VN.Void BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> CHECKING LAST USES for BB01, liveout={} ============================== use: {} def: {V00 V02 V03} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) int RefPositions {#0@0 #13@24 #14@31 #15@31} physReg:x0 Preferences=[x0] Interval 1: (V02) int RefPositions {#18@34 #20@37} physReg:NA Preferences=[x0] Interval 2: (V03) long RefPositions {#4@8 #6@13 #8@19} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 3: long (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 4: int (constant) RefPositions {#5@12 #7@13} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 5: short RefPositions {#9@20 #10@21} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 6: int RefPositions {#11@22 #12@23} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 7: int RefPositions {#16@32 #17@33} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 8: int RefPositions {#22@38 #27@43} physReg:NA Preferences=[x0] Interval 9: long (constant) RefPositions {#23@40 #24@41} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: long RefPositions {#25@42 #28@43} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 11: int (constant) RefPositions {#48@48 #50@49} physReg:NA Preferences=[x0] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> NEG BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> AND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=200.00> BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> BB01 regmask=[x0] minReg=1 last wt=100.00> BB01 regmask=[x1] minReg=1 last wt=100.00> BB01 regmask=[x2] minReg=1 last wt=100.00> BB01 regmask=[x3] minReg=1 last wt=100.00> BB01 regmask=[x4] minReg=1 last wt=100.00> BB01 regmask=[x5] minReg=1 last wt=100.00> BB01 regmask=[x6] minReg=1 last wt=100.00> BB01 regmask=[x7] minReg=1 last wt=100.00> BB01 regmask=[x8] minReg=1 last wt=100.00> BB01 regmask=[x9] minReg=1 last wt=100.00> BB01 regmask=[x10] minReg=1 last wt=100.00> BB01 regmask=[x11] minReg=1 last wt=100.00> BB01 regmask=[x12] minReg=1 last wt=100.00> BB01 regmask=[x13] minReg=1 last wt=100.00> BB01 regmask=[x14] minReg=1 last wt=100.00> BB01 regmask=[x15] minReg=1 last wt=100.00> BB01 regmask=[xip0] minReg=1 last wt=100.00> BB01 regmask=[xip1] minReg=1 last wt=100.00> BB01 regmask=[lr] minReg=1 last wt=100.00> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> ------------ REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval) ------------ ----------------- BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> ----------------- STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=200.00> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 BB01 [000..019) (return), preds={} succs={} ===== N003. IL_OFFSET INLRT @ 0x000[E-] N005. CNS_INT(h) 0xd1ffab1e static Fseq[s_2] Def:(#2) Pref: N007. V03(L2) Use:(#3) * Def:(#4) N009. V03(L2) N011. CNS_INT 1 Def:(#5) N013. STOREIND Use:(#6) Use:(#7) * N015. IL_OFFSET INLRT @ 0x006[E-] N017. V03(L2) N019. IND Use:(#8) * Def:(#9) N021. NEG Use:(#10) * Def:(#11) Pref: N023. V00(L0) Use:(#12) * Def:(#13) N025. IL_OFFSET INLRT @ 0x00F[E-] N027. V00(L0) N029. V00(L0) N031. AND Use:(#14) Use:(#15) * Def:(#16) Pref: N033. V02(L1) Use:(#17) * Def:(#18) N035. V02(L1) N037. PUTARG_REG Use:(#20) Fixed:x0(#19) * Def:(#22) x0 N039. CNS_INT(h) 0xd1ffab1e ftn Def:(#23) N041. IND Use:(#24) * Def:(#25) N043. CALL Use:(#27) Fixed:x0(#26) * Use:(#28) * Kill: x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 xip0 xip1 lr N045. IL_OFFSET INLRT @ 0x017[E-] N047. CNS_INT 0 Def:(#48) N049. RETURN Use:(#50) Fixed:x0(#49) * Linear scan intervals after buildIntervals: Interval 0: (V00) int RefPositions {#0@0 #13@24 #14@31 #15@31} physReg:x0 Preferences=[x0] Interval 1: (V02) int RefPositions {#18@34 #20@37} physReg:NA Preferences=[x0] Interval 2: (V03) long RefPositions {#4@8 #6@13 #8@19} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 3: long (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 4: int (constant) RefPositions {#5@12 #7@13} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 5: short RefPositions {#9@20 #10@21} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 6: int RefPositions {#11@22 #12@23} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 7: int RefPositions {#16@32 #17@33} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 8: int RefPositions {#22@38 #27@43} physReg:NA Preferences=[x0] Interval 9: long (constant) RefPositions {#23@40 #24@41} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: long RefPositions {#25@42 #28@43} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 11: int (constant) RefPositions {#48@48 #50@49} physReg:NA Preferences=[x0] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) int RefPositions {#0@0 #13@24 #14@31 #15@31} physReg:x0 Preferences=[x0] Interval 1: (V02) int RefPositions {#18@34 #20@37} physReg:NA Preferences=[x0] Interval 2: (V03) long RefPositions {#4@8 #6@13 #8@19} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 3: long (constant) RefPositions {#2@6 #3@7} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 4: int (constant) RefPositions {#5@12 #7@13} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 5: short RefPositions {#9@20 #10@21} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 6: int RefPositions {#11@22 #12@23} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 7: int RefPositions {#16@32 #17@33} physReg:NA Preferences=[x0-xip0 x19-x28] RelatedInterval Interval 8: int RefPositions {#22@38 #27@43} physReg:NA Preferences=[x0] Interval 9: long (constant) RefPositions {#23@40 #24@41} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 10: long RefPositions {#25@42 #28@43} physReg:NA Preferences=[x0-xip0 x19-x28] Interval 11: int (constant) RefPositions {#48@48 #50@49} physReg:NA Preferences=[x0] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> NEG BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> AND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=200.00> BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00> BB01 regmask=[x0] minReg=1 last wt=100.00> BB01 regmask=[x1] minReg=1 last wt=100.00> BB01 regmask=[x2] minReg=1 last wt=100.00> BB01 regmask=[x3] minReg=1 last wt=100.00> BB01 regmask=[x4] minReg=1 last wt=100.00> BB01 regmask=[x5] minReg=1 last wt=100.00> BB01 regmask=[x6] minReg=1 last wt=100.00> BB01 regmask=[x7] minReg=1 last wt=100.00> BB01 regmask=[x8] minReg=1 last wt=100.00> BB01 regmask=[x9] minReg=1 last wt=100.00> BB01 regmask=[x10] minReg=1 last wt=100.00> BB01 regmask=[x11] minReg=1 last wt=100.00> BB01 regmask=[x12] minReg=1 last wt=100.00> BB01 regmask=[x13] minReg=1 last wt=100.00> BB01 regmask=[x14] minReg=1 last wt=100.00> BB01 regmask=[x15] minReg=1 last wt=100.00> BB01 regmask=[xip0] minReg=1 last wt=100.00> BB01 regmask=[xip1] minReg=1 last wt=100.00> BB01 regmask=[lr] minReg=1 last wt=100.00> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=500.00> --- V01 --- V02 (Interval 1) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=200.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=200.00> --- V03 (Interval 2) STORE_LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=300.00> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use, Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register, (b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc, '(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive. Columns are only printed up to the last modified register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. ------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | ------------------------------------------+----+----+----+----+----+----+----+----+----+----+ |V0 a| | | | | | | | | | 0.#0 V0 Parm Keep x0 |V0 a| | | | | | | | | | 1.#1 BB1 PredBB0 |V0 a| | | | | | | | | | [000001] 6.#2 C3 Def ORDER(A) x1 |V0 a|C3 a| | | | | | | | | [000025] 7.#3 C3 Use * Keep x1 |V0 a|C3 a| | | | | | | | | 8.#4 V3 Def COVRS(A) x1 |V0 a|V3 a| | | | | | | | | [000000] 12.#5 C4 Def ORDER(A) x2 |V0 a|V3 a|C4 a| | | | | | | | [000030] 13.#6 V3 Use Keep x1 |V0 a|V3 a|C4 a| | | | | | | | 13.#7 C4 Use * Keep x2 |V0 a|V3 a|C4 a| | | | | | | | [000005] 19.#8 V3 Use * Keep x1 |V0 a|V3 a|C4 i| | | | | | | | 20.#9 I5 Def ORDER(A) x1 |V0 a|I5 a|C4 i| | | | | | | | [000006] 21.#10 I5 Use * Keep x1 |V0 a|I5 a|C4 i| | | | | | | | 22.#11 I6 Def ORDER(A) x1 |V0 a|I6 a|C4 i| | | | | | | | [000009] 23.#12 I6 Use * Keep x1 |V0 a|I6 a|C4 i| | | | | | | | 24.#13 V0 Def Keep x0 |V0 a| |C4 i| | | | | | | | [000012] 31.#14 V0 Use Keep x0 |V0 a| |C4 i| | | | | | | | 31.#15 V0 Use * Keep x0 |V0 a| |C4 i| | | | | | | | 32.#16 I7 Def RELPR(A) x0 |I7 a| |C4 i| | | | | | | | [000019] 33.#17 I7 Use * Keep x0 |I7 a| |C4 i| | | | | | | | 34.#18 V2 Def COVRS(A) x0 |V2 a| |C4 i| | | | | | | | [000034] 37.#19 x0 Fixd Keep x0 |V2 a| |C4 i| | | | | | | | 37.#20 V2 Use * Keep x0 |V2 a| |C4 i| | | | | | | | 38.#21 x0 Fixd Keep x0 | | |C4 i| | | | | | | | 38.#22 I8 Def Alloc x0 |I8 a| |C4 i| | | | | | | | [000035] 40.#23 C9 Def ORDER(A) x1 |I8 a|C9 a|C4 i| | | | | | | | [000036] 41.#24 C9 Use * Keep x1 |I8 a|C9 a|C4 i| | | | | | | | 42.#25 I10 Def ORDER(A) x1 |I8 a|I10a|C4 i| | | | | | | | [000013] 43.#26 x0 Fixd Keep x0 |I8 a|I10a|C4 i| | | | | | | | 43.#27 I8 Use * Keep x0 |I8 a|I10a|C4 i| | | | | | | | 43.#28 I10 Use * Keep x1 |I8 a|I10a|C4 i| | | | | | | | 44.#29 x0 Kill Keep x0 | | |C4 i| | | | | | | | 44.#30 x1 Kill Keep x1 | | |C4 i| | | | | | | | 44.#31 x2 Kill Keep x2 | | | | | | | | | | | 44.#32 x3 Kill Keep x3 | | | | | | | | | | | 44.#33 x4 Kill Keep x4 | | | | | | | | | | | 44.#34 x5 Kill Keep x5 | | | | | | | | | | | 44.#35 x6 Kill Keep x6 | | | | | | | | | | | 44.#36 x7 Kill Keep x7 | | | | | | | | | | | 44.#37 x8 Kill Keep x8 | | | | | | | | | | | 44.#38 x9 Kill Keep x9 | | | | | | | | | | | 44.#39 x10 Kill Keep x10 | | | | | | | | | | | 44.#40 x11 Kill Keep x11 | | | | | | | | | | | 44.#41 x12 Kill Keep x12 | | | | | | | | | | | 44.#42 x13 Kill Keep x13 | | | | | | | | | | | 44.#43 x14 Kill Keep x14 | | | | | | | | | | | 44.#44 x15 Kill Keep x15 | | | | | | | | | | | 44.#45 xip0 Kill Keep xip0 | | | | | | | | | | | 44.#46 xip1 Kill Keep xip1 | | | | | | | | | | | 44.#47 lr Kill Keep lr | | | | | | | | | | | [000014] 48.#48 C11 Def Alloc x0 |C11a| | | | | | | | | | [000015] 49.#49 x0 Fixd Keep x0 |C11a| | | | | | | | | | ------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | ------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 49.#50 C11 Use * Keep x0 |C11i| | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> CNS_INT BB01 regmask=[x1] minReg=1 wt=400.00> BB01 regmask=[x1] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x1] minReg=1 wt=300.00> CNS_INT BB01 regmask=[x2] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[x1] minReg=1 wt=300.00> BB01 regmask=[x2] minReg=1 last wt=100.00> LCL_VAR BB01 regmask=[x1] minReg=1 last wt=300.00> IND BB01 regmask=[x1] minReg=1 wt=400.00> BB01 regmask=[x1] minReg=1 last wt=100.00> NEG BB01 regmask=[x1] minReg=1 wt=400.00> BB01 regmask=[x1] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0] minReg=1 last wt=500.00> AND BB01 regmask=[x0] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=200.00> BB01 regmask=[x0] minReg=1 wt=100.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=200.00> BB01 regmask=[x0] minReg=1 wt=100.00> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00> CNS_INT BB01 regmask=[x1] minReg=1 wt=400.00> BB01 regmask=[x1] minReg=1 last wt=100.00> IND BB01 regmask=[x1] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> BB01 regmask=[x1] minReg=1 last wt=100.00> BB01 regmask=[x0] minReg=1 last wt=100.00> BB01 regmask=[x1] minReg=1 last wt=100.00> BB01 regmask=[x2] minReg=1 last wt=100.00> BB01 regmask=[x3] minReg=1 last wt=100.00> BB01 regmask=[x4] minReg=1 last wt=100.00> BB01 regmask=[x5] minReg=1 last wt=100.00> BB01 regmask=[x6] minReg=1 last wt=100.00> BB01 regmask=[x7] minReg=1 last wt=100.00> BB01 regmask=[x8] minReg=1 last wt=100.00> BB01 regmask=[x9] minReg=1 last wt=100.00> BB01 regmask=[x10] minReg=1 last wt=100.00> BB01 regmask=[x11] minReg=1 last wt=100.00> BB01 regmask=[x12] minReg=1 last wt=100.00> BB01 regmask=[x13] minReg=1 last wt=100.00> BB01 regmask=[x14] minReg=1 last wt=100.00> BB01 regmask=[x15] minReg=1 last wt=100.00> BB01 regmask=[xip0] minReg=1 last wt=100.00> BB01 regmask=[xip1] minReg=1 last wt=100.00> BB01 regmask=[lr] minReg=1 last wt=100.00> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00> BB01 regmask=[x0] minReg=1 wt=100.00> BB01 regmask=[x0] minReg=1 last fixed wt=100.00> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[x0] minReg=1 fixed regOptional wt=100.00> STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0] minReg=1 wt=500.00> LCL_VAR BB01 regmask=[x0] minReg=1 last wt=500.00> --- V01 --- V02 (Interval 1) STORE_LCL_VAR BB01 regmask=[x0] minReg=1 wt=200.00> LCL_VAR BB01 regmask=[x0] minReg=1 last fixed wt=200.00> --- V03 (Interval 2) STORE_LCL_VAR BB01 regmask=[x1] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[x1] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[x1] minReg=1 last wt=300.00> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {} Has No Critical Edges Prior to Resolution BB01 use: {} def: {V00 V02 V03} in: {} out: {} Var=Reg beg of BB01: V00=x0 Var=Reg end of BB01: none RESOLVING EDGES Set V00 argument initial register to x0 Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} N003 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N005 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] REG x1 $100 /--* t1 long N007 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 x1 REG x1 N009 ( 1, 1) [000026] ----------- t26 = LCL_VAR long V03 cse1 u:1 x1 REG x1 $100 N011 ( 1, 2) [000000] ----------- t0 = CNS_INT int 1 REG x2 $42 /--* t26 long +--* t0 int N013 (???,???) [000030] -A--G------ * STOREIND short REG NA N015 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N017 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 x1 (last use) REG x1 $100 /--* t28 long N019 ( 4, 3) [000005] n---G------ t5 = * IND short REG x1 /--* t5 short N021 ( 5, 4) [000006] ----G------ t6 = * NEG int REG x1 /--* t6 int N023 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 x0 REG x0 N025 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x00F[E-] REG NA N027 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 x0 REG x0 N029 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 x0 (last use) REG x0 /--* t10 int +--* t11 int N031 ( 5, 5) [000012] ----------- t12 = * AND int REG x0 /--* t12 int N033 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 x0 REG x0 N035 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 x0 (last use) REG x0 /--* t22 int N037 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG x0 N039 ( 3, 12) [000035] H---------- t35 = CNS_INT(h) long 0xd1ffab1e ftn REG x1 /--* t35 long N041 ( 6, 14) [000036] ----------- t36 = * IND long REG x1 /--* t34 int arg0 in x0 +--* t36 long control expr N043 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) REG NA $VN.Void N045 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x017[E-] REG NA N047 ( 1, 2) [000014] ----------- t14 = CNS_INT int 0 REG x0 $40 /--* t14 int N049 ( 2, 3) [000015] ----------- * RETURN int REG NA $VN.Void ------------------------------------------------------------------------------------------------------------------- Final allocation ------------------------------------------+----+----+----+----+----+----+----+----+----+----+ TreeID LocRP# Name Type Action Reg |x0 |x1 |x2 |x3 |x4 |x5 |x6 |x7 |x19 |x20 | ------------------------------------------+----+----+----+----+----+----+----+----+----+----+ 0.#0 V0 Parm Alloc x0 |V0 a| | | | | | | | | | 1.#1 BB1 PredBB0 |V0 a| | | | | | | | | | [000001] 6.#2 C3 Def Alloc x1 |V0 a|C3 a| | | | | | | | | [000025] 7.#3 C3 Use * Keep x1 |V0 a|C3 i| | | | | | | | | 8.#4 V3 Def Alloc x1 |V0 a|V3 a| | | | | | | | | [000000] 12.#5 C4 Def Alloc x2 |V0 a|V3 a|C4 a| | | | | | | | [000030] 13.#6 V3 Use Keep x1 |V0 a|V3 a|C4 a| | | | | | | | 13.#7 C4 Use * Keep x2 |V0 a|V3 a|C4 i| | | | | | | | [000005] 19.#8 V3 Use * Keep x1 |V0 a|V3 i| | | | | | | | | 20.#9 I5 Def Alloc x1 |V0 a|I5 a| | | | | | | | | [000006] 21.#10 I5 Use * Keep x1 |V0 a|I5 i| | | | | | | | | 22.#11 I6 Def Alloc x1 |V0 a|I6 a| | | | | | | | | [000009] 23.#12 I6 Use * Keep x1 |V0 a|I6 i| | | | | | | | | 24.#13 V0 Def Alloc x0 |V0 a| | | | | | | | | | [000012] 31.#14 V0 Use Keep x0 |V0 a| | | | | | | | | | 31.#15 V0 Use * Keep x0 |V0 i| | | | | | | | | | 32.#16 I7 Def Alloc x0 |I7 a| | | | | | | | | | [000019] 33.#17 I7 Use * Keep x0 |I7 i| | | | | | | | | | 34.#18 V2 Def Alloc x0 |V2 a| | | | | | | | | | [000034] 37.#19 x0 Fixd Keep x0 |V2 a| | | | | | | | | | 37.#20 V2 Use * Keep x0 |V2 i| | | | | | | | | | 38.#21 x0 Fixd Keep x0 | | | | | | | | | | | 38.#22 I8 Def Alloc x0 |I8 a| | | | | | | | | | [000035] 40.#23 C9 Def Alloc x1 |I8 a|C9 a| | | | | | | | | [000036] 41.#24 C9 Use * Keep x1 |I8 a|C9 i| | | | | | | | | 42.#25 I10 Def Alloc x1 |I8 a|I10a| | | | | | | | | [000013] 43.#26 x0 Fixd Keep x0 |I8 a|I10a| | | | | | | | | 43.#27 I8 Use * Keep x0 |I8 i|I10a| | | | | | | | | 43.#28 I10 Use * Keep x1 | |I10i| | | | | | | | | 44.#29 x0 Kill Keep x0 | | | | | | | | | | | 44.#30 x1 Kill Keep x1 | | | | | | | | | | | 44.#31 x2 Kill Keep x2 | | | | | | | | | | | 44.#32 x3 Kill Keep x3 | | | | | | | | | | | 44.#33 x4 Kill Keep x4 | | | | | | | | | | | 44.#34 x5 Kill Keep x5 | | | | | | | | | | | 44.#35 x6 Kill Keep x6 | | | | | | | | | | | 44.#36 x7 Kill Keep x7 | | | | | | | | | | | 44.#37 x8 Kill Keep x8 | | | | | | | | | | | 44.#38 x9 Kill Keep x9 | | | | | | | | | | | 44.#39 x10 Kill Keep x10 | | | | | | | | | | | 44.#40 x11 Kill Keep x11 | | | | | | | | | | | 44.#41 x12 Kill Keep x12 | | | | | | | | | | | 44.#42 x13 Kill Keep x13 | | | | | | | | | | | 44.#43 x14 Kill Keep x14 | | | | | | | | | | | 44.#44 x15 Kill Keep x15 | | | | | | | | | | | 44.#45 xip0 Kill Keep xip0 | | | | | | | | | | | 44.#46 xip1 Kill Keep xip1 | | | | | | | | | | | 44.#47 lr Kill Keep lr | | | | | | | | | | | [000014] 48.#48 C11 Def Alloc x0 |C11a| | | | | | | | | | [000015] 49.#49 x0 Fixd Keep x0 |C11a| | | | | | | | | | 49.#50 C11 Use * Keep x0 |C11i| | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Register selection order: ABCDEFGHIJKLMNOPQ Total Tracked Vars: 3 Total Reg Cand Vars: 3 Total number of Intervals: 11 Total number of RefPositions: 50 Total Number of spill temps created: 0 .......... BB01 [ 100.00]: COVERS = 2, RELATED_PREFERENCE = 1, REG_ORDER = 6 .......... Total SpillCount : 0 Weighted: 0.000000 Total CopyReg : 0 Weighted: 0.000000 Total ResolutionMovs : 0 Weighted: 0.000000 Total SplitEdges : 0 Weighted: 0.000000 .......... Total COVERS [# 4] : 2 Weighted: 200.000000 Total RELATED_PREFERENCE [# 7] : 1 Weighted: 100.000000 Total REG_ORDER [#13] : 6 Weighted: 600.000000 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(x0) BB01 [000..019) (return), preds={} succs={} ===== N003. IL_OFFSET INLRT @ 0x000[E-] N005. x1 = CNS_INT(h) 0xd1ffab1e static Fseq[s_2] * N007. V03(x1); x1 N009. V03(x1) N011. x2 = CNS_INT 1 N013. STOREIND ; x1,x2 N015. IL_OFFSET INLRT @ 0x006[E-] N017. V03(x1*) N019. x1 = IND ; x1* N021. x1 = NEG ; x1 * N023. V00(x0); x1 N025. IL_OFFSET INLRT @ 0x00F[E-] N027. V00(x0) N029. V00(x0*) N031. x0 = AND ; x0,x0* * N033. V02(x0); x0 N035. V02(x0*) N037. x0 = PUTARG_REG; x0* N039. x1 = CNS_INT(h) 0xd1ffab1e ftn N041. x1 = IND ; x1 N043. CALL ; x0,x1 N045. IL_OFFSET INLRT @ 0x017[E-] N047. x0 = CNS_INT 0 N049. RETURN ; x0 Var=Reg end of BB01: none *************** Finishing PHASE Linear scan register alloc Trees after Linear scan register alloc ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..019) (return), preds={} succs={} N003 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N005 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] REG x1 $100 /--* t1 long N007 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 x1 REG x1 N009 ( 1, 1) [000026] ----------- t26 = LCL_VAR long V03 cse1 u:1 x1 REG x1 $100 N011 ( 1, 2) [000000] ----------- t0 = CNS_INT int 1 REG x2 $42 /--* t26 long +--* t0 int N013 (???,???) [000030] -A--G------ * STOREIND short REG NA N015 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA N017 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 x1 (last use) REG x1 $100 /--* t28 long N019 ( 4, 3) [000005] n---G------ t5 = * IND short REG x1 /--* t5 short N021 ( 5, 4) [000006] ----G------ t6 = * NEG int REG x1 /--* t6 int N023 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 x0 REG x0 N025 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x00F[E-] REG NA N027 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 x0 REG x0 N029 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 x0 (last use) REG x0 /--* t10 int +--* t11 int N031 ( 5, 5) [000012] ----------- t12 = * AND int REG x0 /--* t12 int N033 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 x0 REG x0 N035 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 x0 (last use) REG x0 /--* t22 int N037 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG x0 N039 ( 3, 12) [000035] H---------- t35 = CNS_INT(h) long 0xd1ffab1e ftn REG x1 /--* t35 long N041 ( 6, 14) [000036] ----------- t36 = * IND long REG x1 /--* t34 int arg0 in x0 +--* t36 long control expr N043 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) REG NA $VN.Void N045 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x017[E-] REG NA N047 ( 1, 2) [000014] ----------- t14 = CNS_INT int 0 REG x0 $40 /--* t14 int N049 ( 2, 3) [000015] ----------- * RETURN int REG NA $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Place 'align' instructions *************** Finishing PHASE Place 'align' instructions [no changes] *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 Modified regs: [x0-xip1 lr] Callee-saved registers pushed: 2 [fp lr] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Setting genSaveFpLrWithAllCalleeSavedRegisters to false --- delta bump 16 for FP frame --- virtual stack offset to actual stack offset delta is 16 -- V01 was 0, now 16 ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 5, 5 ) ubyte -> x0 ;# V01 OutArgs [V01 ] ( 1, 1 ) struct ( 0) [sp+00H] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 cse0 [V02,T02] ( 2, 2 ) int -> x0 "CSE - aggressive" ; V03 cse1 [V03,T01] ( 3, 3 ) long -> x1 "CSE - aggressive" ; ; Lcl frame size = 0 Created: G_M26363_IG02: ; offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} Mark labels for codegen BB01 : first block *************** After genMarkLabelsForCodegen() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..019) (return) i label hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- Setting stack level from -572662307 to 0 =============== Generating BB01 [000..019) (return), preds={} succs={} flags=0x00000001.00220011: i label hascall gcsafe LIR BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} Recording Var Locations at start of BB01 Liveness not changing: 0000000000000000 {} Live regs: (unchanged) 0000 {} GC regs: (unchanged) 0000 {} Byref regs: (unchanged) 0000 {} L_M26363_BB01: Label: G_M26363_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} Scope info: begin block BB01, IL range [000..019) Added IP mapping: 0x0000 STACK_EMPTY (G_M26363_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA Generating: N005 ( 3, 12) [000001] H---------- t1 = CNS_INT(h) long 0xd1ffab1e static Fseq[s_2] REG x1 $100 Mapped BB01 to G_M26363_IG02 IN0001: movz x1, #0xD1FFAB1E // data for test.Program:s_2 IN0002: movk x1, #0xD1FFAB1E LSL #16 IN0003: movk x1, #0xD1FFAB1E LSL #32 /--* t1 long Generating: N007 ( 3, 12) [000025] DA--------- * STORE_LCL_VAR long V03 cse1 d:1 x1 REG x1 V03 in reg x1 is becoming live [000025] Live regs: 0000 {} => 0002 {x1} Live vars after [000025]: {} => {V03} Generating: N009 ( 1, 1) [000026] ----------- t26 = LCL_VAR long V03 cse1 u:1 x1 REG x1 $100 Generating: N011 ( 1, 2) [000000] ----------- t0 = CNS_INT int 1 REG x2 $42 IN0004: mov w2, #1 /--* t26 long +--* t0 int Generating: N013 (???,???) [000030] -A--G------ * STOREIND short REG NA IN0005: strh w2, [x1] Added IP mapping: 0x0006 STACK_EMPTY (G_M26363_IG02,ins#5,ofs#20) Generating: N015 (???,???) [000031] ----------- IL_OFFSET void INLRT @ 0x006[E-] REG NA Generating: N017 ( 1, 1) [000028] ----------- t28 = LCL_VAR long V03 cse1 u:1 x1 (last use) REG x1 $100 /--* t28 long Generating: N019 ( 4, 3) [000005] n---G------ t5 = * IND short REG x1 V03 in reg x1 is becoming dead [000028] Live regs: 0002 {x1} => 0000 {} Live vars after [000028]: {V03} => {} IN0006: ldrsh w1, [x1] /--* t5 short Generating: N021 ( 5, 4) [000006] ----G------ t6 = * NEG int REG x1 IN0007: neg w1, w1 /--* t6 int Generating: N023 ( 5, 4) [000009] DA--G------ * STORE_LCL_VAR ubyte V00 arg0 d:2 x0 REG x0 IN0008: mov w0, w1 V00 in reg x0 is becoming live [000009] Live regs: 0000 {} => 0001 {x0} New debug range: first Live vars after [000009]: {} => {V00} Added IP mapping: 0x000F STACK_EMPTY (G_M26363_IG02,ins#8,ofs#32) Generating: N025 (???,???) [000032] ----------- IL_OFFSET void INLRT @ 0x00F[E-] REG NA Generating: N027 ( 2, 2) [000010] ----------- t10 = LCL_VAR int V00 arg0 u:2 x0 REG x0 Generating: N029 ( 2, 2) [000011] ----------- t11 = LCL_VAR int V00 arg0 u:2 x0 (last use) REG x0 /--* t10 int +--* t11 int Generating: N031 ( 5, 5) [000012] ----------- t12 = * AND int REG x0 V00 in reg x0 is becoming dead [000011] Live regs: 0001 {x0} => 0000 {} Closing debug range. Live vars after [000011]: {V00} => {} IN0009: and w0, w0, w0 /--* t12 int Generating: N033 ( 5, 5) [000019] DA--------- * STORE_LCL_VAR int V02 cse0 d:1 x0 REG x0 V02 in reg x0 is becoming live [000019] Live regs: 0000 {} => 0001 {x0} Live vars after [000019]: {} => {V02} Generating: N035 ( 1, 1) [000022] ----------- t22 = LCL_VAR int V02 cse0 u:1 x0 (last use) REG x0 /--* t22 int Generating: N037 (???,???) [000034] ----------- t34 = * PUTARG_REG int REG x0 V02 in reg x0 is becoming dead [000022] Live regs: 0001 {x0} => 0000 {} Live vars after [000022]: {V02} => {} Generating: N039 ( 3, 12) [000035] H---------- t35 = CNS_INT(h) long 0xd1ffab1e ftn REG x1 IN000a: movz x1, #0xD1FFAB1E // code for System.Console:WriteLine(int) IN000b: movk x1, #0xD1FFAB1E LSL #16 IN000c: movk x1, #0xD1FFAB1E LSL #32 /--* t35 long Generating: N041 ( 6, 14) [000036] ----------- t36 = * IND long REG x1 IN000d: ldr x1, [x1] /--* t34 int arg0 in x0 +--* t36 long control expr Generating: N043 ( 20, 9) [000013] --CXG------ * CALL void System.Console:WriteLine(int) REG NA $VN.Void Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {} IN000e: blr x1 Added IP mapping: 0x0017 STACK_EMPTY (G_M26363_IG02,ins#14,ofs#56) Generating: N045 (???,???) [000033] ----------- IL_OFFSET void INLRT @ 0x017[E-] REG NA Generating: N047 ( 1, 2) [000014] ----------- t14 = CNS_INT int 0 REG x0 $40 IN000f: mov w0, wzr /--* t14 int Generating: N049 ( 2, 3) [000015] ----------- * RETURN int REG NA $VN.Void Added IP mapping: EPILOG (G_M26363_IG02,ins#15,ofs#60) label Reserving epilog IG for block BB01 Saved: G_M26363_IG02: ; offs=000000H, size=003CH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref Created: G_M26363_IG03: ; offs=00003CH, size=0000H, bbWeight=1, gcrefRegs=0000 {} *************** After placeholder IG creation G_M26363_IG01: ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG G_M26363_IG02: ; offs=000000H, size=003CH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref G_M26363_IG03: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {} Variable Live Range History Dump for BB01 V00 arg0: x0 [(G_M26363_IG02,ins#8,ofs#32), (G_M26363_IG02,ins#8,ofs#32)] Liveness not changing: 0000000000000000 {} # compCycleEstimate = 37, compSizeEstimate = 35 test.Program:M8(ubyte):uint ; Final local variable assignments ; ; V00 arg0 [V00,T00] ( 5, 5 ) ubyte -> x0 ;# V01 OutArgs [V01 ] ( 1, 1 ) struct ( 0) [sp+00H] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V02 cse0 [V02,T02] ( 2, 2 ) int -> x0 "CSE - aggressive" ; V03 cse1 [V03,T01] ( 3, 3 ) long -> x1 "CSE - aggressive" ; ; Lcl frame size = 0 *************** Before prolog / epilog generation G_M26363_IG01: ; func=00, offs=000000H, size=0000H, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG G_M26363_IG02: ; offs=000000H, size=003CH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref G_M26363_IG03: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {} Recording Var Locations at start of BB01 *************** In genFnProlog() Added IP mapping to front: PROLOG (G_M26363_IG01,ins#0,ofs#0) label __prolog: New debug range: first Save float regs: [] Save int regs: [fp lr] Frame type 1. #outsz=0; #framesz=16; LclFrameSize=0 IN0010: stp fp, lr, [sp, #-0x10]! offset=16, calleeSaveSpDelta=0 offsetSpToSavedFp=0 IN0011: mov fp, sp *************** In genFnPrologCalleeRegArgs() for int regs *************** In genEnregisterIncomingStackArgs() Closing debug range. Saved: G_M26363_IG01: ; offs=000000H, size=0008H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {} Frame type 1. #outsz=0; #framesz=16; localloc? false calleeSaveSpOffset=16, calleeSaveSpDelta=0 IN0012: ldp fp, lr, [sp], #0x10 IN0013: ret lr Saved: G_M26363_IG03: ; offs=00003CH, size=0008H, bbWeight=1, epilog, nogc, extend 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M26363_IG01: ; func=00, offs=000000H, size=0008H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG G_M26363_IG02: ; offs=000008H, size=003CH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref G_M26363_IG03: ; offs=000044H, size=0008H, bbWeight=1, epilog, nogc, extend *************** In emitJumpDistBind() Emitter Jump List: total jump count: 0 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x4C bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0xc) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M26363_IG01: ; offs=000000H, size=0008H, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG IN0010: 000000 stp fp, lr, [sp, #-0x10]! IN0011: 000004 mov fp, sp ;; size=8 bbWeight=1 PerfScore 1.50 G_M26363_IG02: ; offs=000008H, size=003CH, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref IN0001: 000008 movz x1, #0xD1FFAB1E // data for test.Program:s_2 IN0002: 00000C movk x1, #0xD1FFAB1E LSL #16 IN0003: 000010 movk x1, #0xD1FFAB1E LSL #32 IN0004: 000014 mov w2, #1 IN0005: 000018 strh w2, [x1] IN0006: 00001C ldrsh w1, [x1] IN0007: 000020 neg w1, w1 IN0008: 000024 mov w0, w1 IN0009: 000028 and w0, w0, w0 IN000a: 00002C movz x1, #0xD1FFAB1E // code for System.Console:WriteLine(int) IN000b: 000030 movk x1, #0xD1FFAB1E LSL #16 IN000c: 000034 movk x1, #0xD1FFAB1E LSL #32 IN000d: 000038 ldr x1, [x1] ; Call at 003C [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {} IN000e: 00003C blr x1 IN000f: 000040 mov w0, wzr ;; size=60 bbWeight=1 PerfScore 13.50 G_M26363_IG03: ; offs=000044H, size=0008H, bbWeight=1, epilog, nogc, extend IN0012: 000044 ldp fp, lr, [sp], #0x10 IN0013: 000048 ret lr ;; size=8 bbWeight=1 PerfScore 2.00Allocated method code size = 76 , actual size = 76, unused size = 0 ; Total bytes of code 76, prolog size 8, PerfScore 24.60, instruction count 19, allocated bytes for code 76 (MethodHash=d6309904) for method test.Program:M8(ubyte):uint ; ============================================================ *************** After end code gen, before unwindEmit() G_M26363_IG01: ; func=00, offs=000000H, size=0008H, bbWeight=1, PerfScore 1.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG IN0010: 000000 stp fp, lr, [sp, #-0x10]! IN0011: 000004 mov fp, sp G_M26363_IG02: ; offs=000008H, size=003CH, bbWeight=1, PerfScore 13.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref IN0001: 000008 movz x1, #0xD1FFAB1E // data for test.Program:s_2 IN0002: 00000C movk x1, #0xD1FFAB1E LSL #16 IN0003: 000010 movk x1, #0xD1FFAB1E LSL #32 IN0004: 000014 mov w2, #1 IN0005: 000018 strh w2, [x1] IN0006: 00001C ldrsh w1, [x1] IN0007: 000020 neg w1, w1 IN0008: 000024 mov w0, w1 IN0009: 000028 and w0, w0, w0 IN000a: 00002C movz x1, #0xD1FFAB1E // code for System.Console:WriteLine(int) IN000b: 000030 movk x1, #0xD1FFAB1E LSL #16 IN000c: 000034 movk x1, #0xD1FFAB1E LSL #32 IN000d: 000038 ldr x1, [x1] IN000e: 00003C blr x1 IN000f: 000040 mov w0, wzr G_M26363_IG03: ; offs=000044H, size=0008H, bbWeight=1, PerfScore 2.00, epilog, nogc, extend IN0012: 000044 ldp fp, lr, [sp], #0x10 IN0013: 000048 ret lr *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0xd1ffab1e (not in unwind data) Code Words : 1 Epilog Count : 1 E bit : 0 X bit : 0 Vers : 0 Function Length : 19 (0x00013) Actual length = 76 (0x00004c) ---- Epilog scopes ---- ---- Scope 0 Epilog Start Offset : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e) Epilog Start Index : 1 (0x01) ---- Unwind codes ---- E1 set_fp; mov fp, sp ---- Epilog start at index 1 ---- 81 save_fplr_x #1 (0x01); stp fp, lr, [sp, #-16]! E4 end E4 end allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x4c, unwindSize=0xc, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 6 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000008 ( STACK_EMPTY ) IL offs 0x0006 : 0x0000001C ( STACK_EMPTY ) IL offs 0x000F : 0x00000028 ( STACK_EMPTY ) IL offs 0x0017 : 0x00000040 ( STACK_EMPTY ) IL offs EPILOG : 0x00000044 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 2 ; Variable debug info: 2 live ranges, 1 vars for method test.Program:M8(ubyte):uint (V00 arg0) : From 00000000h to 00000008h, in x0 (V00 arg0) : From 00000028h to 00000029h, in x0 *************** In gcInfoBlockHdrSave() Set code length to 76. Set ReturnKind to Scalar. Set stack base register to fp. Set Outgoing stack arg area size to 0. Defining 1 call sites: Offset 0x3c, size 4. *************** Finishing PHASE Emit GC+EH tables Method code size: 76 Allocations for test.Program:M8(ubyte):uint (MethodHash=d6309904) count: 498, size: 62963, max = 5848 allocateMemory: 131072, nraUsed: 65616 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6500 | 10.32% ASTNode | 5632 | 8.94% InstDesc | 6640 | 10.55% ImpStack | 384 | 0.61% BasicBlock | 656 | 1.04% CallArgs | 88 | 0.14% FlowEdge | 0 | 0.00% TreeStatementList | 128 | 0.20% SiScope | 0 | 0.00% DominatorMemory | 96 | 0.15% LSRA | 7380 | 11.72% LSRA_Interval | 960 | 1.52% LSRA_RefPosition | 4080 | 6.48% Reachability | 40 | 0.06% SSA | 288 | 0.46% ValueNumber | 8922 | 14.17% LvaTable | 1688 | 2.68% UnwindInfo | 32 | 0.05% hashBv | 40 | 0.06% bitset | 32 | 0.05% FixedBitVect | 16 | 0.03% Generic | 1046 | 1.66% LocalAddressVisitor | 0 | 0.00% FieldSeqStore | 144 | 0.23% MemorySsaMap | 40 | 0.06% MemoryPhiArg | 0 | 0.00% CSE | 1536 | 2.44% GC | 1285 | 2.04% CorTailCallInfo | 0 | 0.00% Inlining | 904 | 1.44% ArrayStack | 0 | 0.00% DebugInfo | 328 | 0.52% DebugOnly | 12109 | 19.23% Codegen | 1088 | 1.73% LoopOpt | 0 | 0.00% LoopClone | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 49 | 0.08% RangeCheck | 0 | 0.00% CopyProp | 248 | 0.39% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 328 | 0.52% ClassLayout | 80 | 0.13% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 176 | 0.28% Pgo | 0 | 0.00% ****** DONE compiling test.Program:M8(ubyte):uint