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[arm64] sxtb, sxth, sxtw instructions disassembly incorrect #35303

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BruceForstall opened this issue Apr 22, 2020 · 3 comments · Fixed by #35379
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[arm64] sxtb, sxth, sxtw instructions disassembly incorrect #35303

BruceForstall opened this issue Apr 22, 2020 · 3 comments · Fixed by #35379
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@echesakov
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area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
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@BruceForstall
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The JIT disassembly for the sxtw instruction is:

sxtw    x0, x21

It should instead use the w register form in the second position:

sxtw    x0, w21
@BruceForstall BruceForstall added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Apr 22, 2020
@BruceForstall BruceForstall added this to the Future milestone Apr 22, 2020
@Dotnet-GitSync-Bot Dotnet-GitSync-Bot added the untriaged New issue has not been triaged by the area owner label Apr 22, 2020
@BruceForstall
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cc @kunalspathak (since you are looking at arm64 disassembly issues)

@BruceForstall BruceForstall removed the untriaged New issue has not been triaged by the area owner label Apr 22, 2020
@echesakov
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sxtb and sxth as well

IN0291: 000A48  93401D47          sxtb    x7, x10
IN0292: 000A4C  93403D65          sxth    x5, x11

@echesakov echesakov changed the title [arm64] sxtw instruction disassembly incorrect [arm64] sxtb, sxth, sxtw instructions disassembly incorrect Apr 22, 2020
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echesakov commented Apr 23, 2020 •
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I am going to fix this since I am working nearby

@echesakov echesakov self-assigned this Apr 23, 2020
@echesakov echesakov mentioned this issue Apr 23, 2020
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[Arm64] ASIMD Implement widening, narrowing, saturating instructions echesakov/runtime
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