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LSRA: Avoiding reg spill to memory when reg-value is consistent with memory #6761

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sivarv opened this issue Oct 3, 2016 · 4 comments
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area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI enhancement Product code improvement that does NOT require public API changes/additions optimization tenet-performance Performance related issue
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@sivarv
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sivarv commented Oct 3, 2016

Say a local variable is allocated a reg loaded its value from memory. Say there were many uses of local variable in IR and afterwards local variable needs to be spilled due to register pressure. We can avoid writing reg back to memory if there are no intervening updates to reg on the path where it was loaded from memory to the point where it needs to be spilled.

category:cq
theme:register-allocator
skill-level:expert
cost:medium
impact:medium

@sivarv sivarv self-assigned this Oct 3, 2016
@sivarv sivarv assigned russellhadley and unassigned sivarv Mar 9, 2017
@voinokin
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voinokin commented Jun 25, 2018

This becomes worse with SIMD registers.
Noted with HW intrinsics API - say, there are several SIMD registers used as "seeds" with constant values during calculations, and it comes that some of them got spilled and reloaded within the same basic block all the way due to algorithm's extensive use of such "seeds".

@erozenfeld
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/cc: @dotnet/jit-contrib

@CarolEidt
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This is something that I'd like to see supported, and it makes sense to do this as part of enregistering vars that are live across exception handlers (#6001, dotnet/coreclr#10630), as that also involves tracking of lclVars that are valid in memory.

@msftgits msftgits transferred this issue from dotnet/coreclr Jan 31, 2020
@msftgits msftgits added this to the Future milestone Jan 31, 2020
@kunalspathak kunalspathak self-assigned this May 4, 2021
@kunalspathak
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From #41704, this is also true if there are loads from memory from same location although copy prop should have taken care of this.

  blo     G_M31903_IG88
  ldr     x19, [fp,#48]	// [V133 tmp130]
  ldr     w1, [fp,#56]	// [V134 tmp131]
  add     w20, w1, #5
  ldr     w1, [fp,#60]	// [V135 tmp132]
  sub     w21, w1, #5
  ldr     x1, [fp,#48]	// [V133 tmp130]
  cbz     x1, G_M31903_IG13

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area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI enhancement Product code improvement that does NOT require public API changes/additions optimization tenet-performance Performance related issue
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