From e3867d1040bae8fac97ec85d50f9847845340da4 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Tue, 20 Aug 2024 14:02:31 +0100 Subject: [PATCH 1/3] ARM64-SVE: Always convert to mask for mask APIs --- src/coreclr/jit/hwintrinsic.cpp | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index 9d3db42ec4c09..41ed343712beb 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -2261,11 +2261,9 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, } #if defined(FEATURE_MASKED_HW_INTRINSICS) && defined(TARGET_ARM64) - auto convertToMaskIfNeeded = [&](GenTree*& op) { - if (!varTypeIsMask(op)) - { - op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); - } + auto convertToMask = [&](GenTree*& op) { + assert(varTypeIsSIMD(op)); + op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); }; if (HWIntrinsicInfo::IsExplicitMaskedOperation(intrinsic)) @@ -2278,7 +2276,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, case NI_Sve_CreateBreakBeforePropagateMask: { // HWInstrinsic requires a mask for op3 - convertToMaskIfNeeded(retNode->AsHWIntrinsic()->Op(3)); + convertToMask(retNode->AsHWIntrinsic()->Op(3)); FALLTHROUGH; } case NI_Sve_CreateBreakAfterMask: @@ -2291,13 +2289,13 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, case NI_Sve_TestLastTrue: { // HWInstrinsic requires a mask for op2 - convertToMaskIfNeeded(retNode->AsHWIntrinsic()->Op(2)); + convertToMask(retNode->AsHWIntrinsic()->Op(2)); FALLTHROUGH; } default: { // HWInstrinsic requires a mask for op1 - convertToMaskIfNeeded(retNode->AsHWIntrinsic()->Op(1)); + convertToMask(retNode->AsHWIntrinsic()->Op(1)); break; } } @@ -2317,8 +2315,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, { case NI_Sve_CreateBreakPropagateMask: { - convertToMaskIfNeeded(retNode->AsHWIntrinsic()->Op(1)); - convertToMaskIfNeeded(retNode->AsHWIntrinsic()->Op(2)); + convertToMask(retNode->AsHWIntrinsic()->Op(1)); + convertToMask(retNode->AsHWIntrinsic()->Op(2)); break; } From 8cf6d25b376bff313e6f1cb165b381bcc0ad5c16 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Tue, 20 Aug 2024 16:29:01 +0100 Subject: [PATCH 2/3] Remove convertToMask --- src/coreclr/jit/hwintrinsic.cpp | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index 41ed343712beb..969fbd112e3bc 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -2261,11 +2261,6 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, } #if defined(FEATURE_MASKED_HW_INTRINSICS) && defined(TARGET_ARM64) - auto convertToMask = [&](GenTree*& op) { - assert(varTypeIsSIMD(op)); - op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); - }; - if (HWIntrinsicInfo::IsExplicitMaskedOperation(intrinsic)) { assert(numArgs > 0); @@ -2276,7 +2271,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, case NI_Sve_CreateBreakBeforePropagateMask: { // HWInstrinsic requires a mask for op3 - convertToMask(retNode->AsHWIntrinsic()->Op(3)); + GenTree*& op = retNode->AsHWIntrinsic()->Op(3); + op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); FALLTHROUGH; } case NI_Sve_CreateBreakAfterMask: @@ -2289,13 +2285,15 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, case NI_Sve_TestLastTrue: { // HWInstrinsic requires a mask for op2 - convertToMask(retNode->AsHWIntrinsic()->Op(2)); + GenTree*& op = retNode->AsHWIntrinsic()->Op(2); + op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); FALLTHROUGH; } default: { // HWInstrinsic requires a mask for op1 - convertToMask(retNode->AsHWIntrinsic()->Op(1)); + GenTree*& op = retNode->AsHWIntrinsic()->Op(1); + op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); break; } } @@ -2315,8 +2313,10 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, { case NI_Sve_CreateBreakPropagateMask: { - convertToMask(retNode->AsHWIntrinsic()->Op(1)); - convertToMask(retNode->AsHWIntrinsic()->Op(2)); + GenTree*& op1 = retNode->AsHWIntrinsic()->Op(1); + GenTree*& op2 = retNode->AsHWIntrinsic()->Op(2); + op1 = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op1, simdBaseJitType, simdSize); + op2 = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op2, simdBaseJitType, simdSize); break; } From 88fc306291b37ed81a5112ee3427874d5d0e1c29 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Tue, 20 Aug 2024 16:47:10 +0100 Subject: [PATCH 3/3] fix formatting --- src/coreclr/jit/hwintrinsic.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/coreclr/jit/hwintrinsic.cpp b/src/coreclr/jit/hwintrinsic.cpp index 969fbd112e3bc..058420d0ac4b2 100644 --- a/src/coreclr/jit/hwintrinsic.cpp +++ b/src/coreclr/jit/hwintrinsic.cpp @@ -2272,7 +2272,7 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, { // HWInstrinsic requires a mask for op3 GenTree*& op = retNode->AsHWIntrinsic()->Op(3); - op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); + op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); FALLTHROUGH; } case NI_Sve_CreateBreakAfterMask: @@ -2286,14 +2286,14 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, { // HWInstrinsic requires a mask for op2 GenTree*& op = retNode->AsHWIntrinsic()->Op(2); - op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); + op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); FALLTHROUGH; } default: { // HWInstrinsic requires a mask for op1 GenTree*& op = retNode->AsHWIntrinsic()->Op(1); - op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); + op = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op, simdBaseJitType, simdSize); break; } } @@ -2315,8 +2315,8 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic, { GenTree*& op1 = retNode->AsHWIntrinsic()->Op(1); GenTree*& op2 = retNode->AsHWIntrinsic()->Op(2); - op1 = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op1, simdBaseJitType, simdSize); - op2 = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op2, simdBaseJitType, simdSize); + op1 = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op1, simdBaseJitType, simdSize); + op2 = gtNewSimdCvtVectorToMaskNode(TYP_MASK, op2, simdBaseJitType, simdSize); break; }