From c39be0e85a8cc47772a351fe9fa5f5a70382432c Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Fri, 5 Mar 2021 00:25:50 -0800 Subject: [PATCH 1/3] Unassign register for RefTypeDef if it is not assigned register Fix failures exposed by EHWriteThru: https://dev.azure.com/dnceng/public/_build/results?buildId=1021926&view=ms.vss-test-web.build-test-results-tab&runId=31791570&resultId=180705&paneView=dotnet-dnceng.dnceng-build-release-tasks.helix-test-information-tab https://helixre8s23ayyeko0k025g8.blob.core.windows.net/dotnet-runtime-refs-pull-47307-head-ad03bd78ebf7456dbe/System.Memory.Tests/console.387c2cf0.log?sv=2019-07-07&se=2021-03-24T01%3A36%3A31Z&sr=c&sp=rl&sig=hPD%2B625ykQtQRVKnl3pCZzTEiI5hXzrqZtIPgo6Wc74%3D --- src/coreclr/jit/lsra.cpp | 15 +++++++++++++++ src/coreclr/jit/lsra.h | 5 +---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index 31127e89afd75..fd56573094956 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -10955,6 +10955,21 @@ void LinearScan::verifyFinalAllocation() } if (regNum == REG_NA) { + // If this interval is still assigned to a register + if (interval->physReg != REG_NA) + { + // then unassign it if no new register was assigned to the RefTypeDef + if (RefTypeIsDef(currentRefPosition->refType)) + { + assert(interval->assignedReg != nullptr); + if (interval->assignedReg->assignedInterval == interval) + { + interval->assignedReg->assignedInterval = nullptr; + } + interval->assignedReg = nullptr; + } + } + dumpLsraAllocationEvent(LSRA_EVENT_NO_REG_ALLOCATED, interval); } else if (RefTypeIsDef(currentRefPosition->refType)) diff --git a/src/coreclr/jit/lsra.h b/src/coreclr/jit/lsra.h index 345cbb451f788..e321f14807442 100644 --- a/src/coreclr/jit/lsra.h +++ b/src/coreclr/jit/lsra.h @@ -510,9 +510,6 @@ class RegRecord : public Referenceable void tinyDump(); #endif // DEBUG - // RefPosition * getNextRefPosition(); - // LsraLocation getNextRefLocation(); - // DATA // interval to which this register is currently allocated. @@ -1512,7 +1509,7 @@ class LinearScan : public LinearScanInterface // For SIMD types longer than 8 bytes Caller is responsible for saving and restoring Upper bytes. return ((type == TYP_SIMD16) || (type == TYP_SIMD12)); } - static const var_types LargeVectorSaveType = TYP_DOUBLE; + static const var_types LargeVectorSaveType = TYP_DOUBLE; #else // !defined(TARGET_AMD64) && !defined(TARGET_ARM64) #error("Unknown target architecture for FEATURE_SIMD") #endif // !defined(TARGET_AMD64) && !defined(TARGET_ARM64) From 92ac2fe1350a0789f4fa4e32a17817c0a65ed83a Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Fri, 5 Mar 2021 14:53:00 -0800 Subject: [PATCH 2/3] Fix more asserts for spillAfter/Def where assignedInterval was not reset Fixes errors like this: https://dev.azure.com/dnceng/public/_build/results?buildId=1024357&view=ms.vss-test-web.build-test-results-tab&runId=31848698&resultId=181011&paneView=dotnet-dnceng.dnceng-build-release-tasks.helix-test-information-tab https://helixre8s23ayyeko0k025g8.blob.core.windows.net/dotnet-runtime-refs-pull-47307-head-2f177492e7644d448d/System.Management.Tests/console.5337e574.log?sv=2019-07-07&se=2021-03-25T09%3A27%3A01Z&sr=c&sp=rl&sig=aBfB4tstmjMyucEadkhaFxtWdog3teT32PvzPAS4Vv4%3D --- src/coreclr/jit/lsra.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index fd56573094956..2fb95562f7abe 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -10966,6 +10966,7 @@ void LinearScan::verifyFinalAllocation() { interval->assignedReg->assignedInterval = nullptr; } + interval->physReg = REG_NA; interval->assignedReg = nullptr; } } @@ -11108,6 +11109,16 @@ void LinearScan::verifyFinalAllocation() { assert(!currentRefPosition->spillAfter || currentRefPosition->IsActualRef()); + if (RefTypeIsDef(currentRefPosition->refType)) + { + // If an interval got assigned to a different register (while the different + // register got spilled), then clear the assigned interval of current register. + if (interval->physReg != REG_NA && interval->physReg != regNum) + { + interval->assignedReg->assignedInterval = nullptr; + } + } + interval->physReg = REG_NA; interval->assignedReg = nullptr; From 8cc10f61f044c30e686d7686a630db5765566fe9 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Mon, 8 Mar 2021 14:37:20 -0800 Subject: [PATCH 3/3] jit format --- src/coreclr/jit/lsra.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/lsra.h b/src/coreclr/jit/lsra.h index e321f14807442..f381e223ae781 100644 --- a/src/coreclr/jit/lsra.h +++ b/src/coreclr/jit/lsra.h @@ -1509,7 +1509,7 @@ class LinearScan : public LinearScanInterface // For SIMD types longer than 8 bytes Caller is responsible for saving and restoring Upper bytes. return ((type == TYP_SIMD16) || (type == TYP_SIMD12)); } - static const var_types LargeVectorSaveType = TYP_DOUBLE; + static const var_types LargeVectorSaveType = TYP_DOUBLE; #else // !defined(TARGET_AMD64) && !defined(TARGET_ARM64) #error("Unknown target architecture for FEATURE_SIMD") #endif // !defined(TARGET_AMD64) && !defined(TARGET_ARM64)