From 92c3032d61a6a8cca0b5b9da4339dcf678f5d94f Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Tue, 9 Jan 2024 12:11:24 +0000 Subject: [PATCH 01/15] Move arm64 insOpts entries into insGroupOpts insOpts has a max size of 6 bits, and it is getting full. For some of the options, they are only required to specify the encoding group, after this only the lane size (_S etc) is needed. Move these to a new enum insGroupOpts. --- src/coreclr/jit/codegenarm64test.cpp | 356 +++++++++++++-------------- src/coreclr/jit/emitarm64.cpp | 124 +++++----- src/coreclr/jit/emitarm64.h | 50 ++-- src/coreclr/jit/instr.h | 23 +- 4 files changed, 262 insertions(+), 291 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index 2dad168edd770..a6210af54e762 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4718,12 +4718,12 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_S); // LSRR ., /M, ., . // IF_SVE_AO_3A - theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V4, REG_P3, REG_V24, - INS_OPTS_SCALABLE_WIDE_B); // ASR ., /M, ., .D - theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V19, REG_P7, REG_V3, - INS_OPTS_SCALABLE_WIDE_H); // LSL ., /M, ., .D - theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, - INS_OPTS_SCALABLE_WIDE_S); // LSR ., /M, ., .D + theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V4, REG_P3, REG_V24, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WIDE); // ASR ., /M, ., .D + theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V19, REG_P7, REG_V3, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WIDE); // LSL ., /M, ., .D + theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WIDE); // LSR ., /M, ., .D // IF_SVE_CM_3A theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_SCALABLE, REG_V31, REG_P7, REG_V31, @@ -4732,23 +4732,23 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_D); // CLASTB ., , ., . // IF_SVE_CN_3A - theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // CLASTA , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // CLASTB , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); // CLASTB , , , . + theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTA , , , . + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . // IF_SVE_CO_3A // Note: EA_4BYTE used for B and H (destination register is W) - theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // CLASTA , , , . - theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // CLASTA , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // CLASTB , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // CLASTB , , , . + theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . + theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . // IF_SVE_CX_4A theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_SCALABLE, REG_P15, REG_P0, REG_V0, REG_V10, @@ -4859,12 +4859,12 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_H); // FMINP ., /M, ., . // IF_SVE_HJ_3A - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // FADDA , , , . - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // FADDA , , , . - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); // FADDA , , , . + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . // IF_SVE_HL_3A theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11, @@ -4901,14 +4901,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_D); // FSUBR ., /M, ., . // IF_SVE_AF_3A - theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0, - INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); // ANDV , , . - theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // EORV , , . - theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // ORV , , . - theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); // ORV , , . + theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ANDV , , . + theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // EORV , , . + theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . + theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . // IF_SVE_AG_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4923,12 +4923,12 @@ void CodeGen::genArm64EmitterUnitTestsSve() #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_AI_3A - theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2, - INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); // SADDV
, , . - theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // SADDV
, , . - theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // UADDV
, , . + theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . + theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . + theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UADDV
, , . // IF_SVE_AJ_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4937,14 +4937,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_AK_3A - theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); // SMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // SMINV , , . - theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // UMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31, - INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); // UMINV , , . + theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMAXV , , . + theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMINV , , . + theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMAXV , , . + theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMINV , , . // IF_SVE_AL_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -5023,46 +5023,46 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_D); // COMPACT ., , . // IF_SVE_CP_3A - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_1BYTE, REG_V14, REG_P1, REG_V11, - INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V13, REG_P2, REG_V10, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_2BYTE, REG_V12, REG_P3, REG_V9, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // MOV ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_V11, REG_P4, REG_V8, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); // MOV ., /M, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_1BYTE, REG_V14, REG_P1, REG_V11, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V13, REG_P2, REG_V10, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_2BYTE, REG_V12, REG_P3, REG_V9, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_V11, REG_P4, REG_V8, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, // IF_SVE_CQ_3A // Note: EA_4BYTE used for B and H (source register is W) - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_V10, REG_P5, REG_SP, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V9, REG_P6, REG_R30, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V8, REG_P7, REG_R29, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // MOV ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V7, REG_P0, REG_R28, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // MOV ., /M, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_V10, REG_P5, REG_SP, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V9, REG_P6, REG_R30, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V8, REG_P7, REG_R29, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V7, REG_P0, REG_R28, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, // IF_SVE_CR_3A - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_1BYTE, REG_V6, REG_P1, REG_V27, - INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_2BYTE, REG_V5, REG_P2, REG_V26, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_V4, REG_P3, REG_V25, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // LASTB , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_V3, REG_P4, REG_V24, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); // LASTB , , . + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_1BYTE, REG_V6, REG_P1, REG_V27, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_2BYTE, REG_V5, REG_P2, REG_V26, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_V4, REG_P3, REG_V25, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_V3, REG_P4, REG_V24, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . // IF_SVE_CS_3A // Note: EA_4BYTE used for B and H (source register is W) - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R1, REG_P5, REG_V23, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R0, REG_P6, REG_V22, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_R30, REG_P7, REG_V21, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // LASTB , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R29, REG_P0, REG_V20, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // LASTB , , . + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R1, REG_P5, REG_V23, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R0, REG_P6, REG_V22, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_R30, REG_P7, REG_V21, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R29, REG_P0, REG_V20, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . // IF_SVE_CU_3A theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19, @@ -5130,23 +5130,23 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_H); // UQRSHRN .H, {.S-.S }, # // IF_SVE_DM_2A - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_P0, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // DECP , . - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R1, REG_P1, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // DECP , . - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R2, REG_P2, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // DECP , . - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R3, REG_P3, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // DECP , . - - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R4, REG_P4, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // INCP , . - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R5, REG_P5, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // INCP , . - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R6, REG_P6, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // INCP , . - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R7, REG_P7, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // INCP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . // IF_SVE_DN_2A // Note: B is reserved @@ -5159,77 +5159,77 @@ void CodeGen::genArm64EmitterUnitTestsSve() theEmitter->emitIns_R_R(INS_sve_incp, EA_SCALABLE, REG_V5, REG_P5, INS_OPTS_SCALABLE_D); // INCP ., . // IF_SVE_DO_2A - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R0, REG_P0, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // SQDECP , ., - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R1, REG_P1, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // SQDECP , ., - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R2, REG_P2, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // SQDECP , ., - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R3, REG_P3, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // SQDECP , ., - - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R4, REG_P4, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // SQDECP , . - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R5, REG_P5, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // SQDECP , . - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R6, REG_P6, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // SQDECP , . - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R7, REG_P7, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // SQDECP , . - - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R0, REG_P0, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // SQINCP , ., - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R1, REG_P1, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // SQINCP , ., - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R2, REG_P2, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // SQINCP , ., - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R3, REG_P3, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // SQINCP , ., - - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R4, REG_P4, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // SQINCP , . - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R5, REG_P5, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // SQINCP , . - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R6, REG_P6, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // SQINCP , . - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R7, REG_P7, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // SQINCP , . - - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R0, REG_P0, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R1, REG_P1, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R2, REG_P2, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R3, REG_P3, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // UQDECP , . - - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R4, REG_P4, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R5, REG_P5, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R6, REG_P6, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R7, REG_P7, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // UQDECP , . - - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R0, REG_P0, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R1, REG_P1, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R2, REG_P2, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R3, REG_P3, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // UQINCP , . - - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R4, REG_P4, - INS_OPTS_SCALABLE_B_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R5, REG_P5, - INS_OPTS_SCALABLE_H_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R6, REG_P6, - INS_OPTS_SCALABLE_S_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R7, REG_P7, - INS_OPTS_SCALABLE_D_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . // IF_SVE_DP_2A // NOTE: B is reserved @@ -5337,16 +5337,16 @@ void CodeGen::genArm64EmitterUnitTestsSve() #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_HE_3A - theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_2BYTE, REG_V21, REG_P7, REG_V7, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // FADDV , , . - theEmitter->emitIns_R_R_R(INS_sve_fmaxnmv, EA_2BYTE, REG_V22, REG_P6, REG_V6, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); // FMAXNMV , , . - theEmitter->emitIns_R_R_R(INS_sve_fmaxv, EA_4BYTE, REG_V23, REG_P5, REG_V5, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // FMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_fminnmv, EA_8BYTE, REG_V24, REG_P4, REG_V4, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); // FMINNMV , , . - theEmitter->emitIns_R_R_R(INS_sve_fminv, EA_4BYTE, REG_V25, REG_P3, REG_V3, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); // FMINV , , . + theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_2BYTE, REG_V21, REG_P7, REG_V7, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDV , , . + theEmitter->emitIns_R_R_R(INS_sve_fmaxnmv, EA_2BYTE, REG_V22, REG_P6, REG_V6, INS_OPTS_SCALABLE_H, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXNMV , , . + theEmitter->emitIns_R_R_R(INS_sve_fmaxv, EA_4BYTE, REG_V23, REG_P5, REG_V5, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXV , , . + theEmitter->emitIns_R_R_R(INS_sve_fminnmv, EA_8BYTE, REG_V24, REG_P4, REG_V4, INS_OPTS_SCALABLE_D, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINNMV , , . + theEmitter->emitIns_R_R_R(INS_sve_fminv, EA_4BYTE, REG_V25, REG_P3, REG_V3, INS_OPTS_SCALABLE_S, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINV , , . // IF_SVE_HQ_3A theEmitter->emitIns_R_R_R(INS_sve_frinta, EA_SCALABLE, REG_V26, REG_P7, REG_V2, diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index d8c99b9a7ba3e..a6198f5ed041a 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -1012,10 +1012,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) // (predicated) case IF_SVE_CR_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register elemsize = id->idOpSize(); - assert(insOptsScalableWithSimdScalar(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableSimple(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidVectorElemsize(elemsize)); break; @@ -1023,10 +1023,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_HE_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction case IF_SVE_HJ_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableWithSimdFPScalar(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableFloat(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidVectorElemsizeSveFloat(elemsize)); break; @@ -1034,10 +1034,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register case IF_SVE_CS_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to general register elemsize = id->idOpSize(); - assert(insOptsScalableWithScalar(id->idInsOpt())); // xx - assert(isGeneralRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableSimple(id->idInsOpt())); // xx + assert(isGeneralRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidScalarDatasize(elemsize)); break; @@ -1094,10 +1094,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, widening to scalar SIMD. case IF_SVE_AI_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableWideningToSimdScalar(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableWide(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidVectorElemsizeWidening(elemsize)); break; @@ -1158,10 +1158,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable from general scalar (possibly SP) case IF_SVE_CQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy general register to vector (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableWithScalar(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isGeneralRegisterOrZR(id->idReg3())); // mmmmm + assert(insOptsScalableSimple(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isGeneralRegisterOrZR(id->idReg3())); // mmmmm assert(isValidScalarDatasize(elemsize)); break; @@ -1208,9 +1208,9 @@ void emitter::emitInsSanityCheck(instrDesc* id) FALLTHROUGH; case IF_SVE_DM_2A: // ........xx...... .......MMMMddddd -- SVE inc/dec register by predicate count - assert(insOptsScalableWithScalar(id->idInsOpt())); // xx - assert(isGeneralRegister(id->idReg1())); // ddddd - assert(isPredicateRegister(id->idReg2())); // MMMM + assert(insOptsScalableSimple(id->idInsOpt())); // xx + assert(isGeneralRegister(id->idReg1())); // ddddd + assert(isPredicateRegister(id->idReg2())); // MMMM assert(isValidGeneralDatasize(id->idOpSize())); break; @@ -5352,33 +5352,22 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt) switch (arrangement) { case INS_OPTS_SCALABLE_B: - case INS_OPTS_SCALABLE_WIDE_B: - case INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR: case INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR: - case INS_OPTS_SCALABLE_B_WITH_SCALAR: case INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE: return EA_1BYTE; case INS_OPTS_SCALABLE_H: - case INS_OPTS_SCALABLE_WIDE_H: - case INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR: case INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR: - case INS_OPTS_SCALABLE_H_WITH_SCALAR: case INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE: return EA_2BYTE; case INS_OPTS_SCALABLE_S: - case INS_OPTS_SCALABLE_WIDE_S: - case INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR: case INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR: - case INS_OPTS_SCALABLE_S_WITH_SCALAR: case INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE: return EA_4BYTE; case INS_OPTS_SCALABLE_D: - case INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR: case INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR: - case INS_OPTS_SCALABLE_D_WITH_SCALAR: case INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE: return EA_8BYTE; @@ -6270,8 +6259,12 @@ void emitter::emitIns_Mov( * Add an instruction referencing two registers */ -void emitter::emitIns_R_R( - instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insOpts opt /* = INS_OPTS_NONE */) +void emitter::emitIns_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + insOpts opt /* = INS_OPTS_NONE */, + insGroupOpts gopt /* = INS_GROUP_OPTS_NONE */) { if (IsMovInstruction(ins)) { @@ -6922,7 +6915,7 @@ void emitter::emitIns_R_R( if (isGeneralRegister(reg1)) // ddddd { - assert(insOptsScalableWithScalar(opt)); // xx + assert(insOptsScalableSimple(opt)); // xx assert(size == EA_8BYTE); fmt = IF_SVE_DM_2A; } @@ -6943,7 +6936,7 @@ void emitter::emitIns_R_R( if (isGeneralRegister(reg1)) // ddddd { - assert(insOptsScalableWithScalar(opt)); // xx + assert(insOptsScalableSimple(opt)); // xx assert(isValidGeneralDatasize(size)); fmt = IF_SVE_DO_2A; } @@ -7928,8 +7921,13 @@ void emitter::emitIns_R_R_Imm(instruction ins, emitAttr attr, regNumber reg1, re * Add an instruction referencing three registers. */ -void emitter::emitIns_R_R_R( - instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, insOpts opt) /* = INS_OPTS_NONE */ +void emitter::emitIns_R_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + regNumber reg3, + insOpts opt, + /* = INS_OPTS_NONE */ insGroupOpts gopt /* = INS_GROUP_OPTS_NONE */) { emitAttr size = EA_SIZE(attr); emitAttr elemsize = EA_UNKNOWN; @@ -8642,7 +8640,8 @@ void emitter::emitIns_R_R_R( assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdScalar(opt)); + assert(insOptsScalableSimple(opt)); + assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AF_3A; break; @@ -8670,7 +8669,8 @@ void emitter::emitIns_R_R_R( assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdScalar(opt)); + assert(insOptsScalableWide(opt)); + assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AI_3A; break; @@ -8690,7 +8690,8 @@ void emitter::emitIns_R_R_R( assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdScalar(opt)); + assert(insOptsScalableSimple(opt)); + assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AK_3A; break; @@ -8722,12 +8723,15 @@ void emitter::emitIns_R_R_R( assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (insOptsScalableSimple(opt)) + + if (gopt == INS_GROUP_OPTS_NONE) { + assert(insOptsScalableSimple(opt)); fmt = IF_SVE_AN_3A; } else { + assert(gopt == INS_GROUP_OPTS_SCALABLE_WIDE); assert(insOptsScalableWide(opt)); fmt = IF_SVE_AO_3A; } @@ -8800,14 +8804,15 @@ void emitter::emitIns_R_R_R( case INS_sve_clasta: case INS_sve_clastb: + assert(insOptsScalableSimple(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (insOptsScalableSimple(opt)) + if (gopt == INS_GROUP_OPTS_NONE) { assert(isVectorRegister(reg1)); fmt = IF_SVE_CM_3A; } - else if (insOptsScalableWithSimdScalar(opt)) + else if (gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR) { assert(isFloatReg(reg1)); assert(isValidVectorElemsize(size)); @@ -8815,7 +8820,7 @@ void emitter::emitIns_R_R_R( } else { - assert(insOptsScalableWithScalar(opt)); + assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); assert(isGeneralRegister(reg1)); assert(isValidScalarDatasize(size)); fmt = IF_SVE_CO_3A; @@ -8824,16 +8829,17 @@ void emitter::emitIns_R_R_R( case INS_sve_cpy: case INS_sve_mov: + assert(insOptsScalableSimple(opt)); assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); - if (insOptsScalableWithSimdScalar(opt)) + if (gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg3)); fmt = IF_SVE_CP_3A; } else { - assert(insOptsScalableWithScalar(opt)); + assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); assert(isGeneralRegisterOrSP(reg3)); fmt = IF_SVE_CQ_3A; reg3 = encodingSPtoZR(reg3); @@ -8844,16 +8850,17 @@ void emitter::emitIns_R_R_R( case INS_sve_lasta: case INS_sve_lastb: + assert(insOptsScalableSimple(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (insOptsScalableWithSimdScalar(opt)) + if (gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg1)); fmt = IF_SVE_CR_3A; } else { - assert(insOptsScalableWithScalar(opt)); + assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); assert(isGeneralRegister(reg1)); fmt = IF_SVE_CS_3A; } @@ -9012,7 +9019,7 @@ void emitter::emitIns_R_R_R( assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdFPScalar(opt)); + assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); fmt = IF_SVE_HE_3A; break; @@ -9021,7 +9028,7 @@ void emitter::emitIns_R_R_R( assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdFPScalar(opt)); + assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); fmt = IF_SVE_HJ_3A; break; @@ -15662,9 +15669,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "16b"; break; case INS_OPTS_SCALABLE_B: - case INS_OPTS_SCALABLE_WIDE_B: - case INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR: - case INS_OPTS_SCALABLE_B_WITH_SCALAR: case INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE: str = "b"; break; @@ -15676,9 +15680,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "8h"; break; case INS_OPTS_SCALABLE_H: - case INS_OPTS_SCALABLE_WIDE_H: - case INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR: - case INS_OPTS_SCALABLE_H_WITH_SCALAR: case INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE: str = "h"; break; @@ -15690,9 +15691,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "4s"; break; case INS_OPTS_SCALABLE_S: - case INS_OPTS_SCALABLE_WIDE_S: - case INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR: - case INS_OPTS_SCALABLE_S_WITH_SCALAR: case INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE: str = "s"; break; @@ -15704,8 +15702,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "2d"; break; case INS_OPTS_SCALABLE_D: - case INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR: - case INS_OPTS_SCALABLE_D_WITH_SCALAR: case INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE: str = "d"; break; diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index b7a776c6691e4..329b156d6e32e 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -896,8 +896,7 @@ inline static bool insOptsConvertIntToFloat(insOpts opt) inline static bool insOptsScalable(insOpts opt) { // Opt is any of the scalable types. - return ((insOptsScalableSimple(opt)) || (insOptsScalableWide(opt)) || (insOptsScalableWithSimdScalar(opt)) || - (insOptsScalableWithScalar(opt)) || (insOptsScalableWithSimdVector(opt)) || + return ((insOptsScalableSimple(opt)) || (insOptsScalableWithSimdVector(opt)) || insOptsScalableWithPredicateMerge(opt)); } @@ -929,8 +928,7 @@ inline static bool insOptsScalableFloat(insOpts opt) inline static bool insOptsScalableWide(insOpts opt) { // `opt` is any of the scalable types that are valid for widening to size D. - return ((opt == INS_OPTS_SCALABLE_WIDE_B) || (opt == INS_OPTS_SCALABLE_WIDE_H) || - (opt == INS_OPTS_SCALABLE_WIDE_S)); + return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S)); } inline static bool insOptsScalableWithSimdVector(insOpts opt) @@ -940,34 +938,6 @@ inline static bool insOptsScalableWithSimdVector(insOpts opt) (opt == INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR) || (opt == INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR)); } -inline static bool insOptsScalableWithSimdScalar(insOpts opt) -{ - // `opt` is any of the scalable types that are valid for conversion to/from a scalar in a SIMD register. - return ((opt == INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR) || (opt == INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR) || - (opt == INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR) || (opt == INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR)); -} - -inline static bool insOptsScalableWithSimdFPScalar(insOpts opt) -{ - // `opt` is any of the scalable types that are valid for conversion to/from a FP scalar in a SIMD register. - return ((opt == INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR) || (opt == INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR) || - (opt == INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR)); -} - -inline static bool insOptsScalableWideningToSimdScalar(insOpts opt) -{ - // `opt` is any of the scalable types that are valid for widening then conversion to a scalar in a SIMD register. - return ((opt == INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR) || (opt == INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR) || - (opt == INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR)); -} - -inline static bool insOptsScalableWithScalar(insOpts opt) -{ - // `opt` is any of the SIMD scalable types that are valid for conversion to/from a scalar. - return ((opt == INS_OPTS_SCALABLE_B_WITH_SCALAR) || (opt == INS_OPTS_SCALABLE_H_WITH_SCALAR) || - (opt == INS_OPTS_SCALABLE_S_WITH_SCALAR) || (opt == INS_OPTS_SCALABLE_D_WITH_SCALAR)); -} - inline static bool insOptsScalableWithPredicateMerge(insOpts opt) { // `opt` is any of the SIMD scalable types that are valid for use with a merge predicate. @@ -1014,7 +984,12 @@ void emitIns_R_F(instruction ins, emitAttr attr, regNumber reg, double immDbl, i void emitIns_Mov( instruction ins, emitAttr attr, regNumber dstReg, regNumber srcReg, bool canSkip, insOpts opt = INS_OPTS_NONE); -void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insOpts opt = INS_OPTS_NONE); +void emitIns_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + insOpts opt = INS_OPTS_NONE, + insGroupOpts gopt = INS_GROUP_OPTS_NONE); void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insFlags flags) { @@ -1035,8 +1010,13 @@ void emitIns_R_R_I( // Checks for a large immediate that needs a second instruction void emitIns_R_R_Imm(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, ssize_t imm); -void emitIns_R_R_R( - instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, insOpts opt = INS_OPTS_NONE); +void emitIns_R_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + regNumber reg3, + insOpts opt = INS_OPTS_NONE, + insGroupOpts gopt = INS_GROUP_OPTS_NONE); void emitIns_R_R_R_I(instruction ins, emitAttr attr, diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index 717b9c37fcbd8..a0dafdc9661df 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -275,25 +275,11 @@ enum insOpts : unsigned INS_OPTS_SCALABLE_S, INS_OPTS_SCALABLE_D, - INS_OPTS_SCALABLE_WIDE_B, - INS_OPTS_SCALABLE_WIDE_H, - INS_OPTS_SCALABLE_WIDE_S, - INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR, INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR, INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR, INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR, - INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR, - INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR, - INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR, - INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR, - - INS_OPTS_SCALABLE_B_WITH_SCALAR, - INS_OPTS_SCALABLE_H_WITH_SCALAR, - INS_OPTS_SCALABLE_S_WITH_SCALAR, - INS_OPTS_SCALABLE_D_WITH_SCALAR, - INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE, INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE, INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE, @@ -327,6 +313,15 @@ enum insOpts : unsigned #endif }; +enum insGroupOpts : unsigned +{ + INS_GROUP_OPTS_NONE, + + INS_GROUP_OPTS_SCALABLE_WIDE, + INS_GROUP_OPTS_SCALABLE_WITH_SCALAR, + INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR +}; + enum insCond : unsigned { INS_COND_EQ, From edf011aadea60913c20c43ff0ab11dd52905453a Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 09:50:21 +0000 Subject: [PATCH 02/15] Nits --- src/coreclr/jit/emitarm64.cpp | 14 +++++++------- src/coreclr/jit/emitarm64.h | 3 +-- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index a6198f5ed041a..4081247874ca6 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -7921,13 +7921,13 @@ void emitter::emitIns_R_R_Imm(instruction ins, emitAttr attr, regNumber reg1, re * Add an instruction referencing three registers. */ -void emitter::emitIns_R_R_R(instruction ins, - emitAttr attr, - regNumber reg1, - regNumber reg2, - regNumber reg3, - insOpts opt, - /* = INS_OPTS_NONE */ insGroupOpts gopt /* = INS_GROUP_OPTS_NONE */) +void emitter::emitIns_R_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + regNumber reg3, + insOpts opt /* = INS_OPTS_NONE */, + insGroupOpts gopt /* = INS_GROUP_OPTS_NONE */) { emitAttr size = EA_SIZE(attr); emitAttr elemsize = EA_UNKNOWN; diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 329b156d6e32e..a641bb83d4181 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -896,8 +896,7 @@ inline static bool insOptsConvertIntToFloat(insOpts opt) inline static bool insOptsScalable(insOpts opt) { // Opt is any of the scalable types. - return ((insOptsScalableSimple(opt)) || (insOptsScalableWithSimdVector(opt)) || - insOptsScalableWithPredicateMerge(opt)); + return insOptsScalableSimple(opt) || insOptsScalableWithSimdVector(opt) || insOptsScalableWithPredicateMerge(opt); } inline static bool insOptsScalableSimple(insOpts opt) From e69cc8b0eff0172bc6d58fe90cf7bfea7faa4e7b Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 09:57:03 +0000 Subject: [PATCH 03/15] Rename to insScalableOpts --- src/coreclr/jit/codegenarm64test.cpp | 170 +++++++++++++-------------- src/coreclr/jit/emitarm64.cpp | 50 ++++---- src/coreclr/jit/emitarm64.h | 26 ++-- src/coreclr/jit/instr.h | 10 +- 4 files changed, 128 insertions(+), 128 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index a6210af54e762..1532ce2235dd7 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4719,11 +4719,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AO_3A theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V4, REG_P3, REG_V24, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WIDE); // ASR ., /M, ., .D + INS_SCALABLE_OPTS_SCALABLE_WIDE); // ASR ., /M, ., .D theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V19, REG_P7, REG_V3, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WIDE); // LSL ., /M, ., .D + INS_SCALABLE_OPTS_SCALABLE_WIDE); // LSL ., /M, ., .D theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WIDE); // LSR ., /M, ., .D + INS_SCALABLE_OPTS_SCALABLE_WIDE); // LSR ., /M, ., .D // IF_SVE_CM_3A theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_SCALABLE, REG_V31, REG_P7, REG_V31, @@ -4733,22 +4733,22 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_CN_3A theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTA , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTA , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . // IF_SVE_CO_3A // Note: EA_4BYTE used for B and H (destination register is W) theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . // IF_SVE_CX_4A theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_SCALABLE, REG_P15, REG_P0, REG_V0, REG_V10, @@ -4860,11 +4860,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_HJ_3A theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . // IF_SVE_HL_3A theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11, @@ -4902,13 +4902,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AF_3A theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ANDV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ANDV , , . theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // EORV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // EORV , , . theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . // IF_SVE_AG_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4924,11 +4924,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AI_3A theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UADDV
, , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UADDV
, , . // IF_SVE_AJ_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4938,13 +4938,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AK_3A theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMAXV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMAXV , , . theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMINV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMINV , , . theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMAXV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMAXV , , . theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMINV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMINV , , . // IF_SVE_AL_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -5024,45 +5024,45 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_CP_3A theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_1BYTE, REG_V14, REG_P1, REG_V11, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V13, REG_P2, REG_V10, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_2BYTE, REG_V12, REG_P3, REG_V9, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_V11, REG_P4, REG_V8, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, // IF_SVE_CQ_3A // Note: EA_4BYTE used for B and H (source register is W) theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_V10, REG_P5, REG_SP, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V9, REG_P6, REG_R30, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V8, REG_P7, REG_R29, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V7, REG_P0, REG_R28, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, // IF_SVE_CR_3A theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_1BYTE, REG_V6, REG_P1, REG_V27, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_2BYTE, REG_V5, REG_P2, REG_V26, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_V4, REG_P3, REG_V25, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_V3, REG_P4, REG_V24, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . // IF_SVE_CS_3A // Note: EA_4BYTE used for B and H (source register is W) theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R1, REG_P5, REG_V23, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R0, REG_P6, REG_V22, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_R30, REG_P7, REG_V21, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R29, REG_P0, REG_V20, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . // IF_SVE_CU_3A theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19, @@ -5131,22 +5131,22 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_DM_2A theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . // IF_SVE_DN_2A // Note: B is reserved @@ -5160,76 +5160,76 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_DO_2A theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . // IF_SVE_DP_2A // NOTE: B is reserved @@ -5338,15 +5338,15 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_HE_3A theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_2BYTE, REG_V21, REG_P7, REG_V7, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDV , , . theEmitter->emitIns_R_R_R(INS_sve_fmaxnmv, EA_2BYTE, REG_V22, REG_P6, REG_V6, INS_OPTS_SCALABLE_H, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXNMV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXNMV , , . theEmitter->emitIns_R_R_R(INS_sve_fmaxv, EA_4BYTE, REG_V23, REG_P5, REG_V5, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXV , , . theEmitter->emitIns_R_R_R(INS_sve_fminnmv, EA_8BYTE, REG_V24, REG_P4, REG_V4, INS_OPTS_SCALABLE_D, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINNMV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINNMV , , . theEmitter->emitIns_R_R_R(INS_sve_fminv, EA_4BYTE, REG_V25, REG_P3, REG_V3, INS_OPTS_SCALABLE_S, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINV , , . + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINV , , . // IF_SVE_HQ_3A theEmitter->emitIns_R_R_R(INS_sve_frinta, EA_SCALABLE, REG_V26, REG_P7, REG_V2, diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 4081247874ca6..91888d6019fe0 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -6259,12 +6259,12 @@ void emitter::emitIns_Mov( * Add an instruction referencing two registers */ -void emitter::emitIns_R_R(instruction ins, - emitAttr attr, - regNumber reg1, - regNumber reg2, - insOpts opt /* = INS_OPTS_NONE */, - insGroupOpts gopt /* = INS_GROUP_OPTS_NONE */) +void emitter::emitIns_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + insOpts opt /* = INS_OPTS_NONE */, + insScalableOpts gopt /* = INS_SCALABLE_OPTS_NONE */) { if (IsMovInstruction(ins)) { @@ -7921,13 +7921,13 @@ void emitter::emitIns_R_R_Imm(instruction ins, emitAttr attr, regNumber reg1, re * Add an instruction referencing three registers. */ -void emitter::emitIns_R_R_R(instruction ins, - emitAttr attr, - regNumber reg1, - regNumber reg2, - regNumber reg3, - insOpts opt /* = INS_OPTS_NONE */, - insGroupOpts gopt /* = INS_GROUP_OPTS_NONE */) +void emitter::emitIns_R_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + regNumber reg3, + insOpts opt /* = INS_OPTS_NONE */, + insScalableOpts gopt /* = INS_SCALABLE_OPTS_NONE */) { emitAttr size = EA_SIZE(attr); emitAttr elemsize = EA_UNKNOWN; @@ -8641,7 +8641,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableSimple(opt)); - assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AF_3A; break; @@ -8670,7 +8670,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWide(opt)); - assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AI_3A; break; @@ -8691,7 +8691,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableSimple(opt)); - assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AK_3A; break; @@ -8724,14 +8724,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (gopt == INS_GROUP_OPTS_NONE) + if (gopt == INS_SCALABLE_OPTS_NONE) { assert(insOptsScalableSimple(opt)); fmt = IF_SVE_AN_3A; } else { - assert(gopt == INS_GROUP_OPTS_SCALABLE_WIDE); + assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WIDE); assert(insOptsScalableWide(opt)); fmt = IF_SVE_AO_3A; } @@ -8807,12 +8807,12 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalableSimple(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (gopt == INS_GROUP_OPTS_NONE) + if (gopt == INS_SCALABLE_OPTS_NONE) { assert(isVectorRegister(reg1)); fmt = IF_SVE_CM_3A; } - else if (gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR) + else if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) { assert(isFloatReg(reg1)); assert(isValidVectorElemsize(size)); @@ -8820,7 +8820,7 @@ void emitter::emitIns_R_R_R(instruction ins, } else { - assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); assert(isGeneralRegister(reg1)); assert(isValidScalarDatasize(size)); fmt = IF_SVE_CO_3A; @@ -8832,14 +8832,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalableSimple(opt)); assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); - if (gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR) + if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg3)); fmt = IF_SVE_CP_3A; } else { - assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); assert(isGeneralRegisterOrSP(reg3)); fmt = IF_SVE_CQ_3A; reg3 = encodingSPtoZR(reg3); @@ -8853,14 +8853,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalableSimple(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (gopt == INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR) + if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg1)); fmt = IF_SVE_CR_3A; } else { - assert(gopt == INS_GROUP_OPTS_SCALABLE_WITH_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); assert(isGeneralRegister(reg1)); fmt = IF_SVE_CS_3A; } diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index a641bb83d4181..e6a463ba42004 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -983,12 +983,12 @@ void emitIns_R_F(instruction ins, emitAttr attr, regNumber reg, double immDbl, i void emitIns_Mov( instruction ins, emitAttr attr, regNumber dstReg, regNumber srcReg, bool canSkip, insOpts opt = INS_OPTS_NONE); -void emitIns_R_R(instruction ins, - emitAttr attr, - regNumber reg1, - regNumber reg2, - insOpts opt = INS_OPTS_NONE, - insGroupOpts gopt = INS_GROUP_OPTS_NONE); +void emitIns_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + insOpts opt = INS_OPTS_NONE, + insScalableOpts gopt = INS_SCALABLE_OPTS_NONE); void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insFlags flags) { @@ -1009,13 +1009,13 @@ void emitIns_R_R_I( // Checks for a large immediate that needs a second instruction void emitIns_R_R_Imm(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, ssize_t imm); -void emitIns_R_R_R(instruction ins, - emitAttr attr, - regNumber reg1, - regNumber reg2, - regNumber reg3, - insOpts opt = INS_OPTS_NONE, - insGroupOpts gopt = INS_GROUP_OPTS_NONE); +void emitIns_R_R_R(instruction ins, + emitAttr attr, + regNumber reg1, + regNumber reg2, + regNumber reg3, + insOpts opt = INS_OPTS_NONE, + insScalableOpts gopt = INS_SCALABLE_OPTS_NONE); void emitIns_R_R_R_I(instruction ins, emitAttr attr, diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index a0dafdc9661df..4ba66b0cbed74 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -313,13 +313,13 @@ enum insOpts : unsigned #endif }; -enum insGroupOpts : unsigned +enum insScalableOpts : unsigned { - INS_GROUP_OPTS_NONE, + INS_SCALABLE_OPTS_NONE, - INS_GROUP_OPTS_SCALABLE_WIDE, - INS_GROUP_OPTS_SCALABLE_WITH_SCALAR, - INS_GROUP_OPTS_SCALABLE_WITH_SIMD_SCALAR + INS_SCALABLE_OPTS_SCALABLE_WIDE, + INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR, + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR }; enum insCond : unsigned From 380bf10aea1763f00840db78ed69fd31d644f889 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 11:04:05 +0000 Subject: [PATCH 04/15] Remove _WITH_SIMD_VECTOR --- src/coreclr/jit/codegenarm64test.cpp | 30 ++++++------- src/coreclr/jit/emitarm64.cpp | 66 ++++++++++++++++++---------- src/coreclr/jit/emitarm64.h | 12 ++--- src/coreclr/jit/instr.h | 5 --- 4 files changed, 61 insertions(+), 52 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index 1532ce2235dd7..e8dcf80cd71bf 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4912,13 +4912,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AG_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED - theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V4, REG_P4, REG_V4, INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V4, REG_P4, REG_V4, INS_OPTS_SCALABLE_B); // ANDQV ., , . - theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_8BYTE, REG_V5, REG_P5, REG_V5, INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_8BYTE, REG_V5, REG_P5, REG_V5, INS_OPTS_SCALABLE_H); // EORQV ., , . - theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V6, REG_P6, REG_V6, INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V6, REG_P6, REG_V6, INS_OPTS_SCALABLE_S); // ORQV ., , . - theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7, INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7, INS_OPTS_SCALABLE_D); // ORQV ., , . #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4932,7 +4932,7 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AJ_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED - theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_V7, REG_P22, INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_P7, REG_V22, INS_OPTS_SCALABLE_B); // ADDQV ., , . #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4948,13 +4948,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AL_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED - theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_8BYTE, REG_V0, REG_P5, REG_V25, INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_8BYTE, REG_V0, REG_P5, REG_V25, INS_OPTS_SCALABLE_B); // SMAXQV ., , . - theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_8BYTE, REG_V1, REG_P4, REG_V24, INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_8BYTE, REG_V1, REG_P4, REG_V24, INS_OPTS_SCALABLE_H); // SMINQV ., , . - theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_8BYTE, REG_V2, REG_P3, REG_V23, INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_8BYTE, REG_V2, REG_P3, REG_V23, INS_OPTS_SCALABLE_S); // UMAXQV ., , . - theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22, INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR); + theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22, INS_OPTS_SCALABLE_D); // UMINQV ., , . #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -5325,16 +5325,16 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_GS_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED theEmitter->emitIns_R_R_R(INS_sve_faddqv, EA_8BYTE, REG_V16, REG_P0, REG_V12, - INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR); // FADDQV ., , . + INS_OPTS_SCALABLE_H); // FADDQV ., , . theEmitter->emitIns_R_R_R(INS_sve_fmaxnmqv, EA_8BYTE, REG_V17, REG_P1, REG_V11, - INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR); // FMAXNMQV ., , . + INS_OPTS_SCALABLE_S); // FMAXNMQV ., , . theEmitter->emitIns_R_R_R(INS_sve_fmaxqv, EA_8BYTE, REG_V18, REG_P3, REG_V10, - INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR); // FMAXQV ., , . + INS_OPTS_SCALABLE_D); // FMAXQV ., , . theEmitter->emitIns_R_R_R(INS_sve_fminnmqv, EA_8BYTE, REG_V19, REG_P4, REG_V9, - INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR); // FMINNMQV ., , . + INS_OPTS_SCALABLE_H); // FMINNMQV ., , . theEmitter->emitIns_R_R_R(INS_sve_fminqv, EA_8BYTE, REG_V20, REG_P5, REG_V8, - INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR); // FMINQV ., , . -#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED + INS_OPTS_SCALABLE_D); // FMINQV ., , . +#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_HE_3A theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_2BYTE, REG_V21, REG_P7, REG_V7, INS_OPTS_SCALABLE_H, diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 91888d6019fe0..aed7960b05c3c 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -1082,12 +1082,21 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_AG_3A: // ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (quadwords) case IF_SVE_AJ_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (quadwords) case IF_SVE_AL_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (quadwords) + datasize = id->idOpSize(); + assert(insOptsScalableSimple(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm + assert(datasize == EA_8BYTE); + break; + + // Scalable FP to Simd Vector. case IF_SVE_GS_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction (quadwords) datasize = id->idOpSize(); - assert(insOptsScalableWithSimdVector(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableFloat(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(datasize == EA_8BYTE); break; @@ -5352,22 +5361,18 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt) switch (arrangement) { case INS_OPTS_SCALABLE_B: - case INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR: case INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE: return EA_1BYTE; case INS_OPTS_SCALABLE_H: - case INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR: case INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE: return EA_2BYTE; case INS_OPTS_SCALABLE_S: - case INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR: case INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE: return EA_4BYTE; case INS_OPTS_SCALABLE_D: - case INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR: case INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE: return EA_8BYTE; @@ -5417,6 +5422,28 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt) } } +/*static*/ insOpts emitter::optSveToQuadwordElemsizeArrangement(insOpts arrangement) +{ + switch (arrangement) + { + case INS_OPTS_SCALABLE_B: + return INS_OPTS_16B; + + case INS_OPTS_SCALABLE_H: + return INS_OPTS_8H; + + case INS_OPTS_SCALABLE_S: + return INS_OPTS_4S; + + case INS_OPTS_SCALABLE_D: + return INS_OPTS_2D; + + default: + assert(!" invalid 'arrangement' value"); + return INS_OPTS_NONE; + } +} + /*static*/ emitAttr emitter::widenDatasize(emitAttr datasize) { if (datasize == EA_1BYTE) @@ -8648,11 +8675,10 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_andqv: case INS_sve_eorqv: case INS_sve_orqv: - unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdVector(opt)); + assert(insOptsScalableSimple(opt)); fmt = IF_SVE_AG_3A; break; @@ -8675,11 +8701,10 @@ void emitter::emitIns_R_R_R(instruction ins, break; case INS_sve_addqv: - unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdVector(opt)); + assert(insOptsScalableSimple(opt)); fmt = IF_SVE_AJ_3A; break; @@ -8699,11 +8724,10 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_sminqv: case INS_sve_umaxqv: case INS_sve_uminqv: - unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdVector(opt)); + assert(insOptsScalableSimple(opt)); fmt = IF_SVE_AL_3A; break; @@ -9003,11 +9027,10 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_fminnmqv: case INS_sve_fmaxqv: case INS_sve_fminqv: - unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableWithSimdVector(opt)); + assert(insOptsScalableFloat(opt)); fmt = IF_SVE_GS_3A; break; @@ -9055,7 +9078,6 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_famax: case INS_sve_famin: - unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); @@ -15665,7 +15687,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "8b"; break; case INS_OPTS_16B: - case INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR: str = "16b"; break; case INS_OPTS_SCALABLE_B: @@ -15676,7 +15697,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "4h"; break; case INS_OPTS_8H: - case INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR: str = "8h"; break; case INS_OPTS_SCALABLE_H: @@ -15687,7 +15707,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "2s"; break; case INS_OPTS_4S: - case INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR: str = "4s"; break; case INS_OPTS_SCALABLE_S: @@ -15698,7 +15717,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "1d"; break; case INS_OPTS_2D: - case INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR: str = "2d"; break; case INS_OPTS_SCALABLE_D: @@ -17362,9 +17380,9 @@ void emitter::emitDispInsHelp( case IF_SVE_AJ_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (quadwords) case IF_SVE_AL_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (quadwords) case IF_SVE_GS_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction (quadwords) - emitDispVectorReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispVectorReg(id->idReg1(), optSveToQuadwordElemsizeArrangement(id->idInsOpt()), true); // ddddd + emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; //
, , . diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index e6a463ba42004..68f5ea0f0b6a5 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -599,6 +599,9 @@ static insOpts optWidenElemsizeArrangement(insOpts arrangement); // element. static insOpts optWidenSveElemsizeArrangement(insOpts arrangement); +// For the given SVE 'arrangement', return the one when reduced to a quadword vector. +static insOpts optSveToQuadwordElemsizeArrangement(insOpts arrangement); + // For the given 'datasize' returns the one that is double that of the 'datasize'. static emitAttr widenDatasize(emitAttr datasize); @@ -896,7 +899,7 @@ inline static bool insOptsConvertIntToFloat(insOpts opt) inline static bool insOptsScalable(insOpts opt) { // Opt is any of the scalable types. - return insOptsScalableSimple(opt) || insOptsScalableWithSimdVector(opt) || insOptsScalableWithPredicateMerge(opt); + return insOptsScalableSimple(opt) || insOptsScalableWithPredicateMerge(opt); } inline static bool insOptsScalableSimple(insOpts opt) @@ -930,13 +933,6 @@ inline static bool insOptsScalableWide(insOpts opt) return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S)); } -inline static bool insOptsScalableWithSimdVector(insOpts opt) -{ - // `opt` is any of the scalable types that are valid for conversion to an Advsimd SIMD Vector. - return ((opt == INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR) || (opt == INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR) || - (opt == INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR) || (opt == INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR)); -} - inline static bool insOptsScalableWithPredicateMerge(insOpts opt) { // `opt` is any of the SIMD scalable types that are valid for use with a merge predicate. diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index 4ba66b0cbed74..de03bfad0be38 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -275,11 +275,6 @@ enum insOpts : unsigned INS_OPTS_SCALABLE_S, INS_OPTS_SCALABLE_D, - INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR, - INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR, - INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR, - INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR, - INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE, INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE, INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE, From b1f6a51af1ffce51b76780c6eb6f098cbdd557d6 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 12:08:56 +0000 Subject: [PATCH 05/15] Remove _WITH_PREDICATE_MERGE. Reuse _idReg3Scaled. --- src/coreclr/jit/codegenarm64test.cpp | 16 ++++++------- src/coreclr/jit/emit.h | 16 ++++++++++--- src/coreclr/jit/emitarm64.cpp | 35 ++++++++++++++-------------- src/coreclr/jit/emitarm64.h | 9 +------ src/coreclr/jit/instr.h | 8 ++----- 5 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index e8dcf80cd71bf..ef17953344784 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4622,14 +4622,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_S); // MOVPRFX ., /, . theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V15, REG_P3, REG_V2, INS_OPTS_SCALABLE_D); // MOVPRFX ., /, . - theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V16, REG_P4, REG_V3, - INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE); // MOVPRFX ., /, . - theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V17, REG_P5, REG_V12, - INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE); // MOVPRFX ., /, . - theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V0, REG_P6, REG_V13, - INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE); // MOVPRFX ., /, . - theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V31, REG_P7, REG_V22, - INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE); // MOVPRFX ., /, . + theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V16, REG_P4, REG_V3, INS_OPTS_SCALABLE_B, + INS_SCALABLE_OPTS_PREDICATE_MERGE); // MOVPRFX ., /, . + theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V17, REG_P5, REG_V12, INS_OPTS_SCALABLE_H, + INS_SCALABLE_OPTS_PREDICATE_MERGE); // MOVPRFX ., /, . + theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V0, REG_P6, REG_V13, INS_OPTS_SCALABLE_S, + INS_SCALABLE_OPTS_PREDICATE_MERGE); // MOVPRFX ., /, . + theEmitter->emitIns_R_R_R(INS_sve_movprfx, EA_SCALABLE, REG_V31, REG_P7, REG_V22, INS_OPTS_SCALABLE_D, + INS_SCALABLE_OPTS_PREDICATE_MERGE); // MOVPRFX ., /, . // IF_SVE_AM_2A : right shifts theEmitter->emitIns_R_R_I(INS_sve_asr, EA_SCALABLE, REG_V0, REG_P0, 1, diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h index 87c57113a6513..d939daed40310 100644 --- a/src/coreclr/jit/emit.h +++ b/src/coreclr/jit/emit.h @@ -978,7 +978,7 @@ class emitter #ifdef TARGET_ARM64 // For 64-bit architecture this 32-bit structure can pack with these unsigned bit fields emitLclVarAddr iiaLclVar; - unsigned _idReg3Scaled : 1; // Reg3 is scaled by idOpSize bits + unsigned _idRegBit : 1; // Reg3 is scaled by idOpSize bits GCtype _idGCref2 : 2; #endif regNumber _idReg3 : REGNUM_BITS; @@ -1386,12 +1386,22 @@ class emitter bool idReg3Scaled() const { assert(!idIsSmallDsc()); - return (idAddr()->_idReg3Scaled == 1); + return (idAddr()->_idRegBit == 1); } void idReg3Scaled(bool val) { assert(!idIsSmallDsc()); - idAddr()->_idReg3Scaled = val ? 1 : 0; + idAddr()->_idRegBit = val ? 1 : 0; + } + bool idPredicateReg2Merge() const + { + assert(!idIsSmallDsc()); + return (idAddr()->_idRegBit == 1); + } + void idPredicateReg2Merge(bool val) + { + assert(!idIsSmallDsc()); + idAddr()->_idRegBit = val ? 1 : 0; } #endif // TARGET_ARM64 diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index aed7960b05c3c..ca6feb9cbeea4 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -977,7 +977,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, Merge or Zero predicate. case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt()) || insOptsScalableWithPredicateMerge(id->idInsOpt())); + assert(insOptsScalableSimple(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // nnnnn assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isVectorRegister(id->idReg3())); // ddddd @@ -5361,19 +5361,15 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt) switch (arrangement) { case INS_OPTS_SCALABLE_B: - case INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE: return EA_1BYTE; case INS_OPTS_SCALABLE_H: - case INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE: return EA_2BYTE; case INS_OPTS_SCALABLE_S: - case INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE: return EA_4BYTE; case INS_OPTS_SCALABLE_D: - case INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE: return EA_8BYTE; default: @@ -7959,6 +7955,7 @@ void emitter::emitIns_R_R_R(instruction ins, emitAttr size = EA_SIZE(attr); emitAttr elemsize = EA_UNKNOWN; insFormat fmt = IF_NONE; + bool pmerge = false; /* Figure out the encoding format of the instruction */ switch (ins) @@ -8686,7 +8683,11 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt) || insOptsScalableWithPredicateMerge(opt)); + assert(insOptsScalableSimple(opt)); + if (gopt == INS_SCALABLE_OPTS_PREDICATE_MERGE) + { + pmerge = true; + } fmt = IF_SVE_AH_3A; break; @@ -9126,6 +9127,11 @@ void emitter::emitIns_R_R_R(instruction ins, id->idReg2(reg2); id->idReg3(reg3); + if (pmerge) + { + id->idPredicateReg2Merge(pmerge); + } + dispIns(id); appendToCurIG(id); } @@ -14907,11 +14913,11 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) // Scalable with Merge or Zero predicate case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated) code = emitInsCodeSve(ins, fmt); - code |= insEncodeReg_V_4_to_0(id->idReg1()); // nnnnn - code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg - code |= insEncodeReg_V_9_to_5(id->idReg3()); // ddddd - code |= insEncodePredQualifier_16(insOptsScalableWithPredicateMerge(id->idInsOpt())); // M - code |= insEncodeSveElemsize(optGetSveElemsize(id->idInsOpt())); // xx + code |= insEncodeReg_V_4_to_0(id->idReg1()); // nnnnn + code |= insEncodeReg_P_12_to_10(id->idReg2()); // ggg + code |= insEncodeReg_V_9_to_5(id->idReg3()); // ddddd + code |= insEncodePredQualifier_16(id->idPredicateReg2Merge()); // M + code |= insEncodeSveElemsize(optGetSveElemsize(id->idInsOpt())); // xx dst += emitOutput_Instr(dst, code); break; @@ -15690,7 +15696,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "16b"; break; case INS_OPTS_SCALABLE_B: - case INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE: str = "b"; break; case INS_OPTS_4H: @@ -15700,7 +15705,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "8h"; break; case INS_OPTS_SCALABLE_H: - case INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE: str = "h"; break; case INS_OPTS_2S: @@ -15710,7 +15714,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "4s"; break; case INS_OPTS_SCALABLE_S: - case INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE: str = "s"; break; case INS_OPTS_1D: @@ -15720,7 +15723,6 @@ void emitter::emitDispArrangement(insOpts opt) str = "2d"; break; case INS_OPTS_SCALABLE_D: - case INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE: str = "d"; break; @@ -17308,8 +17310,7 @@ void emitter::emitDispInsHelp( // ., /, . case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated) { - PredicateType ptype = - (insOptsScalableWithPredicateMerge(id->idInsOpt())) ? PREDICATE_MERGE : PREDICATE_ZERO; + PredicateType ptype = (id->idPredicateReg2Merge()) ? PREDICATE_MERGE : PREDICATE_ZERO; emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // nnnnn emitDispLowPredicateReg(id->idReg2(), ptype, id->idInsOpt(), true); // ggg emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // ddddd diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 68f5ea0f0b6a5..50e317c8194a2 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -899,7 +899,7 @@ inline static bool insOptsConvertIntToFloat(insOpts opt) inline static bool insOptsScalable(insOpts opt) { // Opt is any of the scalable types. - return insOptsScalableSimple(opt) || insOptsScalableWithPredicateMerge(opt); + return insOptsScalableSimple(opt); } inline static bool insOptsScalableSimple(insOpts opt) @@ -933,13 +933,6 @@ inline static bool insOptsScalableWide(insOpts opt) return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S)); } -inline static bool insOptsScalableWithPredicateMerge(insOpts opt) -{ - // `opt` is any of the SIMD scalable types that are valid for use with a merge predicate. - return ((opt == INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE) || (opt == INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE) || - (opt == INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE) || (opt == INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE)); -} - static bool isValidImmCond(ssize_t imm); static bool isValidImmCondFlags(ssize_t imm); static bool isValidImmCondFlagsImm5(ssize_t imm); diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index de03bfad0be38..9b6da78163678 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -275,11 +275,6 @@ enum insOpts : unsigned INS_OPTS_SCALABLE_S, INS_OPTS_SCALABLE_D, - INS_OPTS_SCALABLE_B_WITH_PREDICATE_MERGE, - INS_OPTS_SCALABLE_H_WITH_PREDICATE_MERGE, - INS_OPTS_SCALABLE_S_WITH_PREDICATE_MERGE, - INS_OPTS_SCALABLE_D_WITH_PREDICATE_MERGE, - INS_OPTS_MSL, // Vector Immediate (shifting ones variant) INS_OPTS_S_TO_4BYTE, // Single to INT32 @@ -314,7 +309,8 @@ enum insScalableOpts : unsigned INS_SCALABLE_OPTS_SCALABLE_WIDE, INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR + INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR, + INS_SCALABLE_OPTS_PREDICATE_MERGE, }; enum insCond : unsigned From c3ea0a3068f7b7682d17b5b903b9471bb583a68e Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 15:06:04 +0000 Subject: [PATCH 06/15] Remove insOptsScalableSimple --- src/coreclr/jit/emitarm64.cpp | 136 +++++++++++++++++----------------- src/coreclr/jit/emitarm64.h | 6 -- 2 files changed, 68 insertions(+), 74 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index ca6feb9cbeea4..99f14d5e495c6 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -956,10 +956,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_EU_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 saturating/rounding bitwise shift left // (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isScalableVectorSize(elemsize)); break; @@ -977,7 +977,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, Merge or Zero predicate. case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); + assert(insOptsScalable(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // nnnnn assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isVectorRegister(id->idReg3())); // ddddd @@ -987,7 +987,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, with shift immediate. case IF_SVE_AM_2A: // ........xx...... ...gggxxiiiddddd -- SVE bitwise shift by immediate (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); + assert(insOptsScalable(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // ddddd assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isValidVectorShiftAmount(emitGetInsSC(id), optGetSveElemsize(id->idInsOpt()), true)); @@ -1012,10 +1012,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) // (predicated) case IF_SVE_CR_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidVectorElemsize(elemsize)); break; @@ -1034,10 +1034,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register case IF_SVE_CS_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to general register elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isGeneralRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isGeneralRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidScalarDatasize(elemsize)); break; @@ -1047,9 +1047,9 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_AS_4A: // ........xx.mmmmm ...gggaaaaaddddd -- SVE integer multiply-add writing multiplicand // (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isVectorRegister(id->idReg3())); assert(isVectorRegister(id->idReg4())); assert(isScalableVectorSize(elemsize)); @@ -1058,11 +1058,11 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, 4 regs, to predicate register. case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isPredicateRegister(id->idReg1())); // DDDD - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm - assert(isVectorRegister(id->idReg4())); // nnnnn + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isPredicateRegister(id->idReg1())); // DDDD + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm + assert(isVectorRegister(id->idReg4())); // nnnnn assert(isScalableVectorSize(elemsize)); break; @@ -1083,10 +1083,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_AJ_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (quadwords) case IF_SVE_AL_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (quadwords) datasize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(datasize == EA_8BYTE); break; @@ -1120,7 +1120,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) break; default: - assert(insOptsScalableSimple(id->idInsOpt())); // xx + assert(insOptsScalable(id->idInsOpt())); // xx break; } elemsize = id->idOpSize(); @@ -1138,7 +1138,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) case INS_sve_abs: case INS_sve_neg: case INS_sve_rbit: - assert(insOptsScalableSimple(id->idInsOpt())); + assert(insOptsScalable(id->idInsOpt())); break; case INS_sve_sxtb: @@ -1167,10 +1167,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable from general scalar (possibly SP) case IF_SVE_CQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy general register to vector (predicated) elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isGeneralRegisterOrZR(id->idReg3())); // mmmmm + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isGeneralRegisterOrZR(id->idReg3())); // mmmmm assert(isValidScalarDatasize(elemsize)); break; @@ -1192,7 +1192,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) { case INS_sve_sqabs: case INS_sve_sqneg: - assert(insOptsScalableSimple(id->idInsOpt())); + assert(insOptsScalable(id->idInsOpt())); break; default: @@ -1217,9 +1217,9 @@ void emitter::emitInsSanityCheck(instrDesc* id) FALLTHROUGH; case IF_SVE_DM_2A: // ........xx...... .......MMMMddddd -- SVE inc/dec register by predicate count - assert(insOptsScalableSimple(id->idInsOpt())); // xx - assert(isGeneralRegister(id->idReg1())); // ddddd - assert(isPredicateRegister(id->idReg2())); // MMMM + assert(insOptsScalable(id->idInsOpt())); // xx + assert(isGeneralRegister(id->idReg1())); // ddddd + assert(isPredicateRegister(id->idReg2())); // MMMM assert(isValidGeneralDatasize(id->idOpSize())); break; @@ -1247,7 +1247,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) break; case IF_SVE_GD_2A: // .........x.xx... ......nnnnnddddd -- SVE2 saturating extract narrow - assert(insOptsScalableSimple(id->idInsOpt())); + assert(insOptsScalable(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // nnnnn assert(isVectorRegister(id->idReg2())); // ddddd assert(optGetSveElemsize(id->idInsOpt()) != EA_8BYTE); @@ -1257,7 +1257,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_GK_2A: // ................ ......mmmmmddddd -- SVE2 crypto destructive binary operations elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); + assert(insOptsScalable(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // ddddd assert(isVectorRegister(id->idReg2())); // mmmmm #ifdef DEBUG @@ -1275,7 +1275,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_GL_1A: // ................ ...........ddddd -- SVE2 crypto unary operations elemsize = id->idOpSize(); - assert(insOptsScalableSimple(id->idInsOpt())); + assert(insOptsScalable(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // ddddd assert(isScalableVectorSize(elemsize)); break; @@ -6938,7 +6938,7 @@ void emitter::emitIns_R_R(instruction ins, if (isGeneralRegister(reg1)) // ddddd { - assert(insOptsScalableSimple(opt)); // xx + assert(insOptsScalable(opt)); // xx assert(size == EA_8BYTE); fmt = IF_SVE_DM_2A; } @@ -6959,7 +6959,7 @@ void emitter::emitIns_R_R(instruction ins, if (isGeneralRegister(reg1)) // ddddd { - assert(insOptsScalableSimple(opt)); // xx + assert(insOptsScalable(opt)); // xx assert(isValidGeneralDatasize(size)); fmt = IF_SVE_DO_2A; } @@ -7723,7 +7723,7 @@ void emitter::emitIns_R_R_I( case INS_sve_uqshl: case INS_sve_asrd: isRightShift = emitInsIsVectorRightShift(ins); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(isVectorRegister(reg1)); // ddddd assert(isLowPredicateRegister(reg2)); // ggg assert(isValidVectorShiftAmount(imm, optGetSveElemsize(opt), isRightShift)); @@ -8610,7 +8610,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AA_3A; break; @@ -8620,7 +8620,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AB_3A; break; @@ -8644,7 +8644,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AD_3A; break; @@ -8654,7 +8654,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AE_3A; break; @@ -8664,7 +8664,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AF_3A; break; @@ -8675,7 +8675,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AG_3A; break; @@ -8683,7 +8683,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); if (gopt == INS_SCALABLE_OPTS_PREDICATE_MERGE) { pmerge = true; @@ -8705,7 +8705,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AJ_3A; break; @@ -8716,7 +8716,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); fmt = IF_SVE_AK_3A; break; @@ -8728,7 +8728,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AL_3A; break; @@ -8738,7 +8738,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AN_3A; break; @@ -8751,7 +8751,7 @@ void emitter::emitIns_R_R_R(instruction ins, if (gopt == INS_SCALABLE_OPTS_NONE) { - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AN_3A; } else @@ -8770,7 +8770,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AP_3A; break; @@ -8788,7 +8788,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_AQ_3A; break; @@ -8829,7 +8829,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_clasta: case INS_sve_clastb: - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); if (gopt == INS_SCALABLE_OPTS_NONE) @@ -8854,7 +8854,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_cpy: case INS_sve_mov: - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) @@ -8875,7 +8875,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_lasta: case INS_sve_lastb: - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) @@ -8895,7 +8895,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_CU_3A; break; @@ -8934,7 +8934,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_EP_3A; break; @@ -8955,7 +8955,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_ER_3A; break; @@ -8964,7 +8964,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_ES_3A; break; @@ -8988,7 +8988,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_ET_3A; break; @@ -9007,7 +9007,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); fmt = IF_SVE_EU_3A; break; @@ -10023,7 +10023,7 @@ void emitter::emitIns_R_R_R_R(instruction ins, case INS_sve_cmplo: case INS_sve_cmpls: case INS_sve_cmplt: - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(isPredicateRegister(reg1)); // DDDD assert(isLowPredicateRegister(reg2)); // ggg assert(isVectorRegister(reg3)); // mmmmm @@ -10034,7 +10034,7 @@ void emitter::emitIns_R_R_R_R(instruction ins, case INS_sve_mla: case INS_sve_mls: - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(isVectorRegister(reg1)); // ddddd assert(isLowPredicateRegister(reg2)); // ggg assert(isVectorRegister(reg3)); // nnnnn @@ -10045,7 +10045,7 @@ void emitter::emitIns_R_R_R_R(instruction ins, case INS_sve_mad: case INS_sve_msb: - assert(insOptsScalableSimple(opt)); + assert(insOptsScalable(opt)); assert(isVectorRegister(reg1)); // ddddd assert(isLowPredicateRegister(reg2)); // ggg assert(isVectorRegister(reg3)); // mmmmm diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 50e317c8194a2..056b013fa4244 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -897,12 +897,6 @@ inline static bool insOptsConvertIntToFloat(insOpts opt) } inline static bool insOptsScalable(insOpts opt) -{ - // Opt is any of the scalable types. - return insOptsScalableSimple(opt); -} - -inline static bool insOptsScalableSimple(insOpts opt) { // `opt` is any of the standard scalable types. return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S) || From 6b7632cef2093edeb6a166696a9f5f4831e37f9e Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 15:27:45 +0000 Subject: [PATCH 07/15] Better insScalableOpts entry names --- src/coreclr/jit/codegenarm64test.cpp | 170 +++++++++++++-------------- src/coreclr/jit/emitarm64.cpp | 20 ++-- src/coreclr/jit/instr.h | 6 +- 3 files changed, 98 insertions(+), 98 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index ef17953344784..6c394b34baa1c 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4719,11 +4719,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AO_3A theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V4, REG_P3, REG_V24, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WIDE); // ASR ., /M, ., .D + INS_SCALABLE_OPTS_WIDE); // ASR ., /M, ., .D theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V19, REG_P7, REG_V3, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WIDE); // LSL ., /M, ., .D + INS_SCALABLE_OPTS_WIDE); // LSL ., /M, ., .D theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WIDE); // LSR ., /M, ., .D + INS_SCALABLE_OPTS_WIDE); // LSR ., /M, ., .D // IF_SVE_CM_3A theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_SCALABLE, REG_V31, REG_P7, REG_V31, @@ -4733,22 +4733,22 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_CN_3A theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTA , , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CLASTA , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CLASTB , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CLASTB , , , . // IF_SVE_CO_3A // Note: EA_4BYTE used for B and H (destination register is W) theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTA , , , . theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTA , , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTA , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTB , , , . theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CLASTB , , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTB , , , . // IF_SVE_CX_4A theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_SCALABLE, REG_P15, REG_P0, REG_V0, REG_V10, @@ -4860,11 +4860,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_HJ_3A theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDA , , , . theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDA , , , . theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDA , , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDA , , , . // IF_SVE_HL_3A theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11, @@ -4902,13 +4902,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AF_3A theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ANDV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // ANDV , , . theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // EORV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // EORV , , . theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // ORV , , . theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // ORV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // ORV , , . // IF_SVE_AG_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4924,11 +4924,11 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AI_3A theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SADDV
, , . theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SADDV
, , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SADDV
, , . theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UADDV
, , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // UADDV
, , . // IF_SVE_AJ_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4938,13 +4938,13 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_AK_3A theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMAXV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SMAXV , , . theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // SMINV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SMINV , , . theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMAXV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // UMAXV , , . theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // UMINV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // UMINV , , . // IF_SVE_AL_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -5024,45 +5024,45 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_CP_3A theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_1BYTE, REG_V14, REG_P1, REG_V11, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V13, REG_P2, REG_V10, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_2BYTE, REG_V12, REG_P3, REG_V9, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // MOV ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_V11, REG_P4, REG_V8, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // MOV ., /M, // IF_SVE_CQ_3A // Note: EA_4BYTE used for B and H (source register is W) theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_V10, REG_P5, REG_SP, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_WITH_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V9, REG_P6, REG_R30, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // CPY ., /M, + INS_SCALABLE_OPTS_WITH_SCALAR); // CPY ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V8, REG_P7, REG_R29, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_WITH_SCALAR); // MOV ., /M, theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V7, REG_P0, REG_R28, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // MOV ., /M, + INS_SCALABLE_OPTS_WITH_SCALAR); // MOV ., /M, // IF_SVE_CR_3A theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_1BYTE, REG_V6, REG_P1, REG_V27, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_2BYTE, REG_V5, REG_P2, REG_V26, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_V4, REG_P3, REG_V25, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTB , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_V3, REG_P4, REG_V24, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // LASTB , , . // IF_SVE_CS_3A // Note: EA_4BYTE used for B and H (source register is W) theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R1, REG_P5, REG_V23, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R0, REG_P6, REG_V22, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTA , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // LASTA , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_R30, REG_P7, REG_V21, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // LASTB , , . theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R29, REG_P0, REG_V20, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // LASTB , , . + INS_SCALABLE_OPTS_WITH_SCALAR); // LASTB , , . // IF_SVE_CU_3A theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19, @@ -5131,22 +5131,22 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_DM_2A theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // DECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // INCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . // IF_SVE_DN_2A // Note: B is reserved @@ -5160,76 +5160,76 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_DO_2A theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , ., + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // SQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQDECP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); // UQINCP , . + INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . // IF_SVE_DP_2A // NOTE: B is reserved @@ -5338,15 +5338,15 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_HE_3A theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_2BYTE, REG_V21, REG_P7, REG_V7, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FADDV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDV , , . theEmitter->emitIns_R_R_R(INS_sve_fmaxnmv, EA_2BYTE, REG_V22, REG_P6, REG_V6, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXNMV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMAXNMV , , . theEmitter->emitIns_R_R_R(INS_sve_fmaxv, EA_4BYTE, REG_V23, REG_P5, REG_V5, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMAXV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMAXV , , . theEmitter->emitIns_R_R_R(INS_sve_fminnmv, EA_8BYTE, REG_V24, REG_P4, REG_V4, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINNMV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMINNMV , , . theEmitter->emitIns_R_R_R(INS_sve_fminv, EA_4BYTE, REG_V25, REG_P3, REG_V3, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); // FMINV , , . + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMINV , , . // IF_SVE_HQ_3A theEmitter->emitIns_R_R_R(INS_sve_frinta, EA_SCALABLE, REG_V26, REG_P7, REG_V2, diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 99f14d5e495c6..1095bd462602d 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -8665,7 +8665,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_AF_3A; break; @@ -8697,7 +8697,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWide(opt)); - assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_AI_3A; break; @@ -8717,7 +8717,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_AK_3A; break; @@ -8756,7 +8756,7 @@ void emitter::emitIns_R_R_R(instruction ins, } else { - assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WIDE); + assert(gopt == INS_SCALABLE_OPTS_WIDE); assert(insOptsScalableWide(opt)); fmt = IF_SVE_AO_3A; } @@ -8837,7 +8837,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); fmt = IF_SVE_CM_3A; } - else if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) + else if (gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { assert(isFloatReg(reg1)); assert(isValidVectorElemsize(size)); @@ -8845,7 +8845,7 @@ void emitter::emitIns_R_R_R(instruction ins, } else { - assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_WITH_SCALAR); assert(isGeneralRegister(reg1)); assert(isValidScalarDatasize(size)); fmt = IF_SVE_CO_3A; @@ -8857,14 +8857,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); - if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) + if (gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg3)); fmt = IF_SVE_CP_3A; } else { - assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_WITH_SCALAR); assert(isGeneralRegisterOrSP(reg3)); fmt = IF_SVE_CQ_3A; reg3 = encodingSPtoZR(reg3); @@ -8878,14 +8878,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR) + if (gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg1)); fmt = IF_SVE_CR_3A; } else { - assert(gopt == INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR); + assert(gopt == INS_SCALABLE_OPTS_WITH_SCALAR); assert(isGeneralRegister(reg1)); fmt = IF_SVE_CS_3A; } diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index 9b6da78163678..f8c34596c23c8 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -307,9 +307,9 @@ enum insScalableOpts : unsigned { INS_SCALABLE_OPTS_NONE, - INS_SCALABLE_OPTS_SCALABLE_WIDE, - INS_SCALABLE_OPTS_SCALABLE_WITH_SCALAR, - INS_SCALABLE_OPTS_SCALABLE_WITH_SIMD_SCALAR, + INS_SCALABLE_OPTS_WIDE, + INS_SCALABLE_OPTS_WITH_SCALAR, + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR, INS_SCALABLE_OPTS_PREDICATE_MERGE, }; From 1cfff0061832c2f1a6820fd8a873947dcc6a1e03 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 15:33:15 +0000 Subject: [PATCH 08/15] Add INS_SCALABLE_OPTS_NONE asserts --- src/coreclr/jit/emitarm64.cpp | 65 +++++++++++++++++++++++++++-------- src/coreclr/jit/emitarm64.h | 4 +-- 2 files changed, 52 insertions(+), 17 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 1095bd462602d..b32a5e101fbeb 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -6287,7 +6287,7 @@ void emitter::emitIns_R_R(instruction ins, regNumber reg1, regNumber reg2, insOpts opt /* = INS_OPTS_NONE */, - insScalableOpts gopt /* = INS_SCALABLE_OPTS_NONE */) + insScalableOpts sopt /* = INS_SCALABLE_OPTS_NONE */) { if (IsMovInstruction(ins)) { @@ -7950,7 +7950,7 @@ void emitter::emitIns_R_R_R(instruction ins, regNumber reg2, regNumber reg3, insOpts opt /* = INS_OPTS_NONE */, - insScalableOpts gopt /* = INS_SCALABLE_OPTS_NONE */) + insScalableOpts sopt /* = INS_SCALABLE_OPTS_NONE */) { emitAttr size = EA_SIZE(attr); emitAttr elemsize = EA_UNKNOWN; @@ -8611,6 +8611,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AA_3A; break; @@ -8621,6 +8622,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AB_3A; break; @@ -8632,6 +8634,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AC_3A; break; @@ -8645,6 +8648,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AD_3A; break; @@ -8655,6 +8659,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AE_3A; break; @@ -8665,7 +8670,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_AF_3A; break; @@ -8676,6 +8681,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AG_3A; break; @@ -8684,7 +8690,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - if (gopt == INS_SCALABLE_OPTS_PREDICATE_MERGE) + if (sopt == INS_SCALABLE_OPTS_PREDICATE_MERGE) { pmerge = true; } @@ -8697,7 +8703,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWide(opt)); - assert(gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_AI_3A; break; @@ -8706,6 +8712,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AJ_3A; break; @@ -8717,7 +8724,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_AK_3A; break; @@ -8729,6 +8736,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AL_3A; break; @@ -8739,6 +8747,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AN_3A; break; @@ -8749,14 +8758,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (gopt == INS_SCALABLE_OPTS_NONE) + if (sopt == INS_SCALABLE_OPTS_NONE) { assert(insOptsScalable(opt)); fmt = IF_SVE_AN_3A; } else { - assert(gopt == INS_SCALABLE_OPTS_WIDE); + assert(sopt == INS_SCALABLE_OPTS_WIDE); assert(insOptsScalableWide(opt)); fmt = IF_SVE_AO_3A; } @@ -8771,6 +8780,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AP_3A; break; @@ -8780,6 +8790,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AP_3A; break; @@ -8789,6 +8800,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AQ_3A; break; @@ -8798,6 +8810,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableAtLeastHalf(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AQ_3A; break; @@ -8807,6 +8820,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AQ_3A; break; @@ -8816,6 +8830,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(opt == INS_OPTS_SCALABLE_D); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AQ_3A; break; @@ -8824,6 +8839,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_CL_3A; break; @@ -8832,12 +8848,12 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (gopt == INS_SCALABLE_OPTS_NONE) + if (sopt == INS_SCALABLE_OPTS_NONE) { assert(isVectorRegister(reg1)); fmt = IF_SVE_CM_3A; } - else if (gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) + else if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { assert(isFloatReg(reg1)); assert(isValidVectorElemsize(size)); @@ -8845,7 +8861,7 @@ void emitter::emitIns_R_R_R(instruction ins, } else { - assert(gopt == INS_SCALABLE_OPTS_WITH_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_WITH_SCALAR); assert(isGeneralRegister(reg1)); assert(isValidScalarDatasize(size)); fmt = IF_SVE_CO_3A; @@ -8857,14 +8873,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); - if (gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) + if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg3)); fmt = IF_SVE_CP_3A; } else { - assert(gopt == INS_SCALABLE_OPTS_WITH_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_WITH_SCALAR); assert(isGeneralRegisterOrSP(reg3)); fmt = IF_SVE_CQ_3A; reg3 = encodingSPtoZR(reg3); @@ -8878,14 +8894,14 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (gopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) + if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { assert(isVectorRegister(reg1)); fmt = IF_SVE_CR_3A; } else { - assert(gopt == INS_SCALABLE_OPTS_WITH_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_WITH_SCALAR); assert(isGeneralRegister(reg1)); fmt = IF_SVE_CS_3A; } @@ -8896,6 +8912,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_CU_3A; break; @@ -8904,6 +8921,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableAtLeastHalf(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_CU_3A; break; @@ -8912,6 +8930,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_CU_3A; break; @@ -8920,6 +8939,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(opt == INS_OPTS_SCALABLE_D); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_CU_3A; break; @@ -8935,6 +8955,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_EP_3A; break; @@ -8944,6 +8965,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableAtLeastHalf(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_EQ_3A; break; @@ -8956,6 +8978,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_ER_3A; break; @@ -8965,6 +8988,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_ES_3A; break; @@ -8974,6 +8998,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(opt == INS_OPTS_SCALABLE_S); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_ES_3A; break; @@ -8989,6 +9014,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_ET_3A; break; @@ -9008,6 +9034,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_EU_3A; break; @@ -9020,6 +9047,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_GR_3A; break; @@ -9032,6 +9060,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_GS_3A; break; @@ -9045,6 +9074,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); + assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_HE_3A; break; @@ -9054,6 +9084,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); + assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); fmt = IF_SVE_HJ_3A; break; @@ -9074,6 +9105,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_HL_3A; break; @@ -9083,6 +9115,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_HL_3A; break; @@ -9097,6 +9130,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_HQ_3A; break; @@ -9106,6 +9140,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_HR_3A; break; diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 056b013fa4244..7329d5b0d9a1a 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -971,7 +971,7 @@ void emitIns_R_R(instruction ins, regNumber reg1, regNumber reg2, insOpts opt = INS_OPTS_NONE, - insScalableOpts gopt = INS_SCALABLE_OPTS_NONE); + insScalableOpts sopt = INS_SCALABLE_OPTS_NONE); void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insFlags flags) { @@ -998,7 +998,7 @@ void emitIns_R_R_R(instruction ins, regNumber reg2, regNumber reg3, insOpts opt = INS_OPTS_NONE, - insScalableOpts gopt = INS_SCALABLE_OPTS_NONE); + insScalableOpts sopt = INS_SCALABLE_OPTS_NONE); void emitIns_R_R_R_I(instruction ins, emitAttr attr, From 478ac67e6f7862934b0185344a243a8047cf6fb6 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 16:54:11 +0000 Subject: [PATCH 09/15] Remove INS_SCALABLE_OPTS_WITH_SCALAR --- src/coreclr/jit/codegenarm64test.cpp | 192 +++++++++++---------------- src/coreclr/jit/emitarm64.cpp | 43 +++--- src/coreclr/jit/instr.h | 1 - 3 files changed, 102 insertions(+), 134 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index 6c394b34baa1c..e0366e5e71557 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4741,14 +4741,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_CO_3A // Note: EA_4BYTE used for B and H (destination register is W) - theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTA , , , . - theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTA , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTB , , , . - theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // CLASTB , , , . + theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0, + INS_OPTS_SCALABLE_B); // CLASTA , , , . + theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3, + INS_OPTS_SCALABLE_H); // CLASTA , , , . + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12, + INS_OPTS_SCALABLE_S); // CLASTB , , , . + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, + INS_OPTS_SCALABLE_D); // CLASTB , , , . // IF_SVE_CX_4A theEmitter->emitIns_R_R_R_R(INS_sve_cmpeq, EA_SCALABLE, REG_P15, REG_P0, REG_V0, REG_V10, @@ -5034,14 +5034,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_CQ_3A // Note: EA_4BYTE used for B and H (source register is W) - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_V10, REG_P5, REG_SP, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V9, REG_P6, REG_R30, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // CPY ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V8, REG_P7, REG_R29, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // MOV ., /M, - theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V7, REG_P0, REG_R28, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // MOV ., /M, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_V10, REG_P5, REG_SP, + INS_OPTS_SCALABLE_D); // CPY ., /M, + theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V9, REG_P6, REG_R30, + INS_OPTS_SCALABLE_H); // CPY ., /M, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V8, REG_P7, REG_R29, + INS_OPTS_SCALABLE_S); // MOV ., /M, + theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V7, REG_P0, REG_R28, + INS_OPTS_SCALABLE_B); // MOV ., /M, // IF_SVE_CR_3A theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_1BYTE, REG_V6, REG_P1, REG_V27, INS_OPTS_SCALABLE_B, @@ -5055,14 +5055,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() // IF_SVE_CS_3A // Note: EA_4BYTE used for B and H (source register is W) - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R1, REG_P5, REG_V23, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R0, REG_P6, REG_V22, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // LASTA , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_R30, REG_P7, REG_V21, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // LASTB , , . - theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R29, REG_P0, REG_V20, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // LASTB , , . + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R1, REG_P5, REG_V23, + INS_OPTS_SCALABLE_B); // LASTA , , . + theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R0, REG_P6, REG_V22, + INS_OPTS_SCALABLE_S); // LASTA , , . + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_R30, REG_P7, REG_V21, + INS_OPTS_SCALABLE_H); // LASTB , , . + theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R29, REG_P0, REG_V20, + INS_OPTS_SCALABLE_D); // LASTB , , . // IF_SVE_CU_3A theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19, @@ -5130,23 +5130,15 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_H); // UQRSHRN .H, {.S-.S }, # // IF_SVE_DM_2A - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . - theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // DECP , . - - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . - theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // INCP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B); // DECP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H); // DECP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S); // DECP , . + theEmitter->emitIns_R_R(INS_sve_decp, EA_8BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D); // DECP , . + + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B); // INCP , . + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H); // INCP , . + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S); // INCP , . + theEmitter->emitIns_R_R(INS_sve_incp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D); // INCP , . // IF_SVE_DN_2A // Note: B is reserved @@ -5159,77 +5151,53 @@ void CodeGen::genArm64EmitterUnitTestsSve() theEmitter->emitIns_R_R(INS_sve_incp, EA_SCALABLE, REG_V5, REG_P5, INS_OPTS_SCALABLE_D); // INCP ., . // IF_SVE_DO_2A - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , ., - - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . - theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQDECP , . - - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , ., - - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . - theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // SQINCP , . - - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQDECP , . - - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . - - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . - theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SCALAR); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R0, REG_P0, + INS_OPTS_SCALABLE_B); // SQDECP , ., + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R1, REG_P1, + INS_OPTS_SCALABLE_H); // SQDECP , ., + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R2, REG_P2, + INS_OPTS_SCALABLE_S); // SQDECP , ., + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_4BYTE, REG_R3, REG_P3, + INS_OPTS_SCALABLE_D); // SQDECP , ., + + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B); // SQDECP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H); // SQDECP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S); // SQDECP , . + theEmitter->emitIns_R_R(INS_sve_sqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D); // SQDECP , . + + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R0, REG_P0, + INS_OPTS_SCALABLE_H); // SQINCP , ., + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R1, REG_P1, + INS_OPTS_SCALABLE_S); // SQINCP , ., + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R2, REG_P2, + INS_OPTS_SCALABLE_B); // SQINCP , ., + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_4BYTE, REG_R3, REG_P3, + INS_OPTS_SCALABLE_D); // SQINCP , ., + + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B); // SQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H); // SQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S); // SQINCP , . + theEmitter->emitIns_R_R(INS_sve_sqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D); // SQINCP , . + + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D); // UQDECP , . + + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S); // UQDECP , . + theEmitter->emitIns_R_R(INS_sve_uqdecp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D); // UQDECP , . + + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R0, REG_P0, INS_OPTS_SCALABLE_B); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R1, REG_P1, INS_OPTS_SCALABLE_H); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R2, REG_P2, INS_OPTS_SCALABLE_S); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_4BYTE, REG_R3, REG_P3, INS_OPTS_SCALABLE_D); // UQINCP , . + + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R4, REG_P4, INS_OPTS_SCALABLE_B); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R5, REG_P5, INS_OPTS_SCALABLE_H); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R6, REG_P6, INS_OPTS_SCALABLE_S); // UQINCP , . + theEmitter->emitIns_R_R(INS_sve_uqincp, EA_8BYTE, REG_R7, REG_P7, INS_OPTS_SCALABLE_D); // UQINCP , . // IF_SVE_DP_2A // NOTE: B is reserved diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index b32a5e101fbeb..93ddf3664fed8 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -8848,10 +8848,11 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (sopt == INS_SCALABLE_OPTS_NONE) + if (isGeneralRegister(reg1)) { - assert(isVectorRegister(reg1)); - fmt = IF_SVE_CM_3A; + assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(isValidScalarDatasize(size)); + fmt = IF_SVE_CO_3A; } else if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) { @@ -8861,10 +8862,9 @@ void emitter::emitIns_R_R_R(instruction ins, } else { - assert(sopt == INS_SCALABLE_OPTS_WITH_SCALAR); - assert(isGeneralRegister(reg1)); - assert(isValidScalarDatasize(size)); - fmt = IF_SVE_CO_3A; + assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(isVectorRegister(reg1)); + fmt = IF_SVE_CM_3A; } break; @@ -8873,18 +8873,19 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); - if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) + if (isGeneralRegisterOrSP(reg3)) { - assert(isVectorRegister(reg3)); - fmt = IF_SVE_CP_3A; + assert(sopt == INS_SCALABLE_OPTS_NONE); + fmt = IF_SVE_CQ_3A; + reg3 = encodingSPtoZR(reg3); } else { - assert(sopt == INS_SCALABLE_OPTS_WITH_SCALAR); - assert(isGeneralRegisterOrSP(reg3)); - fmt = IF_SVE_CQ_3A; - reg3 = encodingSPtoZR(reg3); + assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(isVectorRegister(reg3)); + fmt = IF_SVE_CP_3A; } + // MOV is an alias for CPY, and is always the preferred disassembly. ins = INS_sve_mov; break; @@ -8894,17 +8895,17 @@ void emitter::emitIns_R_R_R(instruction ins, assert(insOptsScalable(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) - { - assert(isVectorRegister(reg1)); - fmt = IF_SVE_CR_3A; - } - else + if (isGeneralRegister(reg1)) { - assert(sopt == INS_SCALABLE_OPTS_WITH_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_NONE); assert(isGeneralRegister(reg1)); fmt = IF_SVE_CS_3A; } + else if (sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR) + { + assert(isVectorRegister(reg1)); + fmt = IF_SVE_CR_3A; + } break; case INS_sve_rbit: diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index f8c34596c23c8..a495d5f32644f 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -308,7 +308,6 @@ enum insScalableOpts : unsigned INS_SCALABLE_OPTS_NONE, INS_SCALABLE_OPTS_WIDE, - INS_SCALABLE_OPTS_WITH_SCALAR, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR, INS_SCALABLE_OPTS_PREDICATE_MERGE, }; From 5d05d6dadba727f757aafdf2a2e8c6d0dbb137d8 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 17:10:45 +0000 Subject: [PATCH 10/15] insScalableOpts descriptions --- src/coreclr/jit/instr.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index a495d5f32644f..f892d47fe1132 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -303,13 +303,15 @@ enum insOpts : unsigned #endif }; +// When a single instruction has different encodings variants, this is used +// to distinguish those that can't be determined soley by register usage. enum insScalableOpts : unsigned { INS_SCALABLE_OPTS_NONE, - INS_SCALABLE_OPTS_WIDE, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR, - INS_SCALABLE_OPTS_PREDICATE_MERGE, + INS_SCALABLE_OPTS_WIDE, // Variants with wide elements (eg asr) + INS_SCALABLE_OPTS_WITH_SIMD_SCALAR, // Variants with a NEON SIMD register (eg clasta) + INS_SCALABLE_OPTS_PREDICATE_MERGE, // Variants with a Pg/M predicate (eg brka) }; enum insCond : unsigned From 13a77830f324930feff9044825cd4ec056b702b4 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 17:17:26 +0000 Subject: [PATCH 11/15] Remove uses of INS_SCALABLE_OPTS_WITH_SIMD_SCALAR for single variants --- src/coreclr/jit/codegenarm64test.cpp | 76 ++++++++++++++-------------- src/coreclr/jit/emitarm64.cpp | 10 ++-- src/coreclr/jit/instr.h | 2 +- 3 files changed, 44 insertions(+), 44 deletions(-) diff --git a/src/coreclr/jit/codegenarm64test.cpp b/src/coreclr/jit/codegenarm64test.cpp index e0366e5e71557..bbe393ca47891 100644 --- a/src/coreclr/jit/codegenarm64test.cpp +++ b/src/coreclr/jit/codegenarm64test.cpp @@ -4859,12 +4859,12 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_H); // FMINP ., /M, ., . // IF_SVE_HJ_3A - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDA , , , . - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDA , , , . - theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDA , , , . + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, + INS_OPTS_SCALABLE_H); // FADDA , , , . + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, + INS_OPTS_SCALABLE_S); // FADDA , , , . + theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, + INS_OPTS_SCALABLE_D); // FADDA , , , . // IF_SVE_HL_3A theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11, @@ -4901,14 +4901,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() INS_OPTS_SCALABLE_D); // FSUBR ., /M, ., . // IF_SVE_AF_3A - theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // ANDV , , . - theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // EORV , , . - theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // ORV , , . - theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // ORV , , . + theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0, + INS_OPTS_SCALABLE_B); // ANDV , , . + theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1, + INS_OPTS_SCALABLE_H); // EORV , , . + theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2, + INS_OPTS_SCALABLE_S); // ORV , , . + theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3, + INS_OPTS_SCALABLE_D); // ORV , , . // IF_SVE_AG_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4923,12 +4923,12 @@ void CodeGen::genArm64EmitterUnitTestsSve() #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_AI_3A - theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SADDV
, , . - theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SADDV
, , . - theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // UADDV
, , . + theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2, + INS_OPTS_SCALABLE_B); // SADDV
, , . + theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3, + INS_OPTS_SCALABLE_H); // SADDV
, , . + theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4, + INS_OPTS_SCALABLE_S); // UADDV
, , . // IF_SVE_AJ_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -4937,14 +4937,14 @@ void CodeGen::genArm64EmitterUnitTestsSve() #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_AK_3A - theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // SMINV , , . - theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // UMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31, INS_OPTS_SCALABLE_B, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // UMINV , , . + theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4, + INS_OPTS_SCALABLE_D); // SMAXV , , . + theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14, + INS_OPTS_SCALABLE_S); // SMINV , , . + theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24, + INS_OPTS_SCALABLE_H); // UMAXV , , . + theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31, + INS_OPTS_SCALABLE_B); // UMINV , , . // IF_SVE_AL_3A #ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED @@ -5305,16 +5305,16 @@ void CodeGen::genArm64EmitterUnitTestsSve() #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED // IF_SVE_HE_3A - theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_2BYTE, REG_V21, REG_P7, REG_V7, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FADDV , , . - theEmitter->emitIns_R_R_R(INS_sve_fmaxnmv, EA_2BYTE, REG_V22, REG_P6, REG_V6, INS_OPTS_SCALABLE_H, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMAXNMV , , . - theEmitter->emitIns_R_R_R(INS_sve_fmaxv, EA_4BYTE, REG_V23, REG_P5, REG_V5, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMAXV , , . - theEmitter->emitIns_R_R_R(INS_sve_fminnmv, EA_8BYTE, REG_V24, REG_P4, REG_V4, INS_OPTS_SCALABLE_D, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMINNMV , , . - theEmitter->emitIns_R_R_R(INS_sve_fminv, EA_4BYTE, REG_V25, REG_P3, REG_V3, INS_OPTS_SCALABLE_S, - INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); // FMINV , , . + theEmitter->emitIns_R_R_R(INS_sve_faddv, EA_2BYTE, REG_V21, REG_P7, REG_V7, + INS_OPTS_SCALABLE_H); // FADDV , , . + theEmitter->emitIns_R_R_R(INS_sve_fmaxnmv, EA_2BYTE, REG_V22, REG_P6, REG_V6, + INS_OPTS_SCALABLE_H); // FMAXNMV , , . + theEmitter->emitIns_R_R_R(INS_sve_fmaxv, EA_4BYTE, REG_V23, REG_P5, REG_V5, + INS_OPTS_SCALABLE_S); // FMAXV , , . + theEmitter->emitIns_R_R_R(INS_sve_fminnmv, EA_8BYTE, REG_V24, REG_P4, REG_V4, + INS_OPTS_SCALABLE_D); // FMINNMV , , . + theEmitter->emitIns_R_R_R(INS_sve_fminv, EA_4BYTE, REG_V25, REG_P3, REG_V3, + INS_OPTS_SCALABLE_S); // FMINV , , . // IF_SVE_HQ_3A theEmitter->emitIns_R_R_R(INS_sve_frinta, EA_SCALABLE, REG_V26, REG_P7, REG_V2, diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 93ddf3664fed8..11fc3029080d8 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -8670,7 +8670,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AF_3A; break; @@ -8703,7 +8703,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWide(opt)); - assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AI_3A; break; @@ -8724,7 +8724,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_AK_3A; break; @@ -9075,7 +9075,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); - assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_HE_3A; break; @@ -9085,7 +9085,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); - assert(sopt == INS_SCALABLE_OPTS_WITH_SIMD_SCALAR); + assert(sopt == INS_SCALABLE_OPTS_NONE); fmt = IF_SVE_HJ_3A; break; diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h index f892d47fe1132..0d03687d83e17 100644 --- a/src/coreclr/jit/instr.h +++ b/src/coreclr/jit/instr.h @@ -307,7 +307,7 @@ enum insOpts : unsigned // to distinguish those that can't be determined soley by register usage. enum insScalableOpts : unsigned { - INS_SCALABLE_OPTS_NONE, + INS_SCALABLE_OPTS_NONE, // No Variants exist INS_SCALABLE_OPTS_WIDE, // Variants with wide elements (eg asr) INS_SCALABLE_OPTS_WITH_SIMD_SCALAR, // Variants with a NEON SIMD register (eg clasta) From 82a3bacea82637164fadc7bcd6ba5e559d338a9f Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 10 Jan 2024 17:23:48 +0000 Subject: [PATCH 12/15] Remove unused sopt from emitIns_R_R --- src/coreclr/jit/emitarm64.cpp | 8 ++------ src/coreclr/jit/emitarm64.h | 7 +------ 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 11fc3029080d8..efbd3b46198f7 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -6282,12 +6282,8 @@ void emitter::emitIns_Mov( * Add an instruction referencing two registers */ -void emitter::emitIns_R_R(instruction ins, - emitAttr attr, - regNumber reg1, - regNumber reg2, - insOpts opt /* = INS_OPTS_NONE */, - insScalableOpts sopt /* = INS_SCALABLE_OPTS_NONE */) +void emitter::emitIns_R_R( + instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insOpts opt /* = INS_OPTS_NONE */) { if (IsMovInstruction(ins)) { diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 7329d5b0d9a1a..da40c055eb9bb 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -966,12 +966,7 @@ void emitIns_R_F(instruction ins, emitAttr attr, regNumber reg, double immDbl, i void emitIns_Mov( instruction ins, emitAttr attr, regNumber dstReg, regNumber srcReg, bool canSkip, insOpts opt = INS_OPTS_NONE); -void emitIns_R_R(instruction ins, - emitAttr attr, - regNumber reg1, - regNumber reg2, - insOpts opt = INS_OPTS_NONE, - insScalableOpts sopt = INS_SCALABLE_OPTS_NONE); +void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insOpts opt = INS_OPTS_NONE); void emitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insFlags flags) { From d751331306ebae41428a55f10246ded25599b450 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 11 Jan 2024 12:04:55 +0000 Subject: [PATCH 13/15] Add insScalableOptsNone --- src/coreclr/jit/emitarm64.cpp | 97 +++++++++++++++++------------------ src/coreclr/jit/emitarm64.h | 5 ++ 2 files changed, 53 insertions(+), 49 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index efbd3b46198f7..675f82e1bb59b 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -8607,7 +8607,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AA_3A; break; @@ -8618,7 +8618,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AB_3A; break; @@ -8630,7 +8630,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AC_3A; break; @@ -8644,7 +8644,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AD_3A; break; @@ -8655,7 +8655,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AE_3A; break; @@ -8666,7 +8666,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AF_3A; break; @@ -8677,7 +8677,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AG_3A; break; @@ -8699,7 +8699,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWide(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AI_3A; break; @@ -8708,7 +8708,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AJ_3A; break; @@ -8720,7 +8720,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AK_3A; break; @@ -8732,7 +8732,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AL_3A; break; @@ -8743,7 +8743,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AN_3A; break; @@ -8753,17 +8753,16 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - - if (sopt == INS_SCALABLE_OPTS_NONE) + if (sopt == INS_SCALABLE_OPTS_WIDE) { - assert(insOptsScalable(opt)); - fmt = IF_SVE_AN_3A; + assert(insOptsScalableWide(opt)); + fmt = IF_SVE_AO_3A; } else { - assert(sopt == INS_SCALABLE_OPTS_WIDE); - assert(insOptsScalableWide(opt)); - fmt = IF_SVE_AO_3A; + assert(insScalableOptsNone(sopt)); + assert(insOptsScalable(opt)); + fmt = IF_SVE_AN_3A; } break; @@ -8776,7 +8775,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AP_3A; break; @@ -8786,7 +8785,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AP_3A; break; @@ -8796,7 +8795,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AQ_3A; break; @@ -8806,7 +8805,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableAtLeastHalf(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AQ_3A; break; @@ -8816,7 +8815,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AQ_3A; break; @@ -8826,7 +8825,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(opt == INS_OPTS_SCALABLE_D); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AQ_3A; break; @@ -8835,7 +8834,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_CL_3A; break; @@ -8846,7 +8845,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); if (isGeneralRegister(reg1)) { - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); assert(isValidScalarDatasize(size)); fmt = IF_SVE_CO_3A; } @@ -8858,7 +8857,7 @@ void emitter::emitIns_R_R_R(instruction ins, } else { - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); assert(isVectorRegister(reg1)); fmt = IF_SVE_CM_3A; } @@ -8871,7 +8870,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); if (isGeneralRegisterOrSP(reg3)) { - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_CQ_3A; reg3 = encodingSPtoZR(reg3); } @@ -8893,7 +8892,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); if (isGeneralRegister(reg1)) { - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); assert(isGeneralRegister(reg1)); fmt = IF_SVE_CS_3A; } @@ -8909,7 +8908,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_CU_3A; break; @@ -8918,7 +8917,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableAtLeastHalf(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_CU_3A; break; @@ -8927,7 +8926,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableWords(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_CU_3A; break; @@ -8936,7 +8935,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(opt == INS_OPTS_SCALABLE_D); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_CU_3A; break; @@ -8952,7 +8951,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_EP_3A; break; @@ -8962,7 +8961,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableAtLeastHalf(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_EQ_3A; break; @@ -8975,7 +8974,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_ER_3A; break; @@ -8985,7 +8984,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_ES_3A; break; @@ -8995,7 +8994,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(opt == INS_OPTS_SCALABLE_S); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_ES_3A; break; @@ -9011,7 +9010,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_ET_3A; break; @@ -9031,7 +9030,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalable(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_EU_3A; break; @@ -9044,7 +9043,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_GR_3A; break; @@ -9057,7 +9056,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_GS_3A; break; @@ -9071,7 +9070,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_HE_3A; break; @@ -9081,7 +9080,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); assert(isValidVectorElemsizeSveFloat(size)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_HJ_3A; break; @@ -9102,7 +9101,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_HL_3A; break; @@ -9112,7 +9111,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_HL_3A; break; @@ -9127,7 +9126,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_HQ_3A; break; @@ -9137,7 +9136,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); assert(insOptsScalableFloat(opt)); - assert(sopt == INS_SCALABLE_OPTS_NONE); + assert(insScalableOptsNone(sopt)); fmt = IF_SVE_HR_3A; break; diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index da40c055eb9bb..b5f165e4d7373 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -927,6 +927,11 @@ inline static bool insOptsScalableWide(insOpts opt) return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S)); } +inline static bool insScalableOptsNone(insScalableOpts sopt) +{ + return sopt == INS_SCALABLE_OPTS_NONE; +} + static bool isValidImmCond(ssize_t imm); static bool isValidImmCondFlags(ssize_t imm); static bool isValidImmCondFlagsImm5(ssize_t imm); From 4ae0b5e794388e8faa81552b60054ebbc8d5e654 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 11 Jan 2024 12:13:18 +0000 Subject: [PATCH 14/15] Restore unreached() for capstone unsupported --- src/coreclr/jit/emitarm64.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 675f82e1bb59b..da572441af93b 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -8673,6 +8673,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_andqv: case INS_sve_eorqv: case INS_sve_orqv: + unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); @@ -8704,6 +8705,7 @@ void emitter::emitIns_R_R_R(instruction ins, break; case INS_sve_addqv: + unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); @@ -8728,6 +8730,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_sminqv: case INS_sve_umaxqv: case INS_sve_uminqv: + unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); @@ -9052,6 +9055,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_fminnmqv: case INS_sve_fmaxqv: case INS_sve_fminqv: + unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); @@ -9107,6 +9111,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_famax: case INS_sve_famin: + unreached(); // TODO-SVE: Not yet supported. assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); From e15373c650c554c9088e25fb73f83e9a3098f5d0 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 11 Jan 2024 13:20:25 +0000 Subject: [PATCH 15/15] Add insOptsScalableStandard --- src/coreclr/jit/emitarm64.cpp | 154 +++++++++++++++++----------------- src/coreclr/jit/emitarm64.h | 9 +- 2 files changed, 85 insertions(+), 78 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 5519a51ff406a..f0e6f1d27da34 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -956,10 +956,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_EU_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 saturating/rounding bitwise shift left // (predicated) elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isScalableVectorSize(elemsize)); break; @@ -977,7 +977,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, Merge or Zero predicate. case IF_SVE_AH_3A: // ........xx.....M ...gggnnnnnddddd -- SVE constructive prefix (predicated) elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); + assert(insOptsScalableStandard(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // nnnnn assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isVectorRegister(id->idReg3())); // ddddd @@ -987,7 +987,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, with shift immediate. case IF_SVE_AM_2A: // ........xx...... ...gggxxiiiddddd -- SVE bitwise shift by immediate (predicated) elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); + assert(insOptsScalableStandard(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // ddddd assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isValidVectorShiftAmount(emitGetInsSC(id), optGetSveElemsize(id->idInsOpt()), true)); @@ -1012,10 +1012,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) // (predicated) case IF_SVE_CR_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidVectorElemsize(elemsize)); break; @@ -1034,10 +1034,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register case IF_SVE_CS_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to general register elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isGeneralRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isGeneralRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidScalarDatasize(elemsize)); break; @@ -1047,9 +1047,9 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_AS_4A: // ........xx.mmmmm ...gggaaaaaddddd -- SVE integer multiply-add writing multiplicand // (predicated) elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isVectorRegister(id->idReg3())); assert(isVectorRegister(id->idReg4())); assert(isScalableVectorSize(elemsize)); @@ -1058,11 +1058,11 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable, 4 regs, to predicate register. case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isPredicateRegister(id->idReg1())); // DDDD - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm - assert(isVectorRegister(id->idReg4())); // nnnnn + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isPredicateRegister(id->idReg1())); // DDDD + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm + assert(isVectorRegister(id->idReg4())); // nnnnn assert(isScalableVectorSize(elemsize)); break; @@ -1083,10 +1083,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_AJ_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (quadwords) case IF_SVE_AL_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (quadwords) datasize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isVectorRegister(id->idReg3())); // mmmmm + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(datasize == EA_8BYTE); break; @@ -1120,7 +1120,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) break; default: - assert(insOptsScalable(id->idInsOpt())); // xx + assert(insOptsScalableStandard(id->idInsOpt())); // xx break; } elemsize = id->idOpSize(); @@ -1138,7 +1138,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) case INS_sve_abs: case INS_sve_neg: case INS_sve_rbit: - assert(insOptsScalable(id->idInsOpt())); + assert(insOptsScalableStandard(id->idInsOpt())); break; case INS_sve_sxtb: @@ -1167,10 +1167,10 @@ void emitter::emitInsSanityCheck(instrDesc* id) // Scalable from general scalar (possibly SP) case IF_SVE_CQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy general register to vector (predicated) elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isVectorRegister(id->idReg1())); // ddddd - assert(isLowPredicateRegister(id->idReg2())); // ggg - assert(isGeneralRegisterOrZR(id->idReg3())); // mmmmm + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isGeneralRegisterOrZR(id->idReg3())); // mmmmm assert(isValidScalarDatasize(elemsize)); break; @@ -1192,7 +1192,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) { case INS_sve_sqabs: case INS_sve_sqneg: - assert(insOptsScalable(id->idInsOpt())); + assert(insOptsScalableStandard(id->idInsOpt())); break; default: @@ -1217,9 +1217,9 @@ void emitter::emitInsSanityCheck(instrDesc* id) FALLTHROUGH; case IF_SVE_DM_2A: // ........xx...... .......MMMMddddd -- SVE inc/dec register by predicate count - assert(insOptsScalable(id->idInsOpt())); // xx - assert(isGeneralRegister(id->idReg1())); // ddddd - assert(isPredicateRegister(id->idReg2())); // MMMM + assert(insOptsScalableStandard(id->idInsOpt())); // xx + assert(isGeneralRegister(id->idReg1())); // ddddd + assert(isPredicateRegister(id->idReg2())); // MMMM assert(isValidGeneralDatasize(id->idOpSize())); break; @@ -1247,7 +1247,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) break; case IF_SVE_GD_2A: // .........x.xx... ......nnnnnddddd -- SVE2 saturating extract narrow - assert(insOptsScalable(id->idInsOpt())); + assert(insOptsScalableStandard(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // nnnnn assert(isVectorRegister(id->idReg2())); // ddddd assert(optGetSveElemsize(id->idInsOpt()) != EA_8BYTE); @@ -1257,7 +1257,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_GK_2A: // ................ ......mmmmmddddd -- SVE2 crypto destructive binary operations elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); + assert(insOptsScalableStandard(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // ddddd assert(isVectorRegister(id->idReg2())); // mmmmm #ifdef DEBUG @@ -1275,7 +1275,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) case IF_SVE_GL_1A: // ................ ...........ddddd -- SVE2 crypto unary operations elemsize = id->idOpSize(); - assert(insOptsScalable(id->idInsOpt())); + assert(insOptsScalableStandard(id->idInsOpt())); assert(isVectorRegister(id->idReg1())); // ddddd assert(isScalableVectorSize(elemsize)); break; @@ -7039,7 +7039,7 @@ void emitter::emitIns_R_R( if (isGeneralRegister(reg1)) // ddddd { - assert(insOptsScalable(opt)); // xx + assert(insOptsScalableStandard(opt)); // xx assert(size == EA_8BYTE); fmt = IF_SVE_DM_2A; } @@ -7060,7 +7060,7 @@ void emitter::emitIns_R_R( if (isGeneralRegister(reg1)) // ddddd { - assert(insOptsScalable(opt)); // xx + assert(insOptsScalableStandard(opt)); // xx assert(isValidGeneralDatasize(size)); fmt = IF_SVE_DO_2A; } @@ -7088,7 +7088,7 @@ void emitter::emitIns_R_R( case INS_sve_uqxtnt: case INS_sve_sqxtunb: case INS_sve_sqxtunt: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isVectorRegister(reg2)); assert(optGetSveElemsize(opt) != EA_8BYTE); @@ -7100,7 +7100,7 @@ void emitter::emitIns_R_R( case INS_sve_aese: case INS_sve_aesd: case INS_sve_sm4e: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isVectorRegister(reg2)); #ifdef DEBUG @@ -7824,7 +7824,7 @@ void emitter::emitIns_R_R_I( case INS_sve_uqshl: case INS_sve_asrd: isRightShift = emitInsIsVectorRightShift(ins); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); // ddddd assert(isLowPredicateRegister(reg2)); // ggg assert(isValidVectorShiftAmount(imm, optGetSveElemsize(opt), isRightShift)); @@ -8711,7 +8711,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AA_3A; break; @@ -8722,7 +8722,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AB_3A; break; @@ -8748,7 +8748,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AD_3A; break; @@ -8759,7 +8759,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AE_3A; break; @@ -8770,7 +8770,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AF_3A; break; @@ -8782,7 +8782,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AG_3A; break; @@ -8791,7 +8791,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); if (sopt == INS_SCALABLE_OPTS_PREDICATE_MERGE) { pmerge = true; @@ -8814,7 +8814,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AJ_3A; break; @@ -8826,7 +8826,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isFloatReg(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AK_3A; break; @@ -8839,7 +8839,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AL_3A; break; @@ -8850,7 +8850,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AN_3A; break; @@ -8869,7 +8869,7 @@ void emitter::emitIns_R_R_R(instruction ins, else { assert(insScalableOptsNone(sopt)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); fmt = IF_SVE_AN_3A; } break; @@ -8882,7 +8882,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AP_3A; break; @@ -8902,7 +8902,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_AQ_3A; break; @@ -8948,7 +8948,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_clasta: case INS_sve_clastb: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); if (isGeneralRegister(reg1)) @@ -8973,7 +8973,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_cpy: case INS_sve_mov: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); if (isGeneralRegisterOrSP(reg3)) @@ -8995,7 +8995,7 @@ void emitter::emitIns_R_R_R(instruction ins, case INS_sve_lasta: case INS_sve_lastb: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); if (isGeneralRegister(reg1)) @@ -9015,7 +9015,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_CU_3A; break; @@ -9058,7 +9058,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_EP_3A; break; @@ -9081,7 +9081,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_ER_3A; break; @@ -9091,7 +9091,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_ES_3A; break; @@ -9117,7 +9117,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_ET_3A; break; @@ -9137,7 +9137,7 @@ void emitter::emitIns_R_R_R(instruction ins, assert(isVectorRegister(reg1)); assert(isLowPredicateRegister(reg2)); assert(isVectorRegister(reg3)); - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(insScalableOptsNone(sopt)); fmt = IF_SVE_EU_3A; break; @@ -9752,7 +9752,7 @@ void emitter::emitIns_R_R_R_I(instruction ins, break; case INS_sve_ld1b: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isPredicateRegister(reg2)); assert(isGeneralRegister(reg3)); @@ -9809,7 +9809,7 @@ void emitter::emitIns_R_R_R_I(instruction ins, break; case INS_sve_ldnf1b: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isPredicateRegister(reg2)); assert(isGeneralRegister(reg3)); @@ -9821,7 +9821,7 @@ void emitter::emitIns_R_R_R_I(instruction ins, case INS_sve_ldnt1h: case INS_sve_ldnt1w: case INS_sve_ldnt1d: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isPredicateRegister(reg2)); assert(isGeneralRegister(reg3)); @@ -9863,7 +9863,7 @@ void emitter::emitIns_R_R_R_I(instruction ins, case INS_sve_ld1row: case INS_sve_ld1rqd: case INS_sve_ld1rod: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isPredicateRegister(reg2)); assert(isGeneralRegister(reg3)); @@ -9965,7 +9965,7 @@ void emitter::emitIns_R_R_R_I(instruction ins, case INS_sve_ld2d: case INS_sve_ld3d: case INS_sve_ld4d: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isPredicateRegister(reg2)); assert(isGeneralRegister(reg3)); @@ -10070,7 +10070,7 @@ void emitter::emitIns_R_R_R_I(instruction ins, case INS_sve_stnt1h: case INS_sve_stnt1w: case INS_sve_stnt1d: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isPredicateRegister(reg2)); assert(isGeneralRegister(reg3)); @@ -10143,7 +10143,7 @@ void emitter::emitIns_R_R_R_I(instruction ins, case INS_sve_st2d: case INS_sve_st3d: case INS_sve_st4d: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); assert(isPredicateRegister(reg2)); assert(isGeneralRegister(reg3)); @@ -10669,7 +10669,7 @@ void emitter::emitIns_R_R_R_R(instruction ins, case INS_sve_cmplo: case INS_sve_cmpls: case INS_sve_cmplt: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isPredicateRegister(reg1)); // DDDD assert(isLowPredicateRegister(reg2)); // ggg assert(isVectorRegister(reg3)); // mmmmm @@ -10680,7 +10680,7 @@ void emitter::emitIns_R_R_R_R(instruction ins, case INS_sve_mla: case INS_sve_mls: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); // ddddd assert(isLowPredicateRegister(reg2)); // ggg assert(isVectorRegister(reg3)); // nnnnn @@ -10691,7 +10691,7 @@ void emitter::emitIns_R_R_R_R(instruction ins, case INS_sve_mad: case INS_sve_msb: - assert(insOptsScalable(opt)); + assert(insOptsScalableStandard(opt)); assert(isVectorRegister(reg1)); // ddddd assert(isLowPredicateRegister(reg2)); // ggg assert(isVectorRegister(reg3)); // mmmmm diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index c42b2db8d542c..12650ee664c07 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -967,7 +967,14 @@ inline static bool insOptsScalable(insOpts opt) { // `opt` is any of the scalable types. return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S) || - (opt == INS_OPTS_SCALABLE_D) || (opt == INS_OPTS_SCALABLE_Q)); + (opt == INS_OPTS_SCALABLE_D) || (opt == INS_OPTS_SCALABLE_Q)); +} + +inline static bool insOptsScalableStandard(insOpts opt) +{ + // `opt` is any of the scalable types, except Quadword. + return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S) || + (opt == INS_OPTS_SCALABLE_D)); } inline static bool insOptsScalableWords(insOpts opt)