Add Arm64 encodings for IF_SVE_AT_3A to IF_SVE_BK_3A

[a74nh]

None of these instructions use a predicate to mask the result.

Some of these are unpredicated versions of existing instructions. For these we need new sopt values. Once we can distinguish between V0 and P0 then these sopt entries can be removed.

corecltr output (identical to capstone)

add z0.b, z0.b, z0.b
sqadd z3.h, z31.h, z12.h
sqsub z7.s, z0.s, z31.s
sub z19.d, z7.d, z13.d
uqadd z23.b, z28.b, z29.b
uqsub z31.h, z31.h, z31.h
index z24.b, wzr, w9
index z12.d, x15, x0
mul z5.b, z0.b, z31.b
smulh z0.h, z31.h, z5.h
umulh z31.d, z5.d, z0.d
sqdmulh z7.b, z28.b, z0.b
sqrdmulh z23.h, z3.h, z31.h
asr z9.b, z31.b, z2.d
lsl z19.h, z0.h, z12.d
lsr z29.s, z10.s, z22.d
ftssel z17.d, z16.d, z15.d

Contributes towards #94549.

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Issue Details

---

None of these instructions use a predicate to mask the result.

Some of these are unpredicated versions of existing instructions. For these we need new sopt values. Once we can distinguish between V0 and P0 then these sopt entries can be removed.

corecltr output (identical to capstone)

add z0.b, z0.b, z0.b
sqadd z3.h, z31.h, z12.h
sqsub z7.s, z0.s, z31.s
sub z19.d, z7.d, z13.d
uqadd z23.b, z28.b, z29.b
uqsub z31.h, z31.h, z31.h
index z24.b, wzr, w9
index z12.d, x15, x0
mul z5.b, z0.b, z31.b
smulh z0.h, z31.h, z5.h
umulh z31.d, z5.d, z0.d
sqdmulh z7.b, z28.b, z0.b
sqrdmulh z23.h, z3.h, z31.h
asr z9.b, z31.b, z2.d
lsl z19.h, z0.h, z12.d
lsr z29.s, z10.s, z22.d
ftssel z17.d, z16.d, z15.d

Author:	a74nh
Assignees:	-
Labels:	area-CodeGen-coreclr, community-contribution
Milestone:	-

[a74nh]

@kunalspathak

[kunalspathak]

@dotnet/arm64-contrib

[a74nh]

Build error looks unrelated.