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Describe the bug A valid instruction coding is incorrectly flagged as an error.
Example:
Error at VLM instruction: vector register operand absolute value must be between 0 and 15 HLASM Plugin(M124)
To Reproduce Steps to reproduce the behavior:
VSTM 16,31,SAVE VLM 16,31,SAVE
Expected behavior The example code should produce no errors for the leftmost two operands (V1, V3).
Screenshots
Platform
Additional context The 5th bit necessary to encode values 0-31 is located in the RXB portion of vector instructions:
RXB
The text was updated successfully, but these errors were encountered:
there is 32 vector registers in the cpu (fixes eclipse-che4z#143)
24ed37c
🎉 This issue has been resolved in version 0.14.0-beta.1 🎉
The release is available on GitHub release
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c1a6896
🎉 This issue has been resolved in version 0.14.0 🎉
slavek-kucera
Successfully merging a pull request may close this issue.
Describe the bug
A valid instruction coding is incorrectly flagged as an error.
Example:
To Reproduce
Steps to reproduce the behavior:
Expected behavior
The example code should produce no errors for the leftmost two operands (V1, V3).
Screenshots
Platform
Additional context
The 5th bit necessary to encode values 0-31 is located in the
RXB
portion of vector instructions:The text was updated successfully, but these errors were encountered: