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Vector instructions flagged when VR16-31 are used #143

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Jakub-CZ opened this issue Jul 12, 2021 · 2 comments · Fixed by #149
Closed

Vector instructions flagged when VR16-31 are used #143

Jakub-CZ opened this issue Jul 12, 2021 · 2 comments · Fixed by #149
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@Jakub-CZ
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Describe the bug
A valid instruction coding is incorrectly flagged as an error.

Example:

Error at VLM instruction: vector register operand absolute value must be between 0 and 15
HLASM Plugin(M124)

To Reproduce
Steps to reproduce the behavior:

         VSTM  16,31,SAVE
         VLM   16,31,SAVE

Expected behavior
The example code should produce no errors for the leftmost two operands (V1, V3).

Screenshots
image

Platform

  • Editor: VS Code 1.58.0
  • OS: Windows 10
  • Plugin version: 0.13.0

Additional context
The 5th bit necessary to encode values 0-31 is located in the RXB portion of vector instructions:
image

@slavek-kucera slavek-kucera added the bug Something isn't working label Jul 12, 2021
@slavek-kucera slavek-kucera self-assigned this Jul 15, 2021
slavek-kucera added a commit to slavek-kucera/che-che4z-lsp-for-hlasm that referenced this issue Jul 15, 2021
@slavek-kucera slavek-kucera linked a pull request Jul 16, 2021 that will close this issue
@github-actions
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🎉 This issue has been resolved in version 0.14.0-beta.1 🎉

The release is available on GitHub release

Your semantic-release bot 📦🚀

@github-actions
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🎉 This issue has been resolved in version 0.14.0 🎉

The release is available on GitHub release

Your semantic-release bot 📦🚀

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