From 3d6510737b947145fef8a5f0dad13a1dac2f0105 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Fri, 25 Aug 2023 00:06:19 +0200 Subject: [PATCH] Added more test cases. --- tests/unit/Design.py | 45 ++++++++++++++++++++++++++++++++++++++++- tests/unit/File.py | 47 +++++++++++++++++++++++++++++++++++++++++-- tests/unit/FileSet.py | 4 +++- tests/unit/Project.py | 45 ++++++++++++++++++++++++++++++++++++++++- 4 files changed, 136 insertions(+), 5 deletions(-) diff --git a/tests/unit/Design.py b/tests/unit/Design.py index 6c78a2b9..358dd6d4 100644 --- a/tests/unit/Design.py +++ b/tests/unit/Design.py @@ -35,7 +35,7 @@ from pySVModel import SystemVerilogVersion from pyVHDLModel import VHDLVersion -from pyEDAA.ProjectModel import Design, File, Project +from pyEDAA.ProjectModel import Design, File, Project, Attribute if __name__ == "__main__": # pragma: no cover @@ -145,3 +145,46 @@ def test_Design(self): design = Design("design", directory=Path("designA"), project=project) design.Validate() + + +class Attr(Attribute): + pass + + +class Attributes(TestCase): + def test_AddAttribute_WrongType(self): + design = Design("design") + + with self.assertRaises(TypeError): + design["attr"] = 5 + + def test_AddAttribute_Normal(self): + design = Design("design") + + design[Attr] = 5 + + def test_GetAttribute_WrongType(self): + design = Design("design") + design[Attr] = 5 + + with self.assertRaises(TypeError): + _ = design["attr"] + + def test_GetAttribute_Normal(self): + design = Design("design") + design[Attr] = 5 + + _ = design[Attr] + + def test_DelAttribute_WrongType(self): + design = Design("design") + design[Attr] = 5 + + with self.assertRaises(TypeError): + del design["attr"] + + def test_DelAttribute_Normal(self): + design = Design("design") + design[Attr] = 5 + + del design[Attr] diff --git a/tests/unit/File.py b/tests/unit/File.py index f0513a15..58c1b24d 100644 --- a/tests/unit/File.py +++ b/tests/unit/File.py @@ -32,7 +32,7 @@ from pathlib import Path from unittest import TestCase -from pyEDAA.ProjectModel import Design, FileSet, File, Project, FileTypes +from pyEDAA.ProjectModel import Design, FileSet, File, Project, FileTypes, Attribute from pyEDAA.ProjectModel.Attributes import KeyValueAttribute @@ -155,14 +155,57 @@ def test_File(self): file.Validate() +class Attr(Attribute): + pass + + class Attributes(TestCase): + def test_AddAttribute_WrongType(self): + file = File(Path("file.txt")) + + with self.assertRaises(TypeError): + file["attr"] = 5 + + def test_AddAttribute_Normal(self): + file = File(Path("file.txt")) + + file[Attr] = 5 + + def test_GetAttribute_WrongType(self): + file = File(Path("file.txt")) + file[Attr] = 5 + + with self.assertRaises(TypeError): + _ = file["attr"] + + def test_GetAttribute_Normal(self): + file = File(Path("file.txt")) + file[Attr] = 5 + + _ = file[Attr] + + def test_DelAttribute_WrongType(self): + file = File(Path("file.txt")) + file[Attr] = 5 + + with self.assertRaises(TypeError): + del file["attr"] + + def test_DelAttribute_Normal(self): + file = File(Path("file.txt")) + file[Attr] = 5 + + del file[Attr] + + +class AttributeResolution(TestCase): def test_AttachedToFile(self): project = Project("project", rootDirectory=Path("project")) design = Design("design", directory=Path("designA"), project=project) fileSet = FileSet("fileset", design=design) file = File(Path("file_A1.vhdl"), fileSet=fileSet) - file._attributes[KeyValueAttribute] = KeyValueAttribute() + file[KeyValueAttribute] = KeyValueAttribute() attribute = file[KeyValueAttribute] attribute["id1"] = "5" diff --git a/tests/unit/FileSet.py b/tests/unit/FileSet.py index 5c434e96..416c1080 100644 --- a/tests/unit/FileSet.py +++ b/tests/unit/FileSet.py @@ -35,7 +35,9 @@ from pySVModel import SystemVerilogVersion from pyVHDLModel import VHDLVersion -from pyEDAA.ProjectModel import Design, FileSet, File, FileTypes, TextFile, Project, VHDLLibrary, Attribute +from pyEDAA.ProjectModel import Design, FileSet, File, FileTypes, TextFile, Project, VHDLLibrary, Attribute +from pyEDAA.ProjectModel.Attributes import KeyValueAttribute + if __name__ == "__main__": # pragma: no cover print("ERROR: you called a testcase declaration file as an executable module.") diff --git a/tests/unit/Project.py b/tests/unit/Project.py index d231d5e1..3e3d6c28 100644 --- a/tests/unit/Project.py +++ b/tests/unit/Project.py @@ -35,7 +35,7 @@ from pySVModel import SystemVerilogVersion from pyVHDLModel import VHDLVersion -from pyEDAA.ProjectModel import Project +from pyEDAA.ProjectModel import Project, Attribute if __name__ == "__main__": # pragma: no cover @@ -113,3 +113,46 @@ def test_Project(self): project = Project("project", rootDirectory=Path("project")) project.Validate() + + +class Attr(Attribute): + pass + + +class Attributes(TestCase): + def test_AddAttribute_WrongType(self): + project = Project("project") + + with self.assertRaises(TypeError): + project["attr"] = 5 + + def test_AddAttribute_Normal(self): + project = Project("project") + + project[Attr] = 5 + + def test_GetAttribute_WrongType(self): + project = Project("project") + project[Attr] = 5 + + with self.assertRaises(TypeError): + _ = project["attr"] + + def test_GetAttribute_Normal(self): + project = Project("project") + project[Attr] = 5 + + _ = project[Attr] + + def test_DelAttribute_WrongType(self): + project = Project("project") + project[Attr] = 5 + + with self.assertRaises(TypeError): + del project["attr"] + + def test_DelAttribute_Normal(self): + project = Project("project") + project[Attr] = 5 + + del project[Attr]