diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 44a29a02e..6213b6c26 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -63,4 +63,4 @@
 `define OENB_INIT 1'b0
 `define DM_INIT 3'b001
 
-`endif // __GLOBAL_DEFINE_H
\ No newline at end of file
+`endif // __GLOBAL_DEFINE_H
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index dcdc9f837..b4dfd801e 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -36,7 +36,7 @@
  */
 
 module user_proj_example #(
-    parameter BITS = 16
+    parameter BITS = 32
 )(
 `ifdef USE_POWER_PINS
     inout vccd1,	// User area 1 1.8V supply
@@ -61,9 +61,9 @@ module user_proj_example #(
     input  [127:0] la_oenb,
 
     // IOs
-    input  [BITS-1:0] io_in,
-    output [BITS-1:0] io_out,
-    output [BITS-1:0] io_oeb,
+    input  wire [15:0] io_in,
+    output wire [15:0] io_out,
+    output wire [15:0] io_oeb,
 
     // IRQ
     output [2:0] irq
@@ -82,12 +82,12 @@ module user_proj_example #(
     // WB MI A
     assign valid = wbs_cyc_i && wbs_stb_i; 
     assign wstrb = wbs_sel_i & {4{wbs_we_i}};
-    assign wbs_dat_o = {{(32-BITS){1'b0}}, rdata};
-    assign wdata = wbs_dat_i[BITS-1:0];
+    assign wbs_dat_o = rdata;
+    assign wdata = wbs_dat_i[31:0];
 
     // IO
-    assign io_out = count;
-    assign io_oeb = {(BITS){rst}};
+    assign io_out = count[15:0];
+    assign io_oeb = {(16){rst}};
 
     // IRQ
     assign irq = 3'b000;	// Unused
@@ -95,7 +95,7 @@ module user_proj_example #(
     // LA
     assign la_data_out = {{(128-BITS){1'b0}}, count};
     // Assuming LA probes [63:32] are for controlling the count register  
-    assign la_write = ~la_oenb[63:64-BITS] & ~{BITS{valid}};
+    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
     // Assuming LA probes [65:64] are for controlling the count clk & reset  
     assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
     assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
@@ -108,17 +108,17 @@ module user_proj_example #(
         .ready(wbs_ack_o),
         .valid(valid),
         .rdata(rdata),
-        .wdata(wbs_dat_i[BITS-1:0]),
+        .wdata(wbs_dat_i),
         .wstrb(wstrb),
         .la_write(la_write),
-        .la_input(la_data_in[63:64-BITS]),
+        .la_input(la_data_in[63:32]),
         .count(count)
     );
 
 endmodule
 
 module counter #(
-    parameter BITS = 16
+    parameter BITS = 32
 )(
     input clk,
     input reset,
@@ -146,6 +146,8 @@ module counter #(
                 rdata <= count;
                 if (wstrb[0]) count[7:0]   <= wdata[7:0];
                 if (wstrb[1]) count[15:8]  <= wdata[15:8];
+                if (wstrb[2]) count[23:16] <= wdata[23:16];
+                if (wstrb[3]) count[31:24] <= wdata[31:24];
             end else if (|la_write) begin
                 count <= la_write & la_input;
             end