From 181bfce79e9888732a354ffe6eca906ed9d1cb5b Mon Sep 17 00:00:00 2001 From: Kees Jongenburger Date: Mon, 16 Oct 2023 08:46:13 +0000 Subject: [PATCH] Fix typo in code documentation --- verilog/dv/la_test1/la_test1.c | 6 +++--- verilog/dv/mprj_stimulus/mprj_stimulus.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c index cad69d115..e9a78e483 100644 --- a/verilog/dv/la_test1/la_test1.c +++ b/verilog/dv/la_test1/la_test1.c @@ -26,7 +26,7 @@ - Observes counter value through LA probes [31:0] - Sets counter initial value through LA probes [63:32] - Flags when counter value exceeds 500 through the management SoC gpio - - Outputs message to the UART when the test concludes successfuly + - Outputs message to the UART when the test concludes successfully */ void main() @@ -49,8 +49,8 @@ void main() // all of the GPIO pins to be used for user functions. // The upper GPIO pins are configured to be output - // and accessble to the management SoC. - // Used to flad the start/end of a test + // and accessible to the management SoC. + // Used to flag the start/end of a test // The lower GPIO pins are configured to be output // and accessible to the user project. They show // the project count value, although this test is diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c index 55b6d1fc6..595e7ff57 100644 --- a/verilog/dv/mprj_stimulus/mprj_stimulus.c +++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c @@ -23,7 +23,7 @@ void main() { // The upper GPIO pins are configured to be output - // and accessble to the management SoC. + // and accessible to the management SoC. // Used to flag the start/end of a test // The lower GPIO pins are configured to be output // and accessible to the user project. They show @@ -92,9 +92,9 @@ void main() // Configure LA probes [31:0], [127:64] as inputs to the cpu // Configure LA probes [63:32] as outputs from the cpu reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0] - reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32] - reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64] - reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96] + reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32] + reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64] + reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96] // Flag start of the test reg_mprj_datal = 0xAB400000; @@ -133,4 +133,4 @@ void main() // Flag end of the test reg_mprj_datal = 0xAB510000; -} \ No newline at end of file +}