From 69a6c58ca7e68afbf6794fa7cd121122b9dcef58 Mon Sep 17 00:00:00 2001
From: Dimitry Andric <dim@FreeBSD.org>
Date: Tue, 19 Dec 2023 12:34:00 +0100
Subject: [PATCH] After
 https://github.com/llvm/llvm-project/commit/ac182deee8287 RISCV's global isel
 td file got split off to RISCVGISel.td, so handle that in libllvm's Makefile.

---
 lib/clang/libllvm/Makefile | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/lib/clang/libllvm/Makefile b/lib/clang/libllvm/Makefile
index 9a6c7a72c6155..f6441e0541635 100644
--- a/lib/clang/libllvm/Makefile
+++ b/lib/clang/libllvm/Makefile
@@ -2079,21 +2079,26 @@ beforebuild:
 	MCCodeEmitter/-gen-emitter \
 	MCPseudoLowering/-gen-pseudo-lowering \
 	MnemonicTables/-gen-x86-mnemonic-tables,-asmwriternum=1 \
-	O0PreLegalizeGICombiner/-gen-global-isel-combiner-matchtable,-combiners=${arch:H}O0PreLegalizerCombiner \
-	PostLegalizeGICombiner/-gen-global-isel-combiner-matchtable,-combiners=${arch:H}PostLegalizerCombiner \
-	PostLegalizeGILowering/-gen-global-isel-combiner-matchtable,-combiners=${arch:H}PostLegalizerLowering \
-	PreLegalizeGICombiner/-gen-global-isel-combiner-matchtable,-combiners=${arch:H}PreLegalizerCombiner \
+	O0PreLegalizeGICombiner/-gen-global-isel-combiner,-combiners=${arch:H}O0PreLegalizerCombiner \
+	PostLegalizeGICombiner/-gen-global-isel-combiner,-combiners=${arch:H}PostLegalizerCombiner \
+	PostLegalizeGILowering/-gen-global-isel-combiner,-combiners=${arch:H}PostLegalizerLowering \
+	PreLegalizeGICombiner/-gen-global-isel-combiner,-combiners=${arch:H}PreLegalizerCombiner \
 	RegisterBank/-gen-register-bank \
 	RegisterInfo/-gen-register-info \
 	SearchableTables/-gen-searchable-tables \
 	SubtargetInfo/-gen-subtarget \
 	SystemOperands/-gen-searchable-tables \
 	SystemRegister/-gen-searchable-tables
-${arch:T}Gen${hdr:H}.inc: ${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}.td
+.  if "${arch:T}" == "RISCV" && "${hdr:T:C/(-gen-global-isel).*/\1/}" == "-gen-global-isel"
+tdfile_${arch:T}_${hdr:H}=	${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}GISel.td
+.  else
+tdfile_${arch:T}_${hdr:H}=	${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}.td
+.endif
+${arch:T}Gen${hdr:H}.inc: ${tdfile_${arch:T}_${hdr:H}}
 	${LLVM_TBLGEN} ${hdr:T:C/,/ /g} \
 	    -I ${LLVM_SRCS}/include -I ${LLVM_SRCS}/lib/Target/${arch:H} \
 	    -d ${.TARGET}.d -o ${.TARGET} \
-	    ${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}.td
+	    ${tdfile_${arch:T}_${hdr:H}}
 . endfor
 .endfor
 .if ${MK_LLVM_TARGET_AARCH64} != "no"