From a7fb520c69780722dcd48ce30208b4128b255516 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 7 Feb 2024 22:50:52 +0100 Subject: [PATCH] Update libllvm for new RISCVGenMacroFusion.inc tblgen header. --- lib/clang/libllvm/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/clang/libllvm/Makefile b/lib/clang/libllvm/Makefile index 44ce996ba3c1e..99cdc576a5f35 100644 --- a/lib/clang/libllvm/Makefile +++ b/lib/clang/libllvm/Makefile @@ -2132,6 +2132,7 @@ beforebuild: InstrInfo/-gen-instr-info${arch:MX86/X86:C/X86\/X86/,-instr-info-expand-mi-operand-info=0/} \ MCCodeEmitter/-gen-emitter \ MCPseudoLowering/-gen-pseudo-lowering \ + MacroFusion/-gen-macro-fusion-pred \ MnemonicTables/-gen-x86-mnemonic-tables,-asmwriternum=1 \ O0PreLegalizeGICombiner/-gen-global-isel-combiner,-combiners=${arch:H}O0PreLegalizerCombiner \ PostLegalizeGICombiner/-gen-global-isel-combiner,-combiners=${arch:H}PostLegalizerCombiner \ @@ -2245,6 +2246,7 @@ TGHDRS+= RISCVGenGlobalISel.inc TGHDRS+= RISCVGenInstrInfo.inc TGHDRS+= RISCVGenMCCodeEmitter.inc TGHDRS+= RISCVGenMCPseudoLowering.inc +TGHDRS+= RISCVGenMacroFusion.inc TGHDRS+= RISCVGenO0PreLegalizeGICombiner.inc TGHDRS+= RISCVGenPostLegalizeGICombiner.inc TGHDRS+= RISCVGenPreLegalizeGICombiner.inc