From ffb299eb128943946209ad0a14d60157ae5d8e4b Mon Sep 17 00:00:00 2001 From: dzid26 Date: Wed, 5 Jun 2024 11:55:59 +0100 Subject: [PATCH] VScode debug --- .vscode/extensions.json | 3 +- .vscode/launch.json | 66 + .vscode/stm8s105s6.svd.json | 1868 +++++++++++++++++++ .vscode/tasks.json | 13 + tools/openocd-v0.10.0-scripts/stlink-v2.cfg | 16 - tools/openocd-v0.10.0-scripts/stm8s003.cfg | 81 - tools/openocd-v0.10.0-scripts/stm8s105.cfg | 81 - 7 files changed, 1949 insertions(+), 179 deletions(-) create mode 100644 .vscode/launch.json create mode 100644 .vscode/stm8s105s6.svd.json delete mode 100644 tools/openocd-v0.10.0-scripts/stlink-v2.cfg delete mode 100644 tools/openocd-v0.10.0-scripts/stm8s003.cfg delete mode 100644 tools/openocd-v0.10.0-scripts/stm8s105.cfg diff --git a/.vscode/extensions.json b/.vscode/extensions.json index fd260757..771a0969 100644 --- a/.vscode/extensions.json +++ b/.vscode/extensions.json @@ -4,6 +4,7 @@ // List of extensions which should be recommended for users of this workspace. "recommendations": [ - "ms-vscode.cpptools" + "ms-vscode.cpptools", + "cl.stm8-debug" ] } \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 00000000..891258ba --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,66 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + // "preLaunchTask": "STM8 Flash", // TODO flash with OpenOCD + "name": "stm-gdb", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceRoot}/bin/main.elf", + "args": [], + "stopAtEntry": true, + "cwd": "${workspaceRoot}/src/controller", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "stm8-gdb" + }, + "windows": { + "miDebuggerPath": "stm8-gdb.exe" // either build from source or use the one downloaded by the stm8-debug extension (add to system PATH) + }, + "setupCommands": [ + { + "description": "connect to target", + "text": "-target-select extended-remote localhost:3333", + "ignoreFailures": true + }, + { + "description": "set source file directory", + "text": "directory ${workspaceRoot}/src/controller" + } + ], + "logging": { + "moduleLoad": true, + "trace": true, + "engineLogging": true, + "programOutput": true, + "exceptions": true + }, + }, + + { // launch OpenOCD task after flashing, but before debugging // TODO flash with OpenOCD + // "preLaunchTask": "STM8 Flash", // TODO flash with OpenOCD + "name": "stm8-debug extension", // it is Windows only + "type": "stm8-debug", + "request": "launch", + "serverType": "stm8-sdcc", + "executable": "${workspaceFolder}\\bin\\main.elf", + "cpu": "STM8S105S6", + "port": "3333", + "svdFile": ".vscode\\stm8s105s6.svd.json", // based on stm8s105k4 from the demo - some registers might not be accurate + "openOcdConfigs": [ + "interface/stlink.cfg", //stm8-debug comes with sdcc 10.0 + "target/stm8s105.cfg" + ], + "customCommands": [ + "cd ${workspaceFolder}\\src", + "set remotetimeout 2000", + "set debug remote 1" + ] + } + ] +} \ No newline at end of file diff --git a/.vscode/stm8s105s6.svd.json b/.vscode/stm8s105s6.svd.json new file mode 100644 index 00000000..ff052fdc --- /dev/null +++ b/.vscode/stm8s105s6.svd.json @@ -0,0 +1,1868 @@ +[ + { + "name": "GPIOA", + "baseAddress": "0x5000", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOB", + "baseAddress": "0x5005", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOC", + "baseAddress": "0x500A", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOD", + "baseAddress": "0x500F", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOE", + "baseAddress": "0x5014", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOF", + "baseAddress": "0x5019", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOG", + "baseAddress": "0x501E", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOH", + "baseAddress": "0x5023", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "GPIOI", + "baseAddress": "0x5028", + "registers": [ + { + "name": "ODR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "IDR", + "bytes": 1, + "fields": [ + { + "name": "0", + "bitsOffset": 0, + "bitsWidth": 1 + }, + { + "name": "1", + "bitsOffset": 1, + "bitsWidth": 1 + }, + { + "name": "2", + "bitsOffset": 2, + "bitsWidth": 1 + }, + { + "name": "3", + "bitsOffset": 3, + "bitsWidth": 1 + }, + { + "name": "4", + "bitsOffset": 4, + "bitsWidth": 1 + }, + { + "name": "5", + "bitsOffset": 5, + "bitsWidth": 1 + }, + { + "name": "6", + "bitsOffset": 6, + "bitsWidth": 1 + }, + { + "name": "7", + "bitsOffset": 7, + "bitsWidth": 1 + } + ] + }, + { + "name": "DDR", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "FLASH", + "baseAddress": "0x505A", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + }, + { + "name": "NCR2", + "bytes": 1 + }, + { + "name": "FPR", + "bytes": 1 + }, + { + "name": "NFPR", + "bytes": 1 + }, + { + "name": "IAPSR", + "bytes": 1 + }, + { + "name": "PUKR", + "baseAddress": "0x5062", + "bytes": 1 + }, + { + "name": "DUKR", + "baseAddress": "0x5064", + "bytes": 1 + } + ] + }, + { + "name": "EXTI", + "baseAddress": "0x50A0", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + } + ] + }, + { + "name": "RST", + "baseAddress": "0x50B3", + "registers": [ + { + "name": "SR", + "bytes": 1 + } + ] + }, + { + "name": "CLK", + "baseAddress": "0x50C0", + "registers": [ + { + "name": "ICKR", + "bytes": 1 + }, + { + "name": "ECKR", + "bytes": 1 + }, + { + "name": "CMSR", + "baseAddress": "0x50C3", + "bytes": 1 + }, + { + "name": "SWR", + "bytes": 1 + }, + { + "name": "SWCR", + "bytes": 1 + }, + { + "name": "CKDIVR", + "bytes": 1 + }, + { + "name": "PCKENR1", + "bytes": 1 + }, + { + "name": "CSSR", + "bytes": 1 + }, + { + "name": "CCOR", + "bytes": 1 + }, + { + "name": "PCKENR2", + "bytes": 1 + }, + { + "name": "HSITRIMR", + "baseAddress": "0x50CC", + "bytes": 1 + }, + { + "name": "SWIMCCR", + "bytes": 1 + } + ] + }, + { + "name": "WWDG", + "baseAddress": "0x50D1", + "registers": [ + { + "name": "CR", + "bytes": 1 + }, + { + "name": "WR", + "bytes": 1 + } + ] + }, + { + "name": "IWDG", + "baseAddress": "0x50E0", + "registers": [ + { + "name": "KR", + "bytes": 1 + }, + { + "name": "PR", + "bytes": 1 + }, + { + "name": "RLR", + "bytes": 1 + } + ] + }, + { + "name": "AWU", + "baseAddress": "0x50F0", + "registers": [ + { + "name": "CSR1", + "bytes": 1 + }, + { + "name": "APR", + "bytes": 1 + }, + { + "name": "TBR", + "bytes": 1 + } + ] + }, + { + "name": "BEEP", + "baseAddress": "0x50F3", + "registers": [ + { + "name": "CSR", + "bytes": 1 + } + ] + }, + { + "name": "SPI", + "baseAddress": "0x5200", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + }, + { + "name": "ICR", + "bytes": 1 + }, + { + "name": "SR", + "bytes": 1 + }, + { + "name": "DR", + "bytes": 1 + }, + { + "name": "CRCPR", + "bytes": 1 + }, + { + "name": "RXCRCR", + "bytes": 1 + }, + { + "name": "TXCRCR", + "bytes": 1 + } + ] + }, + { + "name": "I2C", + "baseAddress": "0x5210", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + }, + { + "name": "FREQR", + "bytes": 1 + }, + { + "name": "OARL", + "bytes": 1 + }, + { + "name": "OARH", + "bytes": 1 + }, + { + "name": "DR", + "baseAddress": "0x5216", + "bytes": 1 + }, + { + "name": "SR1", + "bytes": 1 + }, + { + "name": "SR2", + "bytes": 1 + }, + { + "name": "SR3", + "bytes": 1 + }, + { + "name": "ITR", + "bytes": 1 + }, + { + "name": "CCRL", + "bytes": 1 + }, + { + "name": "CCRH", + "bytes": 1 + }, + { + "name": "TRISER", + "bytes": 1 + }, + { + "name": "PECR", + "bytes": 1 + } + ] + }, + { + "name": "UART2", + "baseAddress": "0x5240", + "registers": [ + { + "name": "SR", + "bytes": 1 + }, + { + "name": "DR", + "bytes": 1 + }, + { + "name": "BRR1", + "bytes": 1 + }, + { + "name": "BRR2", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + }, + { + "name": "CR3", + "bytes": 1 + }, + { + "name": "CR4", + "bytes": 1 + }, + { + "name": "CR5", + "bytes": 1 + }, + { + "name": "CR6", + "bytes": 1 + }, + { + "name": "GTR", + "bytes": 1 + }, + { + "name": "PSCR", + "bytes": 1 + } + ] + }, + { + "name": "TIM1", + "baseAddress": "0x5250", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + }, + { + "name": "SMCR", + "bytes": 1 + }, + { + "name": "ETR", + "bytes": 1 + }, + { + "name": "IER", + "bytes": 1 + }, + { + "name": "SR1", + "bytes": 1 + }, + { + "name": "SR2", + "bytes": 1 + }, + { + "name": "EGR", + "bytes": 1 + }, + { + "name": "CCMR1", + "bytes": 1 + }, + { + "name": "CCMR2", + "bytes": 1 + }, + { + "name": "CCMR3", + "bytes": 1 + }, + { + "name": "CCMR4", + "bytes": 1 + }, + { + "name": "CCER1", + "bytes": 1 + }, + { + "name": "CCER2", + "bytes": 1 + }, + { + "name": "CNTRH", + "bytes": 1 + }, + { + "name": "CNTRL", + "bytes": 1 + }, + { + "name": "PSCRH", + "bytes": 1 + }, + { + "name": "PSCRL", + "bytes": 1 + }, + { + "name": "ARRH", + "bytes": 1 + }, + { + "name": "ARRL", + "bytes": 1 + }, + { + "name": "RCR", + "bytes": 1 + }, + { + "name": "CCR1H", + "bytes": 1 + }, + { + "name": "CCR1L", + "bytes": 1 + }, + { + "name": "CCR2H", + "bytes": 1 + }, + { + "name": "CCR2L", + "bytes": 1 + }, + { + "name": "CCR3H", + "bytes": 1 + }, + { + "name": "CCR3L", + "bytes": 1 + }, + { + "name": "CCR4H", + "bytes": 1 + }, + { + "name": "CCR4L", + "bytes": 1 + }, + { + "name": "BKR", + "bytes": 1 + }, + { + "name": "DTR", + "bytes": 1 + }, + { + "name": "OISR", + "bytes": 1 + } + ] + }, + { + "name": "TIM2", + "baseAddress": "0x5300", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "IER", + "bytes": 1 + }, + { + "name": "SR1", + "bytes": 1 + }, + { + "name": "SR2", + "bytes": 1 + }, + { + "name": "EGR", + "bytes": 1 + }, + { + "name": "CCMR1", + "bytes": 1 + }, + { + "name": "CCMR2", + "bytes": 1 + }, + { + "name": "CCMR3", + "bytes": 1 + }, + { + "name": "CCER1", + "bytes": 1 + }, + { + "name": "CCER2", + "bytes": 1 + }, + { + "name": "CNTRH", + "bytes": 1 + }, + { + "name": "CNTRL", + "bytes": 1 + }, + { + "name": "PSCR", + "bytes": 1 + }, + { + "name": "ARRH", + "bytes": 1 + }, + { + "name": "ARRL", + "bytes": 1 + }, + { + "name": "CCR1H", + "bytes": 1 + }, + { + "name": "CCR1L", + "bytes": 1 + }, + { + "name": "CCR2H", + "bytes": 1 + }, + { + "name": "CCR2L", + "bytes": 1 + }, + { + "name": "CCR3H", + "bytes": 1 + }, + { + "name": "CCR3L", + "bytes": 1 + } + ] + }, + { + "name": "TIM3", + "baseAddress": "0x5320", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "IER", + "bytes": 1 + }, + { + "name": "SR1", + "bytes": 1 + }, + { + "name": "SR2", + "bytes": 1 + }, + { + "name": "EGR", + "bytes": 1 + }, + { + "name": "CCMR1", + "bytes": 1 + }, + { + "name": "CCMR2", + "bytes": 1 + }, + { + "name": "CCER1", + "bytes": 1 + }, + { + "name": "CNTRH", + "bytes": 1 + }, + { + "name": "CNTRL", + "bytes": 1 + }, + { + "name": "PSCR", + "bytes": 1 + }, + { + "name": "ARRH", + "bytes": 1 + }, + { + "name": "ARRL", + "bytes": 1 + }, + { + "name": "CCR1H", + "bytes": 1 + }, + { + "name": "CCR1L", + "bytes": 1 + }, + { + "name": "CCR2H", + "bytes": 1 + }, + { + "name": "CCR2L", + "bytes": 1 + } + ] + }, + { + "name": "TIM4", + "baseAddress": "0x5340", + "registers": [ + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "IER", + "bytes": 1 + }, + { + "name": "SR", + "bytes": 1 + }, + { + "name": "EGR", + "bytes": 1 + }, + { + "name": "CNTR", + "bytes": 1 + }, + { + "name": "PSCR", + "bytes": 1 + }, + { + "name": "ARR", + "bytes": 1 + } + ] + }, + { + "name": "ADC1", + "baseAddress": "0x53E0", + "registers": [ + { + "name": "DB0R", + "bytes": 2 + }, + { + "name": "DB1R", + "bytes": 2 + }, + { + "name": "DB2R", + "bytes": 2 + }, + { + "name": "DB3R", + "bytes": 2 + }, + { + "name": "DB4R", + "bytes": 2 + }, + { + "name": "DB5R", + "bytes": 2 + }, + { + "name": "DB6R", + "bytes": 2 + }, + { + "name": "DB7R", + "bytes": 2 + }, + { + "name": "DB8R", + "bytes": 2 + }, + { + "name": "DB9R", + "bytes": 2 + }, + { + "name": "CSR", + "baseAddress": "0x5400", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + }, + { + "name": "CR3", + "bytes": 1 + }, + { + "name": "DRH", + "bytes": 1 + }, + { + "name": "DRL", + "bytes": 1 + }, + { + "name": "TDRH", + "bytes": 1 + }, + { + "name": "TDRL", + "bytes": 1 + }, + { + "name": "HTRH", + "bytes": 1 + }, + { + "name": "HTRL", + "bytes": 1 + }, + { + "name": "LTRH", + "bytes": 1 + }, + { + "name": "LTRL", + "bytes": 1 + }, + { + "name": "AWSRH", + "bytes": 1 + }, + { + "name": "AWSRL", + "bytes": 1 + }, + { + "name": "AWCRH", + "bytes": 1 + }, + { + "name": "AWCRL", + "bytes": 1 + } + ] + }, + { + "name": "ITC", + "baseAddress": "0x7F70", + "registers": [ + { + "name": "SPR1", + "bytes": 1 + }, + { + "name": "SPR2", + "bytes": 1 + }, + { + "name": "SPR3", + "bytes": 1 + }, + { + "name": "SPR4", + "bytes": 1 + }, + { + "name": "SPR5", + "bytes": 1 + }, + { + "name": "SPR6", + "bytes": 1 + }, + { + "name": "SPR7", + "bytes": 1 + }, + { + "name": "SPR8", + "bytes": 1 + } + ] + }, + { + "name": "SWIM", + "baseAddress": "0x7F80", + "registers": [ + { + "name": "CSR", + "bytes": 1 + } + ] + }, + { + "name": "DM", + "baseAddress": "0x7F90", + "registers": [ + { + "name": "BK1RE", + "bytes": 1 + }, + { + "name": "BK1RH", + "bytes": 1 + }, + { + "name": "BK1RL", + "bytes": 1 + }, + { + "name": "BK2RE", + "bytes": 1 + }, + { + "name": "BK2RH", + "bytes": 1 + }, + { + "name": "BK2RL", + "bytes": 1 + }, + { + "name": "CR1", + "bytes": 1 + }, + { + "name": "CR2", + "bytes": 1 + }, + { + "name": "CSR1", + "bytes": 1 + }, + { + "name": "CSR2", + "bytes": 1 + }, + { + "name": "ENFCTR", + "bytes": 1 + } + ] + } +] \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json index 4ac75c95..de904bed 100644 --- a/.vscode/tasks.json +++ b/.vscode/tasks.json @@ -52,6 +52,19 @@ "close": false }, "problemMatcher": [] + }, + + { + "label": "Launch OpenOCD", + "type": "shell", + "command": "openocd", + "args": [ + "-f", + "interface/stlink-dap.cfg", //swim is @stlink-dap in openocd > 10.0 + "-f", + "target/stm8s105.cfg" + ] + } ], } \ No newline at end of file diff --git a/tools/openocd-v0.10.0-scripts/stlink-v2.cfg b/tools/openocd-v0.10.0-scripts/stlink-v2.cfg deleted file mode 100644 index ae545a11..00000000 --- a/tools/openocd-v0.10.0-scripts/stlink-v2.cfg +++ /dev/null @@ -1,16 +0,0 @@ -# -# STMicroelectronics ST-LINK/V2 in-circuit debugger/programmer -# - -interface hla -hla_layout stlink -hla_device_desc "ST-LINK/V2" -hla_vid_pid 0x0483 0x3748 - -# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2 -# devices seem to have serial numbers with unreadable characters. ST-LINK/V2 -# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial -# number reset issues. -# eg. -#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f" - diff --git a/tools/openocd-v0.10.0-scripts/stm8s003.cfg b/tools/openocd-v0.10.0-scripts/stm8s003.cfg deleted file mode 100644 index 8a64b9eb..00000000 --- a/tools/openocd-v0.10.0-scripts/stm8s003.cfg +++ /dev/null @@ -1,81 +0,0 @@ -# script for stm8 family - -# -# stm8 devices support SWIM transports only. -# - -transport select stlink_swim - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm8 -} - -# Work-area is a space in RAM used for flash programming -# By default use 1kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x400 -} - -if { [info exists FLASHSTART] } { - set _FLASHSTART $FLASHSTART -} else { - set _FLASHSTART 0x8000 -} - -if { [info exists FLASHEND] } { - set _FLASHEND $FLASHEND -} else { - set _FLASHEND 0xffff -} - -if { [info exists EEPROMSTART] } { - set _EEPROMSTART $EEPROMSTART -} else { - set _EEPROMSTART 0x4000 -} - -if { [info exists EEPROMEND] } { - set _EEPROMEND $EEPROMEND -} else { - set _EEPROMEND 0x43ff -} - -if { [info exists OPTIONSTART] } { - set _OPTIONSTART $OPTIONSTART -} else { - set _OPTIONSTART 0x4800 -} - -if { [info exists OPTIONEND] } { - set _OPTIONEND $OPTIONEND -} else { - set _OPTIONEND 0x487f -} - -if { [info exists BLOCKSIZE] } { - set _BLOCKSIZE $BLOCKSIZE -} else { - set _BLOCKSIZE 0x40 -} - -hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME stm8 -chain-position stm8.cpu - -$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1 -$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND -optionstart $_OPTIONSTART -optionend $_EEPROMEND -blocksize $_BLOCKSIZE - -if { [info exists ENABLE_STEP_IRQ] } { - $_TARGETNAME configure -enable_step_irq -} - -adapter_khz 0 - -reset_config srst_only - diff --git a/tools/openocd-v0.10.0-scripts/stm8s105.cfg b/tools/openocd-v0.10.0-scripts/stm8s105.cfg deleted file mode 100644 index f83bff2c..00000000 --- a/tools/openocd-v0.10.0-scripts/stm8s105.cfg +++ /dev/null @@ -1,81 +0,0 @@ -# script for stm8 family - -# -# stm8 devices support SWIM transports only. -# - -transport select stlink_swim - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm8 -} - -# Work-area is a space in RAM used for flash programming -# By default use 1kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x400 -} - -if { [info exists FLASHSTART] } { - set _FLASHSTART $FLASHSTART -} else { - set _FLASHSTART 0x8000 -} - -if { [info exists FLASHEND] } { - set _FLASHEND $FLASHEND -} else { - set _FLASHEND 0xffff -} - -if { [info exists EEPROMSTART] } { - set _EEPROMSTART $EEPROMSTART -} else { - set _EEPROMSTART 0x4000 -} - -if { [info exists EEPROMEND] } { - set _EEPROMEND $EEPROMEND -} else { - set _EEPROMEND 0x43ff -} - -if { [info exists OPTIONSTART] } { - set _OPTIONSTART $OPTIONSTART -} else { - set _OPTIONSTART 0x4800 -} - -if { [info exists OPTIONEND] } { - set _OPTIONEND $OPTIONEND -} else { - set _OPTIONEND 0x487f -} - -if { [info exists BLOCKSIZE] } { - set _BLOCKSIZE $BLOCKSIZE -} else { - set _BLOCKSIZE 0x80 -} - -hla newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0 - -set _TARGETNAME $_CHIPNAME.cpu - -target create $_TARGETNAME stm8 -chain-position stm8.cpu - -$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1 -$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND -optionstart $_OPTIONSTART -optionend $_EEPROMEND -blocksize $_BLOCKSIZE - -if { [info exists ENABLE_STEP_IRQ] } { - $_TARGETNAME configure -enable_step_irq -} - -adapter_khz 10 - -reset_config srst_only -