diff --git a/board/drivers/clock.h b/board/drivers/clock.h
index a9f2dea730495f..d564c7f01db28d 100644
--- a/board/drivers/clock.h
+++ b/board/drivers/clock.h
@@ -3,7 +3,7 @@ void clock_init(void) {
   RCC->CR |= RCC_CR_HSEON;
   while ((RCC->CR & RCC_CR_HSERDY) == 0);
 
-  // divide shit
+  // divide things
   RCC->CFGR = RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4;
 
   // 16mhz crystal
diff --git a/board/drivers/usb.h b/board/drivers/usb.h
index 84cc81ffb4eaa0..0efa0037b45602 100644
--- a/board/drivers/usb.h
+++ b/board/drivers/usb.h
@@ -416,7 +416,7 @@ void USB_WritePacket(const uint8_t *src, uint16_t len, uint32_t ep) {
   uint32_t count32b = 0;
   count32b = (len + 3U) / 4U;
 
-  // bullshit
+  // TODO: revisit this
   USBx_INEP(ep)->DIEPTSIZ = ((numpacket << 19) & USB_OTG_DIEPTSIZ_PKTCNT) |
                             (len               & USB_OTG_DIEPTSIZ_XFRSIZ);
   USBx_INEP(ep)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
@@ -734,7 +734,6 @@ void usb_init(void) {
   USBx->GAHBCFG = USB_OTG_GAHBCFG_GINT;
 
   // DCTL startup value is 2 on new chip, 0 on old chip
-  // THIS IS FUCKING BULLSHIT
   USBx_DEVICE->DCTL = 0;
 
   // enable the IRQ
diff --git a/tests/gmbitbang/test_one.py b/tests/gmbitbang/test_one.py
index a398e2780385b1..d7d430437dcabb 100755
--- a/tests/gmbitbang/test_one.py
+++ b/tests/gmbitbang/test_one.py
@@ -5,7 +5,7 @@
 p = Panda()
 p.set_safety_mode(Panda.SAFETY_ALLOUTPUT)
 
-# ack any crap on bus
+# hack anything on bus
 p.set_gmlan(bus=2)
 time.sleep(0.1)
 while len(p.can_recv()) > 0: