From 80beb153276eaceac99d63b50f58f3444ea589df Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 13 Feb 2024 19:09:33 +0100 Subject: [PATCH] bench/serwb/demo: Ad SRAM on iCEBreaker and demonstrate use of RegionsRemapper to access SRAM from LiteICLink. Also lower sys_clk_freq to 25MHz for timings on iCEBreaker with SRAM. --- bench/serwb/demo/README.md | 25 +++++++++++++++++-------- bench/serwb/demo/ecpix5.py | 6 +++--- bench/serwb/demo/icebreaker.py | 17 +++++++++++++++-- 3 files changed, 35 insertions(+), 13 deletions(-) diff --git a/bench/serwb/demo/README.md b/bench/serwb/demo/README.md index 86bb075..dc3e6bb 100644 --- a/bench/serwb/demo/README.md +++ b/bench/serwb/demo/README.md @@ -36,6 +36,7 @@ Access over Etherbone to the peripherlas of the ECXPIX-5 and iCEBreaker can be t following commands: litex_server --udp + # Test Access to CSR registers through SerWB litex_cli --regs 0x00000000 : 0x00000000 ctrl_reset 0x00000004 : 0x12345678 ctrl_scratch @@ -51,11 +52,19 @@ following commands: 0x00001810 : 0x00000000 serwb_master_phy_control_prbs_start 0x00001814 : 0x00000000 serwb_master_phy_control_prbs_cycles 0x00001818 : 0x00000000 serwb_master_phy_control_prbs_errors - 0x30000000 : 0x00000000 icebreaker_soc_ctrl_reset - 0x30000004 : 0x12345678 icebreaker_soc_ctrl_scratch - 0x30000008 : 0x00000000 icebreaker_soc_ctrl_bus_errors - 0x30001000 : 0x00000001 icebreaker_soc_serwb_slave_phy_control_ready - 0x30001004 : 0x00000000 icebreaker_soc_serwb_slave_phy_control_error - 0x30001008 : 0x00000018 icebreaker_soc_serwb_slave_phy_control_shift - 0x3000100c : 0x00000000 icebreaker_soc_serwb_slave_phy_control_prbs_start - 0x30001010 : 0x00000000 icebreaker_soc_serwb_slave_phy_control_prbs_cycles \ No newline at end of file + 0x40000000 : 0x00000000 icebreaker_soc_ctrl_reset + 0x40000004 : 0x12345678 icebreaker_soc_ctrl_scratch + 0x40000008 : 0x00000000 icebreaker_soc_ctrl_bus_errors + 0x40001000 : 0x00000001 icebreaker_soc_serwb_slave_phy_control_ready + 0x40001004 : 0x00000000 icebreaker_soc_serwb_slave_phy_control_error + 0x40001008 : 0x00000018 icebreaker_soc_serwb_slave_phy_control_shift + 0x4000100c : 0x00000000 icebreaker_soc_serwb_slave_phy_control_prbs_start + 0x40001010 : 0x00000000 icebreaker_soc_serwb_slave_phy_control_prbs_cycles + + # Test Access to SRAM through SerWB + litex_cli --write 0x50000000 0x12345678 + litex_cli --write 0x50000004 0x5aa55aa5 + litex_cli --read 0x50000000 + 0x50000000 : 0x12345678 + litex_cli --read 0x50000004 + 0x50000004 : 0x5aa55aa5 diff --git a/bench/serwb/demo/ecpix5.py b/bench/serwb/demo/ecpix5.py index 3642333..923846a 100755 --- a/bench/serwb/demo/ecpix5.py +++ b/bench/serwb/demo/ecpix5.py @@ -45,7 +45,7 @@ class SerWBDemoSoC(SoCMini): def __init__(self, platform, with_analyzer=False): - sys_clk_freq = int(50e6) + sys_clk_freq = int(25e6) # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq) @@ -87,7 +87,7 @@ def __init__(self, platform, with_analyzer=False): # Add SerWB as Slave to SoC. # -------------------------- - self.bus.add_slave("serwb", self.serwb_master_core.bus, SoCRegion(origin=0x30000000, size=0x1000000)) + self.bus.add_slave("serwb", self.serwb_master_core.bus, SoCRegion(origin=0x40000000, size=0x20000000)) # Leds ------------------------------------------------------------------------------------- leds_pads = [] @@ -128,7 +128,7 @@ def main(): platform.add_extension(serwb_io) soc = SerWBDemoSoC(platform, with_analyzer=args.with_analyzer) builder = Builder(soc, csr_csv="csr.csv") - builder.add_json("icebreaker_soc.json", 0x30000000, "icebreaker_soc") + builder.add_json("icebreaker_soc.json", 0x40000000, "icebreaker_soc") builder.build(run=args.build) if args.load: diff --git a/bench/serwb/demo/icebreaker.py b/bench/serwb/demo/icebreaker.py index 2278551..6e85774 100755 --- a/bench/serwb/demo/icebreaker.py +++ b/bench/serwb/demo/icebreaker.py @@ -42,7 +42,7 @@ class SerWBDemoSoC(SoCMini): def __init__(self, platform, with_analyzer=False): - sys_clk_freq = int(50e6) + sys_clk_freq = int(25e6) # CRG -------------------------------------------------------------------------------------- self.cd_sys = ClockDomain() @@ -52,6 +52,8 @@ def __init__(self, platform, with_analyzer=False): csr_data_width = 32, ident = "LiteICLink SerWB demo on iCEBreaker", ident_version = True, + with_integrated_main_ram = True, + integrated_main_ram_size = 1024, ) # UARTBone --------------------------------------------------------------------------------- @@ -77,7 +79,18 @@ def __init__(self, platform, with_analyzer=False): # Add SerWB as Master to SoC. # --------------------------- - self.bus.add_master("serwb", self.serwb_slave_core.bus, SoCRegion(origin=0x00000000, size=0x10000000)) + self.bus.add_master("serwb", self.serwb_slave_core.bus, SoCRegion(origin=0x00000000, size=0x20000000)) + + # Address Remapping. + # ------------------ + serwb_bus = wishbone.Interface(address_width=32, data_width=32) + self.submodules += wishbone.RegionsRemapper( + master = self.bus.masters["serwb"], + slave = serwb_bus, + src_regions = [SoCRegion(origin=0x10000000, size=0x10000000)], + dst_regions = [SoCRegion(origin=0x40000000, size=0x10000000)], + ) + self.bus.masters["serwb"] = serwb_bus # Leds ------------------------------------------------------------------------------------- self.comb += [