From bf1ed9036b83f7570b99badb9a068cc55a8871dd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Feb 2024 11:32:11 +0100 Subject: [PATCH] bench/serwb: Minor cleanup and updates. --- bench/serwb/icebreaker.py | 65 +++++++++++++-------- bench/serwb/nexys_video.py | 67 ++++++++++++++-------- bench/serwb/sim.py | 91 +++++++++++++++++------------- bench/serwb/t120_bga576_dev_kit.py | 69 ++++++++++++---------- bench/serwb/test_serwb.py | 18 ++++-- bench/serwb/ti60_f225_dev_kit.py | 62 +++++++++++--------- bench/serwb/trellisboard.py | 69 ++++++++++++---------- bench/serwb/ulx3s.py | 63 ++++++++++++--------- 8 files changed, 297 insertions(+), 207 deletions(-) diff --git a/bench/serwb/icebreaker.py b/bench/serwb/icebreaker.py index ad5154a..a8b4f12 100755 --- a/bench/serwb/icebreaker.py +++ b/bench/serwb/icebreaker.py @@ -3,7 +3,7 @@ # # This file is part of LiteICLink. # -# Copyright (c) 2020-2023 Florent Kermarrec +# Copyright (c) 2020-2024 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import argparse @@ -65,7 +65,8 @@ def __init__(self, platform, loopback=False, with_analyzer=False): ident = "LiteICLink SerWB bench on iCEBreaker", ident_version = True, with_uart = True, - uart_name = "uartbone") + uart_name = "uartbone", + ) # SerWB ------------------------------------------------------------------------------------ # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected @@ -79,43 +80,59 @@ def __init__(self, platform, loopback=False, with_analyzer=False): # +--------+ +------+ +------+ +------+ # ------------------------------------------------------------------------------------------ - # Pads + # Pads. + # ----- if loopback: serwb_master_pads = Record([("tx", 1), ("rx", 1)]) serwb_slave_pads = Record([("tx", 1), ("rx", 1)]) - self.comb += serwb_slave_pads.rx.eq(serwb_master_pads.tx) - self.comb += serwb_master_pads.rx.eq(serwb_slave_pads.tx) + self.comb += [ + serwb_slave_pads.rx.eq(serwb_master_pads.tx), + serwb_master_pads.rx.eq(serwb_slave_pads.tx), + ] else: serwb_master_pads = platform.request("serwb_master") serwb_slave_pads = platform.request("serwb_slave") - # Master + # Master. + # ------- self.serwb_master_phy = SERWBPHY( device = platform.device, pads = serwb_master_pads, - mode = "master") + mode = "master", + ) - # Slave + # Slave. + # ------ self.serwb_slave_phy = SERWBPHY( device = platform.device, pads = serwb_slave_pads, - mode ="slave") - - # Wishbone Slave - serwb_master_core = SERWBCore(self.serwb_master_phy, self.clk_freq, mode="slave", + mode ="slave", + ) + + # Wishbone Slave. + # --------------- + self.serwb_master_core = serwb_master_core = SERWBCore( + phy = self.serwb_master_phy, + clk_freq = self.clk_freq, + mode = "slave", etherbone_buffer_depth = 1, tx_buffer_depth = 0, - rx_buffer_depth = 0) - self.submodules += serwb_master_core - - # Wishbone Master - serwb_slave_core = SERWBCore(self.serwb_slave_phy, self.clk_freq, mode="master", + rx_buffer_depth = 0, + ) + + # Wishbone Master. + # ---------------- + self.serwb_slave_core = serwb_slave_core = SERWBCore( + phy = self.serwb_slave_phy, + clk_freq = self.clk_freq, + mode = "master", etherbone_buffer_depth = 1, tx_buffer_depth = 0, - rx_buffer_depth = 0) - self.submodules += serwb_slave_core + rx_buffer_depth = 0, + ) - # Wishbone SRAM + # Wishbone SRAM. + # -------------- self.serwb_sram = Up5kSPRAM(size=64*kB) self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192)) self.comb += serwb_slave_core.bus.connect(self.serwb_sram.bus) @@ -131,10 +148,10 @@ def __init__(self, platform, loopback=False, with_analyzer=False): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on iCEBreaker") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") - parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs)") + parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on iCEBreaker.") + parser.add_argument("--build", action="store_true", help="Build bitstream.") + parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM).") + parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs).") args = parser.parse_args() platform = icebreaker.Platform() diff --git a/bench/serwb/nexys_video.py b/bench/serwb/nexys_video.py index 6fe50d4..008d7fe 100755 --- a/bench/serwb/nexys_video.py +++ b/bench/serwb/nexys_video.py @@ -3,7 +3,7 @@ # # This file is part of LiteICLink. # -# Copyright (c) 2017-2023 Florent Kermarrec +# Copyright (c) 2017-2024 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import argparse @@ -32,7 +32,7 @@ # IOs ---------------------------------------------------------------------------------------------- serwb_io = [ - # HDMI loopback + # HDMI loopback. ("serwb_master", 0, Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")), # hdmi_out clk Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")), # hdmi_out clk @@ -63,6 +63,8 @@ def __init__(self, platform, sys_clk_freq): # # # + # PLL. + # ---- self.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -70,6 +72,8 @@ def __init__(self, platform, sys_clk_freq): pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_idelay, 200e6) + # IDelayCtrl. + # ----------- self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # SerWBTestSoC ------------------------------------------------------------------------------------ @@ -92,7 +96,8 @@ def __init__(self, platform, low_speed=True, with_analyzer=True): ident = "LiteICLink SerWB bench on Nexys Video", ident_version = True, with_uart = True, - uart_name = "uartbone") + uart_name = "uartbone", + ) # SerWB ------------------------------------------------------------------------------------ # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected @@ -106,32 +111,48 @@ def __init__(self, platform, low_speed=True, with_analyzer=True): # +--------+ +------+ +------+ +------+ # ------------------------------------------------------------------------------------------ - # Enable + # Enable. + # ------- self.comb += platform.request("serwb_enable").eq(1) + # PHY. + # ---- phy_cls = SERWBLowSpeedPHY if low_speed else SERWBPHY - # Master + # Master. + # ------- self.serwb_master_phy = phy_cls( device = platform.device, pads = platform.request("serwb_master"), - mode = "master") + mode = "master", + ) - # Slave + # Slave. + # ------ self.serwb_slave_phy = phy_cls( device = platform.device, pads = platform.request("serwb_slave"), - mode ="slave") - - # Wishbone Slave - serwb_master_core = SERWBCore(self.serwb_master_phy, self.clk_freq, mode="slave") - self.submodules += serwb_master_core - - # Wishbone Master - serwb_slave_core = SERWBCore(self.serwb_slave_phy, self.clk_freq, mode="master") - self.submodules += serwb_slave_core - - # Wishbone SRAM + mode ="slave", + ) + + # Wishbone Slave. + # --------------- + self.serwb_master_core = serwb_master_core = SERWBCore( + phy = self.serwb_master_phy, + clk_freq = self.clk_freq, + mode = "slave", + ) + + # Wishbone Master. + # ---------------- + self.serwb_slave_core = serwb_slave_core = SERWBCore( + phy = self.serwb_slave_phy, + clk_freq = self.clk_freq, + mode = "master", + ) + + # Wishbone SRAM. + # -------------- self.serwb_sram = wishbone.SRAM(8192) self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192)) self.comb += serwb_slave_core.bus.connect(self.serwb_sram.bus) @@ -170,11 +191,11 @@ def __init__(self, platform, low_speed=True, with_analyzer=True): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on Nexys Video") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") - parser.add_argument("--low-speed", action="store_true", help="Use Low-Speed PHY") - parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer") + parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on Nexys Video.") + parser.add_argument("--build", action="store_true", help="Build bitstream.") + parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM).") + parser.add_argument("--low-speed", action="store_true", help="Use Low-Speed PHY.") + parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer.") args = parser.parse_args() platform = digilent_nexys_video.Platform() diff --git a/bench/serwb/sim.py b/bench/serwb/sim.py index 63f505f..5b4912e 100755 --- a/bench/serwb/sim.py +++ b/bench/serwb/sim.py @@ -3,7 +3,7 @@ # # This file is part of LiteICLink. # -# Copyright (c) 2020-2023 Florent Kermarrec +# Copyright (c) 2020-2024 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause import argparse @@ -32,8 +32,11 @@ # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst. ("sys_clk", 0, Pins(1)), ("sys_rst", 0, Pins(1)), + + # Serial. ("serial", 0, Subsignal("source_valid", Pins(1)), Subsignal("source_ready", Pins(1)), @@ -43,6 +46,7 @@ Subsignal("sink_ready", Pins(1)), Subsignal("sink_data", Pins(8)), ), + # Ethernet. ("eth", 0, Subsignal("source_valid", Pins(1)), Subsignal("source_ready", Pins(1)), @@ -77,34 +81,38 @@ def __init__(self): # SerWB ------------------------------------------------------------------------------------ - # Pads + # Pads. + # ----- serwb_master_pads = Record([("tx", 1), ("rx", 1)]) serwb_slave_pads = Record([("tx", 1), ("rx", 1)]) self.comb += serwb_slave_pads.rx.eq(serwb_master_pads.tx) self.comb += serwb_master_pads.rx.eq(serwb_slave_pads.tx) - # Master - serwb_master_phy = SERWBPHY( + # Master. + # ------- + self.serwb_master_phy = serwb_master_phy = SERWBPHY( device = platform.device, pads = serwb_master_pads, mode = "master", - init_timeout = 128) - self.submodules += serwb_master_phy + init_timeout = 128 + ) - # Slave - serwb_slave_phy = SERWBPHY( + # Slave. + # ------ + self.serwb_slave_phy = serwb_slave_phy = SERWBPHY( device = platform.device, pads = serwb_slave_pads, mode ="slave", - init_timeout = 128) - self.submodules += serwb_slave_phy + init_timeout = 128, + ) - # Simulation Timer + # Sim Timer. + # ---------- timer = Signal(32) self.sync += timer.eq(timer + 1) - - # Simulation Gen/Check + # Sim Gen/Check. + # -------------- class EndpointCounterGenerator(Module): def __init__(self, name, ready, endpoint): counter = Signal(32) @@ -131,16 +139,19 @@ def __init__(self, name, ready, endpoint): ready = serwb_master_phy.init.ready & serwb_slave_phy.init.ready - # Master gen/check + # Master gen/check. + # ----------------- self.submodules += EndpointCounterGenerator("Master", ready=ready, endpoint=serwb_master_phy.sink) self.submodules += EndpointCounterChecker("Master", ready=ready, endpoint=serwb_master_phy.source) - # Slave gen/check + # Slave gen/check. + # ---------------- self.submodules += EndpointCounterGenerator("Slave", ready=ready, endpoint=serwb_slave_phy.sink) self.submodules += EndpointCounterChecker("Slave", ready=ready, endpoint=serwb_slave_phy.source) - # Simulation Status + # Simu Status. + # ------------ serwb_master_phy.init.fsm.finalize() serwb_slave_phy.init.fsm.finalize() for phy, fsm in [ @@ -172,23 +183,15 @@ def __init__(self): ident = "LiteICLink SerWB bench simulation", ident_version = True, with_uart = True, - uart_name = "sim") + uart_name = "sim", + ) # CRG -------------------------------------------------------------------------------------- self.crg = CRG(platform.request("sys_clk")) # Etherbone--------------------------------------------------------------------------------- - # phy self.ethphy = LiteEthPHYModel(self.platform.request("eth")) - # core - ethcore = LiteEthUDPIPCore(self.ethphy, - mac_address = 0x10e2d5000000, - ip_address = "192.168.1.50", - clk_freq = sys_clk_freq) - self.ethcore = ethcore - # etherbone - self.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234, mode="master") - self.bus.add_master(master=self.etherbone.wishbone.bus) + self.add_etherbone(phy=self.ethphy) # SerWB ------------------------------------------------------------------------------------ # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected @@ -202,35 +205,43 @@ def __init__(self): # +--------+ +------+ +------+ +------+ # ------------------------------------------------------------------------------------------ - # Pads + # Pads. + # ----- serwb_master_pads = Record([("tx", 1), ("rx", 1)]) serwb_slave_pads = Record([("tx", 1), ("rx", 1)]) self.comb += serwb_slave_pads.rx.eq(serwb_master_pads.tx) self.comb += serwb_master_pads.rx.eq(serwb_slave_pads.tx) - # Master + # Master. + # ------- self.serwb_master_phy = SERWBPHY( device = platform.device, pads = serwb_master_pads, mode = "master", - init_timeout = 128) + init_timeout = 128, + ) - # Slave + # Slave. + # ------ self.serwb_slave_phy = SERWBPHY( device = platform.device, pads = serwb_slave_pads, mode ="slave", - init_timeout = 128) + init_timeout = 128, + ) - # Wishbone Slave + # Wishbone Slave. + # --------------- serwb_master_core = SERWBCore(self.serwb_master_phy, self.clk_freq, mode="slave") self.submodules += serwb_master_core - # Wishbone Master + # Wishbone Master. + # ---------------- serwb_slave_core = SERWBCore(self.serwb_slave_phy, self.clk_freq, mode="master") self.submodules += serwb_slave_core - # Wishbone SRAM + # Wishbone SRAM. + # -------------- self.serwb_sram = wishbone.SRAM(8192) self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192)) self.comb += serwb_slave_core.bus.connect(self.serwb_sram.bus) @@ -238,11 +249,11 @@ def __init__(self): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="SerWB LiteX/Verilator Simulation") - parser.add_argument("--min", action="store_true", help="Run Minimal simulation (SerSBMinSoC)") - parser.add_argument("--trace", action="store_true", help="Enable VCD tracing") - parser.add_argument("--trace-start", default="0", help="Cycle to start VCD tracing") - parser.add_argument("--trace-end", default="-1", help="Cycle to end VCD tracing") + parser = argparse.ArgumentParser(description="SerWB LiteX/Verilator Simulation.") + parser.add_argument("--min", action="store_true", help="Run Minimal simulation (SerSBMinSoC).") + parser.add_argument("--trace", action="store_true", help="Enable VCD tracing.") + parser.add_argument("--trace-start", default="0", help="Cycle to start VCD tracing.") + parser.add_argument("--trace-end", default="-1", help="Cycle to end VCD tracing.") args = parser.parse_args() sim_config = SimConfig() diff --git a/bench/serwb/t120_bga576_dev_kit.py b/bench/serwb/t120_bga576_dev_kit.py index 9eb6765..8fa83fe 100755 --- a/bench/serwb/t120_bga576_dev_kit.py +++ b/bench/serwb/t120_bga576_dev_kit.py @@ -3,9 +3,9 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2023 MoTeC -# Copyright (c) 2023 Gwenhael Goavec-Merou -# Copyright (c) 2017-2023 Florent Kermarrec +# Copyright (c) 2023-2024 MoTeC +# Copyright (c) 2023-2024 Gwenhael Goavec-Merou +# Copyright (c) 2017-2024 Florent Kermarrec from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer @@ -30,6 +30,7 @@ from litescope import LiteScopeAnalyzer # IOs ---------------------------------------------------------------------------------------------- + master_connector = "P2" slave_connector = "P3" serwb_io = [ @@ -69,13 +70,17 @@ def __init__(self, platform, sys_clk_freq, clk_ratio="1:1"): # # # + # Parameters. + # ----------- sys_clk_freq_div = {"1:1":1, "1:2":2, "1:4":4}[clk_ratio] # Clk/Rst. + # -------- clk40 = platform.request("clk40") rst_n = platform.request("user_btn", 0) - # PLL + # PLL. + # ---- self.pll = pll = TRIONPLL(platform) self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk40, 40e6) @@ -102,7 +107,8 @@ def __init__(self, platform, sys_clk_freq=100e6, clk_ratio="1:4", with_analyzer= ident = f"LiteICLink SerWB bench @ {int(sys_clk_freq/1e6):d}MHz on Efinix Trion T120 BGA576 Dev Kit", ident_version = True, with_uart = True, - uart_name = "uartbone") + uart_name = "uartbone", + ) # SerWB ------------------------------------------------------------------------------------ # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected @@ -116,9 +122,10 @@ def __init__(self, platform, sys_clk_freq=100e6, clk_ratio="1:4", with_analyzer= # +--------+ +-------+ +-------+ +------+ # ------------------------------------------------------------------------------------------ - # SerWB Master --------------------------------------------------------------------------- - # PHY - serwb_master_phy = SERWBPHY( + # SerWB Master ----------------------------------------------------------------------------- + # PHY. + # ---- + self.serwb_master_phy = serwb_master_phy = SERWBPHY( device = self.platform.device, pads = self.platform.request("serwb_master"), mode = "master", @@ -126,40 +133,45 @@ def __init__(self, platform, sys_clk_freq=100e6, clk_ratio="1:4", with_analyzer= clk4x = "serwb_phy4x", clk_ratio = clk_ratio, ) - self.submodules.serwb_master_phy = serwb_master_phy - # Core - serwb_master_core = SERWBCore(serwb_master_phy, self.clk_freq, mode="slave", + # Core. + # ----- + self.serwb_master_core = serwb_master_core = SERWBCore( + phy = serwb_master_phy, + clk_freq = self.clk_freq, + mode = "slave", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8 + rx_buffer_depth = 8, ) - self.submodules += serwb_master_core # Connect as peripheral to main SoC. + # ---------------------------------- self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=1024)) # SerWB Slave ---------------------------------------------------------------------------- - # PHY - serwb_slave_phy = SERWBPHY( + # PHY. + # ---- + self.serwb_slave_phy = serwb_slave_phy = ClockDomainsRenamer("rx_sys")(SERWBPHY( device = self.platform.device, pads = self.platform.request("serwb_slave"), mode = "slave", clk_ratio = clk_ratio, - ) - serwb_slave_phy = ClockDomainsRenamer("rx_sys")(serwb_slave_phy) - self.submodules.serwb_slave_phy = serwb_slave_phy - - # Core - serwb_slave_core = SERWBCore(serwb_slave_phy, self.clk_freq, mode="master", + )) + + # Core. + # ----- + self.serwb_slave_core = serwb_slave_core = ClockDomainsRenamer("rx_sys")(SERWBCore( + phy = serwb_slave_phy, + clk_freq = self.clk_freq, + mode = "master", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8 - ) - serwb_slave_core = ClockDomainsRenamer("rx_sys")(serwb_slave_core) - self.submodules += serwb_slave_core + rx_buffer_depth = 8, + )) - # Wishbone SRAM + # Wishbone SRAM. + # -------------- serwb_sram = ClockDomainsRenamer("rx_sys")(wishbone.SRAM(1024)) self.submodules += serwb_sram self.comb += serwb_slave_core.bus.connect(serwb_sram.bus) @@ -185,14 +197,13 @@ def __init__(self, platform, sys_clk_freq=100e6, clk_ratio="1:4", with_analyzer= ] self.analyzer = LiteScopeAnalyzer(analyzer_signals, 256, csr_csv="analyzer.csv") - # Build -------------------------------------------------------------------------------------------- def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_trion_t120_bga576_dev_kit.Platform, description="LiteICLink SerWB bench on Efinix Trion T120 BGA576 Dev Kit.") - parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") - parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer") + parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") + parser.add_target_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer.") parser.add_target_argument("--lvds-rx-delay", default=0, type=int, help="Static delay value for LVDS_RX Data.") parser.add_target_argument("--lvds-clk-delay", default=0, type=int, help="Static delay value for LVDS_RX PLL_CLKIN.") args = parser.parse_args() diff --git a/bench/serwb/test_serwb.py b/bench/serwb/test_serwb.py index 2959509..fb32486 100755 --- a/bench/serwb/test_serwb.py +++ b/bench/serwb/test_serwb.py @@ -40,11 +40,13 @@ def init_test(port): bus = RemoteClient(port=port) bus.open() - # Reset SerWB Master + # Reset SerWB Master. + # ------------------- print("Reseting SerWB Master...") bus.regs.serwb_master_phy_control_reset.write(1) - # Initialize SerWB Master + # Initialize SerWB Master. + # ------------------------ timeout = 4 print("Initializing SerWB Master...") while (bus.regs.serwb_master_phy_control_ready.read() == 0 and @@ -61,7 +63,8 @@ def init_test(port): else: print("Success.") - # Show Master Config + # Show Master Config. + # ------------------- print("Master config") print("-------------") if hasattr(bus.regs, "serwb_master_phy_control_delay"): @@ -71,12 +74,14 @@ def init_test(port): print(f"delay_max: {bus.regs.serwb_master_phy_control_delay_max.read()}") print(f"delay: {bus.regs.serwb_master_phy_control_delay.read()}") print(f"bitslip: {bus.regs.serwb_master_phy_control_shift.read()}") - print(f"phase: {bus.regs.serwb_master_phy_control_phase.read()}") + if hasattr(bus.regs, "serwb_master_phy_control_phase"): + print(f"phase: {bus.regs.serwb_master_phy_control_phase.read()}") print(f"ready: {bus.regs.serwb_master_phy_control_ready.read()}") print(f"error: {bus.regs.serwb_master_phy_control_error.read()}") print("") - # Show Slave Config + # Show Slave Config. + # ------------------ print("Slave config") print("------------") if hasattr(bus.regs, "serwb_slave_phy_control_delay"): @@ -86,7 +91,8 @@ def init_test(port): print(f"delay_max: {bus.regs.serwb_slave_phy_control_delay_max.read()}") print(f"delay: {bus.regs.serwb_slave_phy_control_delay.read()}") print(f"bitslip: {bus.regs.serwb_slave_phy_control_shift.read()}") - print(f"phase: {bus.regs.serwb_slave_phy_control_phase.read()}") + if hasattr(bus.regs, "serwb_slave_phy_control_phase"): + print(f"phase: {bus.regs.serwb_slave_phy_control_phase.read()}") print(f"ready: {bus.regs.serwb_slave_phy_control_ready.read()}") print(f"error: {bus.regs.serwb_slave_phy_control_error.read()}") diff --git a/bench/serwb/ti60_f225_dev_kit.py b/bench/serwb/ti60_f225_dev_kit.py index f377ceb..b320c0d 100755 --- a/bench/serwb/ti60_f225_dev_kit.py +++ b/bench/serwb/ti60_f225_dev_kit.py @@ -3,9 +3,9 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2023 MoTeC -# Copyright (c) 2023 Gwenhael Goavec-Merou -# Copyright (c) 2017-2023 Florent Kermarrec +# Copyright (c) 2023-2024 MoTeC +# Copyright (c) 2023-2024 Gwenhael Goavec-Merou +# Copyright (c) 2017-2024 Florent Kermarrec from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer @@ -65,10 +65,12 @@ def __init__(self, platform, sys_clk_freq, clk_ratio="1:1"): sys_clk_freq_div = {"1:1":1, "1:2":2, "1:4":4}[clk_ratio] # Clk/Rst. + # -------- clk25 = platform.request("clk25") rst_n = platform.request("user_btn", 0) - # PLL + # PLL. + # ---- self.pll = pll = TITANIUMPLL(platform) self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk25, 25e6) @@ -99,7 +101,8 @@ def __init__(self, platform, sys_clk_freq=300e6, clk_ratio="1:4", with_analyzer= ident = f"LiteICLink SerWB bench @ {int(sys_clk_freq/1e6):d}MHz on Efinix Titanium Ti60 F225 Dev Kit", ident_version = True, with_uart = False, - with_jtagbone = True) + with_jtagbone = True, + ) # SerWB ------------------------------------------------------------------------------------ # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected @@ -114,8 +117,9 @@ def __init__(self, platform, sys_clk_freq=300e6, clk_ratio="1:4", with_analyzer= # ------------------------------------------------------------------------------------------ # SerWB Master --------------------------------------------------------------------------- - # PHY - serwb_master_phy = SERWBPHY( + # PHY. + # ---- + self.serwb_master_phy = serwb_master_phy = SERWBPHY( device = self.platform.device, pads = self.platform.request("serwb_master"), mode = "master", @@ -123,42 +127,46 @@ def __init__(self, platform, sys_clk_freq=300e6, clk_ratio="1:4", with_analyzer= clk4x = "serwb_phy4x", clk_ratio = clk_ratio, ) - self.submodules.serwb_master_phy = serwb_master_phy - # Core - serwb_master_core = SERWBCore(serwb_master_phy, self.clk_freq, mode="slave", + # Core. + # ----- + self.serwb_master_core = serwb_master_core = SERWBCore( + phy = serwb_master_phy, + clk_freq = self.clk_freq, + mode = "slave", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8 + rx_buffer_depth = 8, ) - self.submodules += serwb_master_core # Connect as peripheral to main SoC. + # ---------------------------------- self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=1024)) # SerWB Slave ---------------------------------------------------------------------------- - # PHY - serwb_slave_phy = SERWBPHY( + # PHY. + # ---- + self.serwb_slave_phy = serwb_slave_phy = ClockDomainsRenamer("rx_sys")(SERWBPHY( device = self.platform.device, pads = self.platform.request("serwb_slave"), mode = "slave", clk_ratio = clk_ratio, - ) - serwb_slave_phy = ClockDomainsRenamer("rx_sys")(serwb_slave_phy) - self.submodules.serwb_slave_phy = serwb_slave_phy - - # Core - serwb_slave_core = SERWBCore(serwb_slave_phy, self.clk_freq, mode="master", + )) + + # Core. + # ----- + self.serwb_slave_core = serwb_slave_core = ClockDomainsRenamer("rx_sys")(SERWBCore( + phy = serwb_slave_phy, + clk_freq = self.clk_freq, + mode = "master", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8 - ) - serwb_slave_core = ClockDomainsRenamer("rx_sys")(serwb_slave_core) - self.submodules += serwb_slave_core + rx_buffer_depth = 8, + )) - # Wishbone SRAM - serwb_sram = ClockDomainsRenamer("rx_sys")(wishbone.SRAM(1024)) - self.submodules += serwb_sram + # Wishbone SRAM. + # -------------- + self.serwb_sram = serwb_sram = ClockDomainsRenamer("rx_sys")(wishbone.SRAM(1024)) self.comb += serwb_slave_core.bus.connect(serwb_sram.bus) # Analyzer --------------------------------------------------------------------------------- diff --git a/bench/serwb/trellisboard.py b/bench/serwb/trellisboard.py index c7f116f..f1899b1 100755 --- a/bench/serwb/trellisboard.py +++ b/bench/serwb/trellisboard.py @@ -32,7 +32,7 @@ # IOs ---------------------------------------------------------------------------------------------- serwb_io = [ - # PMOD loopback + # PMOD loopback. ("serwb_master", 0, Subsignal("clk", Pins("pmoda:0"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("pmoda:1"), IOStandard("LVCMOS33")), @@ -80,60 +80,69 @@ def __init__(self, platform, loopback=False, with_analyzer=False): # +--------+ +------+ +------+ +------+ # ------------------------------------------------------------------------------------------ - # Pads + # Pads. + # ----- if loopback: serwb_master_pads = Record([("tx", 1), ("rx", 1)]) serwb_slave_pads = Record([("tx", 1), ("rx", 1)]) - self.comb += serwb_slave_pads.rx.eq(serwb_master_pads.tx) - self.comb += serwb_master_pads.rx.eq(serwb_slave_pads.tx) + self.comb += [ + serwb_slave_pads.rx.eq(serwb_master_pads.tx), + serwb_master_pads.rx.eq(serwb_slave_pads.tx), + ] else: serwb_master_pads = platform.request("serwb_master") serwb_slave_pads = platform.request("serwb_slave") # SerWB Master ----------------------------------------------------------------------------- - # PHY - serwb_master_phy = SERWBPHY( + # PHY. + # ---- + self.serwb_master_phy = serwb_master_phy = SERWBPHY( device = platform.device, pads = serwb_master_pads, - mode = "master") - self.serwb_master_phy = serwb_master_phy + mode = "master", + ) - # Core - serwb_master_core = SERWBCore(serwb_master_phy, self.clk_freq, mode="slave", + # Core. + # ----- + self.serwb_master_core = serwb_master_core = SERWBCore(serwb_master_phy, self.clk_freq, mode="slave", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8) - self.submodules += serwb_master_core + rx_buffer_depth = 8, + ) # Connect as peripheral to main SoC. + # ---------------------------------- self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192)) # SerWB Slave ------------------------------------------------------------------------------ - # PHY - serwb_slave_phy = SERWBPHY( + # PHY. + # ---- + self.serwb_slave_phy = serwb_slave_phy = ClockDomainsRenamer("serwb")(SERWBPHY( device = platform.device, pads = serwb_slave_pads, - mode ="slave") + mode ="slave", + )) self.cd_serwb = ClockDomain() if hasattr(serwb_slave_phy.serdes, "clocking"): self.comb += self.cd_serwb.clk.eq(serwb_slave_phy.serdes.clocking.refclk) else: self.comb += self.cd_serwb.clk.eq(ClockSignal("sys")) self.specials += AsyncResetSynchronizer(self.cd_serwb, ResetSignal("sys")) - serwb_slave_phy = ClockDomainsRenamer("serwb")(serwb_slave_phy) - self.serwb_slave_phy = serwb_slave_phy - # Core - serwb_slave_core = SERWBCore(serwb_slave_phy, self.clk_freq, mode="master", + # Core. + # ----- + self.serwb_slave_core = serwb_slave_core = SERWBCore( + phy = serwb_slave_phy, + clk_freq = self.clk_freq, + mode = "master", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8) - serwb_slave_core = ClockDomainsRenamer("serwb")(serwb_slave_core) - self.submodules += serwb_slave_core + rx_buffer_depth = 8, + ) - # Wishbone SRAM - serwb_sram = ClockDomainsRenamer("serwb")(wishbone.SRAM(8192)) - self.submodules += serwb_sram + # Wishbone SRAM. + # -------------- + self.serwb_sram = serwb_sram = ClockDomainsRenamer("serwb")(wishbone.SRAM(8192)) self.comb += serwb_slave_core.bus.connect(serwb_sram.bus) # Leds ------------------------------------------------------------------------------------- @@ -170,11 +179,11 @@ def __init__(self, platform, loopback=False, with_analyzer=False): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on Trellisboard") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") - parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs)") - parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer") + parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on Trellisboard.") + parser.add_argument("--build", action="store_true", help="Build bitstream.") + parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM).") + parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs).") + parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer.") args = parser.parse_args() platform = trellisboard.Platform(toolchain="trellis") diff --git a/bench/serwb/ulx3s.py b/bench/serwb/ulx3s.py index f1abea5..7e46c27 100755 --- a/bench/serwb/ulx3s.py +++ b/bench/serwb/ulx3s.py @@ -79,60 +79,67 @@ def __init__(self, platform, loopback=False, with_analyzer=False): # +--------+ +------+ +------+ +------+ # ------------------------------------------------------------------------------------------ - # Pads + # Pads. + # ----- if loopback: serwb_master_pads = Record([("tx", 1), ("rx", 1)]) serwb_slave_pads = Record([("tx", 1), ("rx", 1)]) - self.comb += serwb_slave_pads.rx.eq(serwb_master_pads.tx) - self.comb += serwb_master_pads.rx.eq(serwb_slave_pads.tx) + self.comb += [ + serwb_slave_pads.rx.eq(serwb_master_pads.tx), + serwb_master_pads.rx.eq(serwb_slave_pads.tx), + ] else: serwb_master_pads = platform.request("serwb_master") serwb_slave_pads = platform.request("serwb_slave") # SerWB Master ----------------------------------------------------------------------------- - # PHY - serwb_master_phy = SERWBPHY( + # PHY. + # ---- + self.serwb_master_phy = serwb_master_phy = SERWBPHY( device = platform.device, pads = serwb_master_pads, mode = "master") - self.serwb_master_phy = serwb_master_phy - # Core - serwb_master_core = SERWBCore(serwb_master_phy, self.clk_freq, mode="slave", + # Core. + # ----- + self.serwb_master_core = serwb_master_core = SERWBCore(serwb_master_phy, self.clk_freq, mode="slave", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8) - self.submodules += serwb_master_core + rx_buffer_depth = 8, + ) # Connect as peripheral to main SoC. + # ---------------------------------- self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192)) # SerWB Slave ------------------------------------------------------------------------------ - # PHY - serwb_slave_phy = SERWBPHY( + # PHY. + # ---- + self.serwb_slave_phy = serwb_slave_phy = ClockDomainsRenamer("serwb")(SERWBPHY( device = platform.device, pads = serwb_slave_pads, - mode ="slave") + mode ="slave", + )) self.cd_serwb = ClockDomain() if hasattr(serwb_slave_phy.serdes, "clocking"): self.comb += self.cd_serwb.clk.eq(serwb_slave_phy.serdes.clocking.refclk) else: self.comb += self.cd_serwb.clk.eq(ClockSignal("sys")) self.specials += AsyncResetSynchronizer(self.cd_serwb, ResetSignal("sys")) - serwb_slave_phy = ClockDomainsRenamer("serwb")(serwb_slave_phy) - self.serwb_slave_phy = serwb_slave_phy - # Core - serwb_slave_core = SERWBCore(serwb_slave_phy, self.clk_freq, mode="master", + # Core. + # ----- + self.serwb_slave_core = serwb_slave_core = ClockDomainsRenamer("serwb")(SERWBCore( + phy = serwb_slave_phy, + clk_freq = self.clk_freq, + mode = "master", etherbone_buffer_depth = 1, tx_buffer_depth = 8, - rx_buffer_depth = 8) - serwb_slave_core = ClockDomainsRenamer("serwb")(serwb_slave_core) - self.submodules += serwb_slave_core + rx_buffer_depth = 8, + )) - # Wishbone SRAM - serwb_sram = ClockDomainsRenamer("serwb")(wishbone.SRAM(8192)) - self.submodules += serwb_sram + # Wishbone SRAM. + self.serwb_sram = serwb_sram = ClockDomainsRenamer("serwb")(wishbone.SRAM(8192)) self.comb += serwb_slave_core.bus.connect(serwb_sram.bus) # Leds ------------------------------------------------------------------------------------- @@ -169,11 +176,11 @@ def __init__(self, platform, loopback=False, with_analyzer=False): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on ULX3S") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") - parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs)") - parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer") + parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on ULX3S.") + parser.add_argument("--build", action="store_true", help="Build bitstream.") + parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM).") + parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs).") + parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer.") args = parser.parse_args() platform = radiona_ulx3s.Platform(toolchain="trellis")