From 7615c9159c5afa417a311987333ea07f3c9834ac Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Tue, 17 Dec 2024 23:28:55 +0000
Subject: [PATCH] soc/integration/soc: Fix CSRBridge Bus Width conversion

Wishbone2CSR and AXILite2CSR bridges are incapable for performing
bus width conversion, which means it's Bus slave port must have same
width as CSRs.

Use CSR width to create slave bus to allow width adaptar to be inserted
by add_slave. Also add relevant assertion.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 litex/soc/integration/soc.py                  | 5 +++--
 litex/soc/interconnect/axi/axi_lite_to_csr.py | 2 ++
 litex/soc/interconnect/wishbone.py            | 2 ++
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index e523a33d20..536f97ab5a 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1138,13 +1138,14 @@ def add_csr_bridge(self, name="csr", origin=None, register=False):
         }[self.bus.standard]
         csr_bridge_name = f"{name}_bridge"
         self.check_if_exists(csr_bridge_name)
+        data_width = self.csr.data_width
         csr_bridge = csr_bridge_cls(
             bus_bridge_cls(
                 address_width = self.bus.address_width,
-                data_width    = self.bus.data_width),
+                data_width    = data_width),
             bus_csr = csr_bus.Interface(
                 address_width = self.csr.address_width,
-                data_width    = self.csr.data_width),
+                data_width    = data_width),
             register = register)
         self.logger.info("CSR Bridge {} {}.".format(
             colorer(name, color="underline"),
diff --git a/litex/soc/interconnect/axi/axi_lite_to_csr.py b/litex/soc/interconnect/axi/axi_lite_to_csr.py
index d6ceb68c4b..f49822e9d0 100644
--- a/litex/soc/interconnect/axi/axi_lite_to_csr.py
+++ b/litex/soc/interconnect/axi/axi_lite_to_csr.py
@@ -29,6 +29,8 @@ def __init__(self, axi_lite=None, bus_csr=None, register=False):
         self.axi_lite = axi_lite
         self.csr      = bus_csr
 
+        assert axi_lite.data_width == bus_csr.data_width
+
         fsm, comb = axi_lite_to_simple(
             axi_lite   = self.axi_lite,
             port_adr   = self.csr.adr,
diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 37f190ce5a..da70fdc31e 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -588,6 +588,8 @@ def __init__(self, bus_wishbone=None, bus_csr=None, register=True):
             # If no Wishbone bus provided, create it with default parameters.
             self.wishbone = Interface()
 
+        assert self.wishbone.data_width == self.csr.data_width
+
         # # #
 
         wishbone_adr_shift = {