From 8a0d50b03e2cd3316d4217ba3553df33fbf75620 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Fri, 17 May 2024 09:46:23 +1000 Subject: [PATCH 1/3] tools/litex_json2dts_linux: add all soc sys_clk Adds clocks for a downstream iclink soc, for example when builder.add_json() has imported soc clocks. Node names are as per devicetree fixed-clock.yaml bindings. --- litex/tools/litex_json2dts_linux.py | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/litex/tools/litex_json2dts_linux.py b/litex/tools/litex_json2dts_linux.py index 94c7986cb7..140ea95755 100755 --- a/litex/tools/litex_json2dts_linux.py +++ b/litex/tools/litex_json2dts_linux.py @@ -118,13 +118,18 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic # Clocks ------------------------------------------------------------------------------------------ - dts += """ - sys_clk: pll {{ + for c in [c for c in d["constants"].keys() if c.endswith("config_clock_frequency")]: + name = c.removesuffix("config_clock_frequency") + "sys_clk" + dts += """ + {name}: clock-{freq} {{ compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <{sys_clk_freq}>; + clock-frequency = <{freq}>; }}; -""".format(sys_clk_freq=d["constants"]["config_clock_frequency"]) +""".format( + name=name, + freq=d["constants"][c], + ) # CPU ------------------------------------------------------------------------------------------ From ddc521b0338abfba390efe91a487c24384030f2d Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Tue, 21 May 2024 10:05:06 +1000 Subject: [PATCH 2/3] tools/litex_json2dts_linux: fix tlb-split This is also relevant to vexriscv_smp, not rocket specific. Fixes these dt-schema validation errors: cpus: cpu@0: 'tlb-split' is a dependency of 'd-tlb-size' from schema : http://devicetree.org/schemas/cpus.yaml# cpus: cpu@0: 'tlb-split' is a dependency of 'd-tlb-sets' from schema : http://devicetree.org/schemas/cpus.yaml# cpus: cpu@0: 'tlb-split' is a dependency of 'i-tlb-size' from schema : http://devicetree.org/schemas/cpus.yaml# cpus: cpu@0: 'tlb-split' is a dependency of 'i-tlb-sets' from schema : http://devicetree.org/schemas/cpus.yaml# --- litex/tools/litex_json2dts_linux.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/tools/litex_json2dts_linux.py b/litex/tools/litex_json2dts_linux.py index 140ea95755..d83df1a50f 100755 --- a/litex/tools/litex_json2dts_linux.py +++ b/litex/tools/litex_json2dts_linux.py @@ -161,6 +161,7 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic tlb_desc = "" if "config_cpu_dtlb_size" in d["constants"]: tlb_desc += """ + tlb-split; d-tlb-size = <{d_tlb_size}>; d-tlb-sets = <{d_tlb_ways}>; """.format( @@ -181,7 +182,6 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic next-level-cache = <&memory>; riscv,pmpgranularity = <4>; riscv,pmpregions = <8>; - tlb-split; """ else: extra_attr = "" From 5e0c3f0a04a1cf17a3f898db9b2382144cc52f4a Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Tue, 21 May 2024 10:37:42 +1000 Subject: [PATCH 3/3] tools/litex_json2dts_linux: add compatible, model Fixes these dt-schema validation errors: /: 'compatible' is a required property from schema $id: http://devicetree.org/schemas/root-node.yaml# /: 'model' is a required property from schema $id: http://devicetree.org/schemas/root-node.yaml# --- litex/soc/integration/soc.py | 1 + litex/soc/integration/soc_core.py | 1 + litex/tools/litex_json2dts_linux.py | 10 ++++++++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 7bcdfdd8a2..8fc806fa2e 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -944,6 +944,7 @@ def __init__(self, platform, sys_clk_freq, self.sys_clk_freq = int(sys_clk_freq) # Do conversion to int here to allow passing float to SoC. self.constants = {} self.csr_regions = {} + self.add_constant("platform", platform.name) # Set Top-Level to LiteXContext. LiteXContext.top = self diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 34a430bfca..14e3b53bed 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -247,6 +247,7 @@ def __init__(self, platform, clk_freq, # Add Identifier. if ident != "": self.add_identifier("identifier", identifier=ident, with_build_time=ident_version) + self.add_constant("identifier", ident) # Add UARTBone. if with_uartbone: diff --git a/litex/tools/litex_json2dts_linux.py b/litex/tools/litex_json2dts_linux.py index d83df1a50f..185b7613c3 100755 --- a/litex/tools/litex_json2dts_linux.py +++ b/litex/tools/litex_json2dts_linux.py @@ -55,14 +55,20 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic cpu_mmu = d["constants"].get("config_cpu_mmu", None) # Header --------------------------------------------------------------------------------------- + platform = d["constants"]["platform"] dts = """ /dts-v1/; -/ { +/ {{ + compatible = "litex,{platform}", "litex,soc"; + model = "{identifier}"; #address-cells = <1>; #size-cells = <1>; -""" +""".format( + platform=platform, + identifier=d["constants"].get("identifier", platform), + ) # Boot Arguments -------------------------------------------------------------------------------