diff --git a/softGlueApp/src/drvZynq.c b/softGlueApp/src/drvZynq.c
index d00a8d1..2bbe862 100644
--- a/softGlueApp/src/drvZynq.c
+++ b/softGlueApp/src/drvZynq.c
@@ -557,13 +557,13 @@ int initZynqSingleRegisterPort(const char *portName, const char *componentName)
 }
 
 /*
- * softGlueCalcSpecifiedRegisterAddress - For access to a single-register component by
+ * softGlueZCalcSpecifiedRegisterAddress - For access to a single-register component by
  * other than an EPICS record (for example, by an interrupt-service routine).
  * The AXI and word offset are specified as arguments, and we need
  * to translate that information into a memory mapped address, as calcRegister32Address()
  * would have done for an EPICS record.
  */
-epicsUInt32 *softGlueCalcSpecifiedRegisterAddress(int type, int addr)
+epicsUInt32 *softGlueZCalcSpecifiedRegisterAddress(int type, int addr)
 {
 	drvZynqPvt *pPvt;
 	epicsUInt8 *reg8;
diff --git a/softGlueApp/src/drvZynq.h b/softGlueApp/src/drvZynq.h
index fa230ae..ba1a808 100644
--- a/softGlueApp/src/drvZynq.h
+++ b/softGlueApp/src/drvZynq.h
@@ -43,4 +43,4 @@ int findUioAddr(const char *componentName, int map);
 int softGlueRegisterInterruptRoutine(epicsUInt32 risingMask, epicsUInt32 fallingMask,
 	void (*routine)(softGlueIntRoutineData *IRData), void *userPvt);
 
-epicsUInt32 *softGlueCalcSpecifiedRegisterAddress(int type, int addr);
+epicsUInt32 *softGlueZCalcSpecifiedRegisterAddress(int type, int addr);
diff --git a/softGlueApp/src/readSoftGlueCounter_ISR.c b/softGlueApp/src/readSoftGlueCounter_ISR.c
index e63312b..bab6eae 100644
--- a/softGlueApp/src/readSoftGlueCounter_ISR.c
+++ b/softGlueApp/src/readSoftGlueCounter_ISR.c
@@ -122,7 +122,7 @@ int readSoftGlueCounter_ISRPrepare(epicsUInt32 risingMask) {
 	/* Get the address of the COUNTS registers of eight counters. */
 	for (i=0; i<5; i++) {
 		/* The first arg specifies which AXI component: 0 for 8-bit I/O point register, 1 for 32-bit register */
-		rcISRData.addr[i] = softGlueCalcSpecifiedRegisterAddress(1, counterOffset[i]);
+		rcISRData.addr[i] = softGlueZCalcSpecifiedRegisterAddress(1, counterOffset[i]);
 		if (readSoftGlueCounter_ISRDebug) {
 			printf("readSoftGlueCounter_ISRPrepare: addr[%d]=%p\n", i, rcISRData.addr[i]);
 		}
diff --git a/softGlueApp/src/sampleCustomInterruptHandler.c b/softGlueApp/src/sampleCustomInterruptHandler.c
index b191a76..e24e20e 100644
--- a/softGlueApp/src/sampleCustomInterruptHandler.c
+++ b/softGlueApp/src/sampleCustomInterruptHandler.c
@@ -72,13 +72,13 @@ int sampleCustomInterruptPrepare(epicsUInt32 risingMask, epicsUInt32 fallingMask
 	 * The address 123 is from softGlue_FPGAContent.substitutions.
 	 * We want to write to bit 5.
 	 */
-	myISRData.addr = softGlueCalcSpecifiedRegisterAddress(0, 123);
+	myISRData.addr = softGlueZCalcSpecifiedRegisterAddress(0, 123);
 
 	/* Get the address of the divByN N register.
 	 * The address 38 is from softGlue_FPGARegisters.substitutions.
 	 * It's the DivByN-3_N register to which we want to write.
 	 */
-	//myISRData.addr = softGlueCalcSpecifiedRegisterAddress(1, 38);
+	//myISRData.addr = softGlueZCalcSpecifiedRegisterAddress(1, 38);
 
 	/* Tell softGlue to call sampleCustomInterruptRoutine() when its interrupt-service routine handles an interrupt
 	 * from the specified carrier, slot, sopcAddress (I/O register), and bit (mask).  This also