{"payload":{"header_redesign_enabled":false,"results":[{"id":"238153951","archived":false,"color":"#3572A5","followers":10,"has_funding_file":false,"hl_name":"erihsu/Sym-CTS","hl_trunc_description":"symmetric clock tree synthesis for NTV IC design","language":"Python","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":238153951,"name":"Sym-CTS","owner_id":31060229,"owner_login":"erihsu","updated_at":"2022-05-08T05:24:13.532Z","has_issues":true}},"sponsorable":false,"topics":["perl","cts","integrated-circuits","python37"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":69,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aerihsu%252FSym-CTS%2B%2Blanguage%253APython","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/erihsu/Sym-CTS/star":{"post":"nGyAWdbj3kZqGwnq9rUUkiX7A3qlPupVE5PqRi09g7ao93lLUOBz3KD_Np2rha5xvn1rOLzOD9psnhHTcTuCdQ"},"/erihsu/Sym-CTS/unstar":{"post":"F1cxQ5CAICwotCaB_T8wGcww05mVXZJSB_miSPR6c4GY3vu9G0r8gbKA_AQfoT1xLQfKKcamgEz1f1FlZZJ6bQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"D4AQKSW9-iMJd9i_U5eiXK0A5tnhxFEwKtqZaQpeonA3sTgnp4knwp1i_CNqp40nfMPZZ5Y-D_LR08hHAgR-8A"}}},"title":"Repository search results"}