v0.39.0

Feature

• Implement batch normed linear layer (9322f6f)

Fix

• Allow to set affine and bias equals false in translate function (b351284)
• Remove dequantize (c111022)

v0.38.0

Feature

• Add check that all variables are filled when saving a template (c988d2b)
• Add function to get all unfilled variables of a template (d635cb6)
• Write function of InMemoryFile and OnDiskFile now takes Template object (a867ea1)

Fix

• Remove broken lstm implementation (c524ca2)
• Add variable (229d452)
• Fix not inserted process name (dbabea0)

v0.37.2

Fix

• Try manual publishing (c8b6c35)

v0.34.0

Feature

• Make precomputed scalar functions use unified interface (6b59da5)
• Binary_arithmetics (54e38d5)

Fix

• Correct import paths (169f868)

v0.33.3

Fix

• Remove DualPort2ClockRam design (f9224c6)
• Set correct rom names (9570826)

Documentation

• Remove deprecated documentation (11b9945)

v0.33.2

Fix

• Small import fix (07d2e29)
• translation: Add missing rom files and calculate correct twos complement (f700409)
• translation: Add missing ROMs and set correct names in fp_linear1d template (ad4c6f0)
• Fix type annotation (8da1107)
• unit: Fix failing unittests that are using the linear1d layer and design (ff582e1)

v0.33.1

Fix

• Usage of lstm output in lstm_network impl (2e16141)
• Wrong fixed point config object used for linear layers (3626113)

v0.33.0

Feature

• Add rom design for saving weights (75862b7)

Fix

• Correctly pad rom memory (fe768d5)

v0.32.1

Fix

• Typo in test for lstm cell designs (2ffeaec)
• Set library for lstm_cell (2b3a565)

v0.32.0

Feature

• Add linear layer to lstm network (bccb50c)
• Add linear layer to lstm network (48982f0)
• translation: Add support for single buffered module to sequential (5402782)
• translation: Sequential layer with bufferless layers (d7cea69)
• Add data flow node, sink node and source node (9a511de)
• Introduce vhdl_design class (2431ba4)
• Add logic and logic vector signals (551f241)
• Add connectable base in/out signals (fea05ed)
• Introduce vhdl_design class (20566f6)
• Add logic and logic vector signals (1947baa)
• Add connectable base in/out signals (7ad67f9)

Fix

• translation: Correct values for x/y_address_width (c7af1af)
• Tests and remove type annotations leading to deps (75ed6cc)
• Typing (b0bfa39)
• Fix unit tests after major rebase (3b596e9)
• Type annotations for tracing module (da598a9)
• Fix incorrect vector signal initialization (3b23f7a)
• Fix incorrect vector signal initialization (3c68255)