diff --git a/esp-hal-common/src/analog/adc/esp32.rs b/esp-hal-common/src/analog/adc/esp32.rs index 976bcbb82af..a94f96541f3 100644 --- a/esp-hal-common/src/analog/adc/esp32.rs +++ b/esp-hal-common/src/analog/adc/esp32.rs @@ -4,7 +4,7 @@ use embedded_hal::adc::{Channel, OneShot}; use crate::{ analog::{ADC1, ADC2}, - pac::{RTCIO, SENS}, + peripherals::{RTCIO, SENS}, }; /// The sampling/readout resolution of the ADC diff --git a/esp-hal-common/src/analog/adc/riscv.rs b/esp-hal-common/src/analog/adc/riscv.rs index a21c8f8376b..6fa243e240f 100644 --- a/esp-hal-common/src/analog/adc/riscv.rs +++ b/esp-hal-common/src/analog/adc/riscv.rs @@ -6,7 +6,7 @@ use embedded_hal::adc::{Channel, OneShot}; use crate::analog::ADC2; use crate::{ analog::ADC1, - pac::APB_SARADC, + peripherals::APB_SARADC, system::{Peripheral, PeripheralClockControl}, }; diff --git a/esp-hal-common/src/analog/adc/xtensa.rs b/esp-hal-common/src/analog/adc/xtensa.rs index 0bf5e72cc72..8318cd53009 100644 --- a/esp-hal-common/src/analog/adc/xtensa.rs +++ b/esp-hal-common/src/analog/adc/xtensa.rs @@ -4,7 +4,7 @@ use embedded_hal::adc::{Channel, OneShot}; use crate::{ analog::{ADC1, ADC2}, - pac::{APB_SARADC, SENS}, + peripherals::{APB_SARADC, SENS}, }; /// The sampling/readout resolution of the ADC diff --git a/esp-hal-common/src/analog/dac.rs b/esp-hal-common/src/analog/dac.rs index 11b70509c16..893f0b1daed 100644 --- a/esp-hal-common/src/analog/dac.rs +++ b/esp-hal-common/src/analog/dac.rs @@ -1,4 +1,4 @@ -use crate::pac::{RTCIO, SENS}; +use crate::peripherals::{RTCIO, SENS}; pub trait DAC { fn write(&mut self, value: u8); diff --git a/esp-hal-common/src/analog/mod.rs b/esp-hal-common/src/analog/mod.rs index 0b4b7510ddd..2eae5dea76a 100644 --- a/esp-hal-common/src/analog/mod.rs +++ b/esp-hal-common/src/analog/mod.rs @@ -11,7 +11,7 @@ cfg_if::cfg_if! { if #[cfg(any(esp32, esp32s2, esp32s3))] { use core::marker::PhantomData; - use crate::pac::SENS; + use crate::peripherals::SENS; pub struct ADC1 { _private: PhantomData<()>, @@ -65,7 +65,7 @@ cfg_if::cfg_if! { if #[cfg(esp32c3)] { use core::marker::PhantomData; - use crate::pac::APB_SARADC; + use crate::peripherals::APB_SARADC; pub struct ADC1 { _private: PhantomData<()>, @@ -103,7 +103,7 @@ cfg_if::cfg_if! { if #[cfg(esp32c2)] { use core::marker::PhantomData; - use crate::pac::APB_SARADC; + use crate::peripherals::APB_SARADC; pub struct ADC1 { _private: PhantomData<()>, diff --git a/esp-hal-common/src/clocks_ll/esp32.rs b/esp-hal-common/src/clocks_ll/esp32.rs index 6f5ea116e73..2430e435933 100644 --- a/esp-hal-common/src/clocks_ll/esp32.rs +++ b/esp-hal-common/src/clocks_ll/esp32.rs @@ -39,8 +39,8 @@ const I2C_BBPLL_OC_DIV_7_0: u32 = 3; const I2C_BBPLL_OC_DCUR: u32 = 5; pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock) { - let efuse = unsafe { &*crate::pac::EFUSE::ptr() }; - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let efuse = unsafe { &*crate::peripherals::EFUSE::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; unsafe { let rtc_cntl_dbias_hp_volt: u32 = @@ -201,7 +201,7 @@ pub(crate) fn esp32_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock } pub(crate) fn esp32_rtc_bbpll_enable() { - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; unsafe { rtc_cntl.options0.modify(|_, w| { @@ -261,8 +261,8 @@ unsafe fn i2c_writereg_rtc(block: u32, block_hostid: u32, reg_add: u32, indata: } pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) { - let apb_cntl = unsafe { &*crate::pac::APB_CTRL::ptr() }; - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let apb_cntl = unsafe { &*crate::peripherals::APB_CTRL::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; unsafe { let value = (((freq.hz()) >> 12) & UINT16_MAX) | ((((freq.hz()) >> 12) & UINT16_MAX) << 16); @@ -292,9 +292,9 @@ pub(crate) fn esp32_rtc_update_to_xtal(freq: XtalClock, _div: u32) { } pub(crate) fn set_cpu_freq(cpu_freq_mhz: crate::clock::CpuClock) { - let efuse = unsafe { &*crate::pac::EFUSE::ptr() }; - let dport = unsafe { &*crate::pac::DPORT::ptr() }; - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let efuse = unsafe { &*crate::peripherals::EFUSE::ptr() }; + let dport = unsafe { &*crate::peripherals::DPORT::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; unsafe { const RTC_CNTL_DBIAS_1V25: u32 = 7; diff --git a/esp-hal-common/src/clocks_ll/esp32c2.rs b/esp-hal-common/src/clocks_ll/esp32c2.rs index b9288d713b7..bbe52641416 100644 --- a/esp-hal-common/src/clocks_ll/esp32c2.rs +++ b/esp-hal-common/src/clocks_ll/esp32c2.rs @@ -39,7 +39,7 @@ const I2C_MST_BBPLL_STOP_FORCE_HIGH: u32 = 1 << 2; const I2C_MST_BBPLL_STOP_FORCE_LOW: u32 = 1 << 3; pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllClock) { - let system = unsafe { &*crate::pac::SYSTEM::ptr() }; + let system = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { let div_ref: u32; @@ -112,7 +112,7 @@ pub(crate) fn esp32c2_rtc_bbpll_configure(xtal_freq: XtalClock, _pll_freq: PllCl } pub(crate) fn esp32c2_rtc_bbpll_enable() { - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; rtc_cntl.options0.modify(|_, w| { w.bb_i2c_force_pd() @@ -125,7 +125,7 @@ pub(crate) fn esp32c2_rtc_bbpll_enable() { } pub(crate) fn esp32c2_rtc_update_to_xtal(freq: XtalClock, _div: u32) { - let system_control = unsafe { &*crate::pac::SYSTEM::ptr() }; + let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { ets_update_cpu_frequency(freq.mhz()); @@ -148,7 +148,7 @@ pub(crate) fn esp32c2_rtc_update_to_xtal(freq: XtalClock, _div: u32) { } pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) { - let system_control = unsafe { &*crate::pac::SYSTEM::ptr() }; + let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { system_control @@ -165,7 +165,7 @@ pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) { } pub(crate) fn esp32c2_rtc_apb_freq_update(apb_freq: ApbClock) { - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; let value = ((apb_freq.hz() >> 12) & u16::MAX as u32) | (((apb_freq.hz() >> 12) & u16::MAX as u32) << 16); diff --git a/esp-hal-common/src/clocks_ll/esp32c3.rs b/esp-hal-common/src/clocks_ll/esp32c3.rs index f04de04a0d0..4e2cff076bc 100644 --- a/esp-hal-common/src/clocks_ll/esp32c3.rs +++ b/esp-hal-common/src/clocks_ll/esp32c3.rs @@ -43,7 +43,7 @@ const I2C_MST_BBPLL_STOP_FORCE_HIGH: u32 = 1 << 3; const I2C_MST_BBPLL_STOP_FORCE_LOW: u32 = 1 << 2; pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClock) { - let system = unsafe { &*crate::pac::SYSTEM::ptr() }; + let system = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { let div_ref: u32; @@ -173,7 +173,7 @@ pub(crate) fn esp32c3_rtc_bbpll_configure(xtal_freq: XtalClock, pll_freq: PllClo } pub(crate) fn esp32c3_rtc_bbpll_enable() { - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; rtc_cntl.options0.modify(|_, w| { w.bb_i2c_force_pd() @@ -186,7 +186,7 @@ pub(crate) fn esp32c3_rtc_bbpll_enable() { } pub(crate) fn esp32c3_rtc_update_to_xtal(freq: XtalClock, _div: u32) { - let system_control = unsafe { &*crate::pac::SYSTEM::ptr() }; + let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { ets_update_cpu_frequency(freq.mhz()); @@ -209,7 +209,7 @@ pub(crate) fn esp32c3_rtc_update_to_xtal(freq: XtalClock, _div: u32) { } pub(crate) fn esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) { - let system_control = unsafe { &*crate::pac::SYSTEM::ptr() }; + let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { system_control @@ -226,7 +226,7 @@ pub(crate) fn esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) { } pub(crate) fn esp32c3_rtc_apb_freq_update(apb_freq: ApbClock) { - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; let value = ((apb_freq.hz() >> 12) & u16::MAX as u32) | (((apb_freq.hz() >> 12) & u16::MAX as u32) << 16); diff --git a/esp-hal-common/src/clocks_ll/esp32s2.rs b/esp-hal-common/src/clocks_ll/esp32s2.rs index 284f898e876..b435e34a026 100644 --- a/esp-hal-common/src/clocks_ll/esp32s2.rs +++ b/esp-hal-common/src/clocks_ll/esp32s2.rs @@ -11,8 +11,8 @@ const DIG_DBIAS_80M_160M: u32 = RTC_CNTL_DBIAS_1V25; const DIG_DBIAS_240M: u32 = RTC_CNTL_DBIAS_1V25; pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) { - let system_control = unsafe { &*crate::pac::SYSTEM::PTR }; - let rtc_cntl = unsafe { &*crate::pac::RTC_CNTL::ptr() }; + let system_control = unsafe { &*crate::peripherals::SYSTEM::PTR }; + let rtc_cntl = unsafe { &*crate::peripherals::RTC_CNTL::ptr() }; unsafe { system_control diff --git a/esp-hal-common/src/clocks_ll/esp32s3.rs b/esp-hal-common/src/clocks_ll/esp32s3.rs index 45b33636e3c..d6f9c282d3e 100644 --- a/esp-hal-common/src/clocks_ll/esp32s3.rs +++ b/esp-hal-common/src/clocks_ll/esp32s3.rs @@ -1,7 +1,7 @@ use crate::clock::CpuClock; pub(crate) fn set_cpu_clock(cpu_clock_speed: CpuClock) { - let system_control = unsafe { &*crate::pac::SYSTEM::PTR }; + let system_control = unsafe { &*crate::peripherals::SYSTEM::PTR }; unsafe { system_control diff --git a/esp-hal-common/src/cpu_control/esp32.rs b/esp-hal-common/src/cpu_control/esp32.rs index 83c2831cdc1..717d7c0c8ea 100644 --- a/esp-hal-common/src/cpu_control/esp32.rs +++ b/esp-hal-common/src/cpu_control/esp32.rs @@ -33,7 +33,7 @@ pub struct CpuControl { } unsafe fn internal_park_core(core: Cpu) { - let rtc_control = crate::pac::RTC_CNTL::PTR; + let rtc_control = crate::peripherals::RTC_CNTL::PTR; let rtc_control = &*rtc_control; match core { @@ -70,7 +70,7 @@ impl CpuControl { /// Unpark the given core pub fn unpark_core(&mut self, core: Cpu) { - let rtc_control = crate::pac::RTC_CNTL::PTR; + let rtc_control = crate::peripherals::RTC_CNTL::PTR; let rtc_control = unsafe { &*rtc_control }; match core { @@ -94,7 +94,7 @@ impl CpuControl { } fn flush_cache(&mut self, core: Cpu) { - let dport_control = crate::pac::DPORT::PTR; + let dport_control = crate::peripherals::DPORT::PTR; let dport_control = unsafe { &*dport_control }; match core { @@ -139,7 +139,7 @@ impl CpuControl { fn enable_cache(&mut self, core: Cpu) { let spi0 = unsafe { &(*crate::peripherals::SPI0::ptr()) }; - let dport_control = crate::pac::DPORT::PTR; + let dport_control = crate::peripherals::DPORT::PTR; let dport_control = unsafe { &*dport_control }; match core { @@ -191,7 +191,7 @@ impl CpuControl { &mut self, entry: &mut (dyn FnMut() + Send), ) -> Result { - let dport_control = crate::pac::DPORT::PTR; + let dport_control = crate::peripherals::DPORT::PTR; let dport_control = unsafe { &*dport_control }; if !xtensa_lx::is_debugger_attached() diff --git a/esp-hal-common/src/cpu_control/esp32s3.rs b/esp-hal-common/src/cpu_control/esp32s3.rs index f542e3ed17c..4e46b3de192 100644 --- a/esp-hal-common/src/cpu_control/esp32s3.rs +++ b/esp-hal-common/src/cpu_control/esp32s3.rs @@ -33,7 +33,7 @@ pub struct CpuControl { } unsafe fn internal_park_core(core: Cpu) { - let rtc_control = crate::pac::RTC_CNTL::PTR; + let rtc_control = crate::peripherals::RTC_CNTL::PTR; let rtc_control = &*rtc_control; match core { @@ -70,7 +70,7 @@ impl CpuControl { /// Unpark the given core pub fn unpark_core(&mut self, core: Cpu) { - let rtc_control = crate::pac::RTC_CNTL::PTR; + let rtc_control = crate::peripherals::RTC_CNTL::PTR; let rtc_control = unsafe { &*rtc_control }; match core { @@ -126,7 +126,7 @@ impl CpuControl { &mut self, entry: &mut (dyn FnMut() + Send), ) -> Result { - let system_control = crate::pac::SYSTEM::PTR; + let system_control = crate::peripherals::SYSTEM::PTR; let system_control = unsafe { &*system_control }; if !xtensa_lx::is_debugger_attached() diff --git a/esp-hal-common/src/dma/gdma.rs b/esp-hal-common/src/dma/gdma.rs index 57fe18a734d..71d38d357a2 100644 --- a/esp-hal-common/src/dma/gdma.rs +++ b/esp-hal-common/src/dma/gdma.rs @@ -16,7 +16,7 @@ macro_rules! impl_channel { } fn set_out_burstmode(burst_mode: bool) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_,w| { w.out_data_burst_en().bit(burst_mode) @@ -25,7 +25,7 @@ macro_rules! impl_channel { } fn set_out_priority(priority: DmaPriority) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].write(|w| { w.tx_pri().variant(priority as u8) @@ -33,7 +33,7 @@ macro_rules! impl_channel { } fn clear_out_interrupts() { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] dma.[].write(|w| { @@ -73,20 +73,20 @@ macro_rules! impl_channel { } fn reset_out() { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| w.out_rst().set_bit()); dma.[].modify(|_, w| w.out_rst().clear_bit()); } fn set_out_descriptors(address: u32) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| unsafe { w.outlink_addr().bits(address) }); } fn has_out_descriptor_error() -> bool { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] let ret = dma.[].read().out_dscr_err().bit(); @@ -97,19 +97,19 @@ macro_rules! impl_channel { } fn set_out_peripheral(peripheral: u8) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| w.peri_out_sel().variant(peripheral)); } fn start_out() { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| w.outlink_start().set_bit()); } fn is_out_done() -> bool { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] let ret = dma.[].read().out_total_eof().bit(); @@ -120,12 +120,12 @@ macro_rules! impl_channel { } fn last_out_dscr_address() -> usize { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].read().out_eof_des_addr().bits() as usize } fn is_out_eof_interrupt_set() -> bool { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] let ret = dma.[].read().out_eof().bit(); @@ -136,7 +136,7 @@ macro_rules! impl_channel { } fn reset_out_eof_interrupt() { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] dma.[].write(|w| { @@ -152,7 +152,7 @@ macro_rules! impl_channel { } fn set_in_burstmode(burst_mode: bool) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_,w| { w.in_data_burst_en().bit(burst_mode).indscr_burst_en().bit(burst_mode) @@ -160,7 +160,7 @@ macro_rules! impl_channel { } fn set_in_priority(priority: DmaPriority) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].write(|w| { w.rx_pri().variant(priority as u8) @@ -168,7 +168,7 @@ macro_rules! impl_channel { } fn clear_in_interrupts() { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] dma.[].write(|w| { @@ -212,20 +212,20 @@ macro_rules! impl_channel { } fn reset_in() { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| w.in_rst().set_bit()); dma.[].modify(|_, w| w.in_rst().clear_bit()); } fn set_in_descriptors(address: u32) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| unsafe { w.inlink_addr().bits(address) }); } fn has_in_descriptor_error() -> bool { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] let ret = dma.[].read().in_dscr_err().bit(); @@ -236,19 +236,19 @@ macro_rules! impl_channel { } fn set_in_peripheral(peripheral: u8) { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| w.peri_in_sel().variant(peripheral)); } fn start_in() { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].modify(|_, w| w.inlink_start().set_bit()); } fn is_in_done() -> bool { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; #[cfg(not(esp32s3))] let ret = dma.[].read().in_suc_eof().bit(); @@ -259,7 +259,7 @@ macro_rules! impl_channel { } fn last_in_dscr_address() -> usize { - let dma = unsafe { &*crate::pac::DMA::PTR }; + let dma = unsafe { &*crate::peripherals::DMA::PTR }; dma.[].read().inlink_dscr_bf0().bits() as usize } } @@ -352,7 +352,7 @@ pub(crate) mod private { /// /// This offers the available DMA channels. pub struct Gdma { - _inner: crate::pac::DMA, + _inner: crate::peripherals::DMA, pub channel0: ChannelCreator0, #[cfg(not(esp32c2))] pub channel1: ChannelCreator1, @@ -367,7 +367,7 @@ pub struct Gdma { impl Gdma { /// Create a DMA instance. pub fn new( - dma: crate::pac::DMA, + dma: crate::peripherals::DMA, peripheral_clock_control: &mut PeripheralClockControl, ) -> Gdma { peripheral_clock_control.enable(Peripheral::Gdma); diff --git a/esp-hal-common/src/dma/pdma.rs b/esp-hal-common/src/dma/pdma.rs index 21798345bba..ed9c54f1375 100644 --- a/esp-hal-common/src/dma/pdma.rs +++ b/esp-hal-common/src/dma/pdma.rs @@ -15,7 +15,7 @@ macro_rules! ImplSpiChannel { // (only) on ESP32 we need to configure DPORT for the SPI DMA channels #[cfg(esp32)] { - let dport = unsafe { &*crate::pac::DPORT::PTR }; + let dport = unsafe { &*crate::peripherals::DPORT::PTR }; match $num { 2 => { @@ -34,7 +34,7 @@ macro_rules! ImplSpiChannel { } fn set_out_burstmode(burst_mode: bool) { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_conf .modify(|_, w| w.outdscr_burst_en().bit(burst_mode)); } @@ -42,7 +42,7 @@ macro_rules! ImplSpiChannel { fn set_out_priority(_priority: DmaPriority) {} fn clear_out_interrupts() { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_clr.write(|w| { w.out_done_int_clr() .set_bit() @@ -56,19 +56,19 @@ macro_rules! ImplSpiChannel { } fn reset_out() { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_conf.modify(|_, w| w.out_rst().set_bit()); spi.dma_conf.modify(|_, w| w.out_rst().clear_bit()); } fn set_out_descriptors(address: u32) { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_out_link .modify(|_, w| unsafe { w.outlink_addr().bits(address) }); } fn has_out_descriptor_error() -> bool { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_raw.read().outlink_dscr_error_int_raw().bit() } @@ -77,27 +77,27 @@ macro_rules! ImplSpiChannel { } fn start_out() { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_out_link.modify(|_, w| w.outlink_start().set_bit()); } fn is_out_done() -> bool { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_raw.read().out_done_int_raw().bit() } fn last_out_dscr_address() -> usize { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.out_eof_des_addr.read().dma_out_eof_des_addr().bits() as usize } fn is_out_eof_interrupt_set() -> bool { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_raw.read().out_eof_int_raw().bit() } fn reset_out_eof_interrupt() { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_clr.write(|w| { w.out_eof_int_clr() .set_bit() @@ -105,7 +105,7 @@ macro_rules! ImplSpiChannel { } fn set_in_burstmode(burst_mode: bool) { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_conf .modify(|_, w| w.indscr_burst_en().bit(burst_mode)); } @@ -113,7 +113,7 @@ macro_rules! ImplSpiChannel { fn set_in_priority(_priority: DmaPriority) {} fn clear_in_interrupts() { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_clr.write(|w| { w.in_done_int_clr() .set_bit() @@ -127,19 +127,19 @@ macro_rules! ImplSpiChannel { } fn reset_in() { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_conf.modify(|_, w| w.in_rst().set_bit()); spi.dma_conf.modify(|_, w| w.in_rst().clear_bit()); } fn set_in_descriptors(address: u32) { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_in_link .modify(|_, w| unsafe { w.inlink_addr().bits(address) }); } fn has_in_descriptor_error() -> bool { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_raw.read().inlink_dscr_error_int_raw().bit() } @@ -148,17 +148,17 @@ macro_rules! ImplSpiChannel { } fn start_in() { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_in_link.modify(|_, w| w.inlink_start().set_bit()); } fn is_in_done() -> bool { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.dma_int_raw.read().in_done_int_raw().bit() } fn last_in_dscr_address() -> usize { - let spi = unsafe { &*crate::pac::[]::PTR }; + let spi = unsafe { &*crate::peripherals::[]::PTR }; spi.inlink_dscr_bf0.read().dma_inlink_dscr_bf0().bits() as usize } } @@ -237,7 +237,7 @@ macro_rules! ImplI2sChannel { } fn set_out_burstmode(burst_mode: bool) { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.lc_conf .modify(|_, w| w.outdscr_burst_en().bit(burst_mode)); } @@ -245,7 +245,7 @@ macro_rules! ImplI2sChannel { fn set_out_priority(_priority: DmaPriority) {} fn clear_out_interrupts() { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_clr.write(|w| { w.out_done_int_clr() .set_bit() @@ -259,19 +259,19 @@ macro_rules! ImplI2sChannel { } fn reset_out() { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.lc_conf.modify(|_, w| w.out_rst().set_bit()); reg_block.lc_conf.modify(|_, w| w.out_rst().clear_bit()); } fn set_out_descriptors(address: u32) { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.out_link .modify(|_, w| unsafe { w.outlink_addr().bits(address) }); } fn has_out_descriptor_error() -> bool { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_raw.read().out_dscr_err_int_raw().bit() } @@ -280,27 +280,27 @@ macro_rules! ImplI2sChannel { } fn start_out() { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.out_link.modify(|_, w| w.outlink_start().set_bit()); } fn is_out_done() -> bool { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_raw.read().out_done_int_raw().bit() } fn last_out_dscr_address() -> usize { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.out_eof_des_addr.read().out_eof_des_addr().bits() as usize } fn is_out_eof_interrupt_set() -> bool { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_raw.read().out_eof_int_raw().bit() } fn reset_out_eof_interrupt() { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_clr.write(|w| { w.out_eof_int_clr() .set_bit() @@ -308,7 +308,7 @@ macro_rules! ImplI2sChannel { } fn set_in_burstmode(burst_mode: bool) { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.lc_conf .modify(|_, w| w.indscr_burst_en().bit(burst_mode)); } @@ -316,7 +316,7 @@ macro_rules! ImplI2sChannel { fn set_in_priority(_priority: DmaPriority) {} fn clear_in_interrupts() { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_clr.write(|w| { w.in_done_int_clr() .set_bit() @@ -330,19 +330,19 @@ macro_rules! ImplI2sChannel { } fn reset_in() { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.lc_conf.modify(|_, w| w.in_rst().set_bit()); reg_block.lc_conf.modify(|_, w| w.in_rst().clear_bit()); } fn set_in_descriptors(address: u32) { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.in_link .modify(|_, w| unsafe { w.inlink_addr().bits(address) }); } fn has_in_descriptor_error() -> bool { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_raw.read().in_dscr_err_int_raw().bit() } @@ -351,17 +351,17 @@ macro_rules! ImplI2sChannel { } fn start_in() { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.in_link.modify(|_, w| w.inlink_start().set_bit()); } fn is_in_done() -> bool { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.int_raw.read().in_done_int_raw().bit() } fn last_in_dscr_address() -> usize { - let reg_block = unsafe { &*crate::pac::[<$peripheral>]::PTR }; + let reg_block = unsafe { &*crate::peripherals::[<$peripheral>]::PTR }; reg_block.inlink_dscr_bf0.read().inlink_dscr_bf0().bits() as usize } } diff --git a/esp-hal-common/src/efuse/esp32.rs b/esp-hal-common/src/efuse/esp32.rs index 6c69b0d0de1..4461b9b09a1 100644 --- a/esp-hal-common/src/efuse/esp32.rs +++ b/esp-hal-common/src/efuse/esp32.rs @@ -2,7 +2,7 @@ use fugit::{HertzU32, RateExtU32}; -use crate::pac::EFUSE; +use crate::peripherals::EFUSE; pub struct Efuse; diff --git a/esp-hal-common/src/efuse/esp32c2.rs b/esp-hal-common/src/efuse/esp32c2.rs index 60a58eef19f..a0ca4d6f8fe 100644 --- a/esp-hal-common/src/efuse/esp32c2.rs +++ b/esp-hal-common/src/efuse/esp32c2.rs @@ -1,6 +1,6 @@ //! Reading of eFuses -use crate::pac::EFUSE; +use crate::peripherals::EFUSE; pub struct Efuse; diff --git a/esp-hal-common/src/efuse/esp32c3.rs b/esp-hal-common/src/efuse/esp32c3.rs index 039174d339e..81ae4ce5f84 100644 --- a/esp-hal-common/src/efuse/esp32c3.rs +++ b/esp-hal-common/src/efuse/esp32c3.rs @@ -1,6 +1,6 @@ //! Reading of eFuses -use crate::pac::EFUSE; +use crate::peripherals::EFUSE; pub struct Efuse; diff --git a/esp-hal-common/src/efuse/esp32s2.rs b/esp-hal-common/src/efuse/esp32s2.rs index 039174d339e..81ae4ce5f84 100644 --- a/esp-hal-common/src/efuse/esp32s2.rs +++ b/esp-hal-common/src/efuse/esp32s2.rs @@ -1,6 +1,6 @@ //! Reading of eFuses -use crate::pac::EFUSE; +use crate::peripherals::EFUSE; pub struct Efuse; diff --git a/esp-hal-common/src/efuse/esp32s3.rs b/esp-hal-common/src/efuse/esp32s3.rs index 039174d339e..81ae4ce5f84 100644 --- a/esp-hal-common/src/efuse/esp32s3.rs +++ b/esp-hal-common/src/efuse/esp32s3.rs @@ -1,6 +1,6 @@ //! Reading of eFuses -use crate::pac::EFUSE; +use crate::peripherals::EFUSE; pub struct Efuse; diff --git a/esp-hal-common/src/embassy/time_driver_systimer.rs b/esp-hal-common/src/embassy/time_driver_systimer.rs index 616ce8779a2..2bc2aee1427 100644 --- a/esp-hal-common/src/embassy/time_driver_systimer.rs +++ b/esp-hal-common/src/embassy/time_driver_systimer.rs @@ -57,9 +57,9 @@ impl EmbassyTimer { pub fn init(_clocks: &Clocks, _systimer: TimerType) { use crate::{interrupt, interrupt::Priority, macros::interrupt}; - interrupt::enable(pac::Interrupt::SYSTIMER_TARGET0, Priority::max()).unwrap(); - interrupt::enable(pac::Interrupt::SYSTIMER_TARGET1, Priority::max()).unwrap(); - interrupt::enable(pac::Interrupt::SYSTIMER_TARGET2, Priority::max()).unwrap(); + interrupt::enable(peripherals::Interrupt::SYSTIMER_TARGET0, Priority::max()).unwrap(); + interrupt::enable(peripherals::Interrupt::SYSTIMER_TARGET1, Priority::max()).unwrap(); + interrupt::enable(peripherals::Interrupt::SYSTIMER_TARGET2, Priority::max()).unwrap(); #[interrupt] fn SYSTIMER_TARGET0() { diff --git a/esp-hal-common/src/embassy/time_driver_timg.rs b/esp-hal-common/src/embassy/time_driver_timg.rs index 5462e62b9b7..2bc8f3f071c 100644 --- a/esp-hal-common/src/embassy/time_driver_timg.rs +++ b/esp-hal-common/src/embassy/time_driver_timg.rs @@ -1,7 +1,7 @@ use core::cell::RefCell; use critical_section::{CriticalSection, Mutex}; -use pac::TIMG0; +use peripherals::TIMG0; use super::AlarmState; use crate::{ @@ -60,7 +60,7 @@ impl EmbassyTimer { critical_section::with(|cs| DRIVER.timer.borrow_ref_mut(cs).replace(timer)); - interrupt::enable(pac::Interrupt::TG0_T0_LEVEL, Priority::max()).unwrap(); + interrupt::enable(peripherals::Interrupt::TG0_T0_LEVEL, Priority::max()).unwrap(); #[interrupt] fn TG0_T0_LEVEL() { diff --git a/esp-hal-common/src/gpio.rs b/esp-hal-common/src/gpio.rs index 77cad104536..412e5172ba8 100644 --- a/esp-hal-common/src/gpio.rs +++ b/esp-hal-common/src/gpio.rs @@ -22,7 +22,7 @@ use core::convert::Infallible; pub use crate::types::*; use crate::{ - pac::{GPIO, IO_MUX}, + peripherals::{GPIO, IO_MUX}, types::{ get_io_mux_reg, gpio_intr_enable, @@ -314,13 +314,13 @@ pub trait BankGpioRegisterAccess { fn write_output_clear(&self, word: u32); fn set_output_signal(&self, gpio_num: u8, signal: u32) { - let gpio = unsafe { &*crate::pac::GPIO::PTR }; + let gpio = unsafe { &*crate::peripherals::GPIO::PTR }; gpio.func_out_sel_cfg[gpio_num as usize] .modify(|_, w| unsafe { w.out_sel().bits(signal as OutputSignalType) }); } fn configure_out_sel(&self, gpio_num: u8, signal: u32, invert: bool, oen: bool, oen_inv: bool) { - let gpio = unsafe { &*crate::pac::GPIO::PTR }; + let gpio = unsafe { &*crate::peripherals::GPIO::PTR }; gpio.func_out_sel_cfg[gpio_num as usize].modify(|_, w| unsafe { w.out_sel() .bits(signal as OutputSignalType) @@ -334,7 +334,7 @@ pub trait BankGpioRegisterAccess { } fn set_signal_to_level(&self, signal: u32, high: bool) { - let gpio = unsafe { &*crate::pac::GPIO::PTR }; + let gpio = unsafe { &*crate::peripherals::GPIO::PTR }; gpio.func_in_sel_cfg[signal as usize].modify(|_, w| unsafe { w.sel() .set_bit() @@ -346,7 +346,7 @@ pub trait BankGpioRegisterAccess { } fn clear_func_in_sel(&self, signal: u32) { - let gpio = unsafe { &*crate::pac::GPIO::PTR }; + let gpio = unsafe { &*crate::peripherals::GPIO::PTR }; gpio.func_in_sel_cfg[signal as usize].modify(|_, w| w.sel().clear_bit()); } @@ -357,7 +357,7 @@ pub trait BankGpioRegisterAccess { int_type: u8, wake_up_from_light_sleep: bool, ) { - let gpio = unsafe { &*crate::pac::GPIO::PTR }; + let gpio = unsafe { &*crate::peripherals::GPIO::PTR }; gpio.pin[gpio_num as usize].modify(|_, w| unsafe { w.int_ena() .bits(int_ena as u8) @@ -369,7 +369,7 @@ pub trait BankGpioRegisterAccess { } fn set_open_drain(&self, gpio_num: u8, open_drain: bool) { - let gpio = unsafe { &*crate::pac::GPIO::PTR }; + let gpio = unsafe { &*crate::peripherals::GPIO::PTR }; gpio.pin[gpio_num as usize].modify(|_, w| w.pad_driver().bit(open_drain)); } } @@ -1358,7 +1358,7 @@ macro_rules! gpio { pub fn enable_iomux_clk_gate() { #[cfg(esp32s2)] { - use crate::pac::SENS; + use crate::peripherals::SENS; let sensors = unsafe { &*SENS::ptr() }; sensors .sar_io_mux_conf @@ -1379,7 +1379,7 @@ macro_rules! analog { )+ ) => { pub(crate) fn internal_into_analog(pin: u8) { - use crate::pac::RTCIO; + use crate::peripherals::RTCIO; let rtcio = unsafe{ &*RTCIO::ptr() }; $crate::gpio::enable_iomux_clk_gate(); @@ -1436,7 +1436,7 @@ macro_rules! analog { )+ ) => { pub(crate) fn internal_into_analog(pin: u8) { - use crate::pac::RTCIO; + use crate::peripherals::RTCIO; let rtcio = unsafe{ &*RTCIO::ptr() }; $crate::gpio::enable_iomux_clk_gate(); @@ -1492,8 +1492,8 @@ macro_rules! analog { $($pin_num:literal)+ ) => { pub(crate) fn internal_into_analog(pin: u8) { - use crate::pac::IO_MUX; - use crate::pac::GPIO; + use crate::peripherals::IO_MUX; + use crate::peripherals::GPIO; let io_mux = unsafe{ &*IO_MUX::PTR }; let gpio = unsafe{ &*GPIO::PTR }; diff --git a/esp-hal-common/src/gpio/esp32.rs b/esp-hal-common/src/gpio/esp32.rs index 2bf6a174402..34a436bd00b 100644 --- a/esp-hal-common/src/gpio/esp32.rs +++ b/esp-hal-common/src/gpio/esp32.rs @@ -2,7 +2,7 @@ use paste::paste; use crate::{ gpio::PhantomData, - pac::GPIO, + peripherals::GPIO, AlternateFunction, Bank0GpioRegisterAccess, Bank1GpioRegisterAccess, @@ -22,9 +22,9 @@ pub const ZERO_INPUT: u8 = 0x30; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function2; -pub(crate) fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 { +pub(crate) fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO0 { unsafe { - let iomux = &*crate::pac::IO_MUX::PTR; + let iomux = &*crate::peripherals::IO_MUX::PTR; match gpio_num { 0 => core::mem::transmute(&(iomux.gpio0)), @@ -569,7 +569,7 @@ pub enum OutputSignal { } pub(crate) fn errata36(pin_num: u8, pull_up: bool, pull_down: bool) { - use crate::pac::RTCIO; + use crate::peripherals::RTCIO; let rtcio = unsafe { &*RTCIO::PTR }; match pin_num { diff --git a/esp-hal-common/src/gpio/esp32c2.rs b/esp-hal-common/src/gpio/esp32c2.rs index 745572000e5..5f66baa1af3 100644 --- a/esp-hal-common/src/gpio/esp32c2.rs +++ b/esp-hal-common/src/gpio/esp32c2.rs @@ -2,7 +2,7 @@ use paste::paste; use crate::{ gpio::PhantomData, - pac::GPIO, + peripherals::GPIO, AlternateFunction, Bank0GpioRegisterAccess, GpioPin, @@ -20,8 +20,8 @@ pub const ZERO_INPUT: u8 = 0x1f; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; -pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO { - unsafe { &(&*crate::pac::IO_MUX::PTR).gpio[gpio_num as usize] } +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { + unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio[gpio_num as usize] } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal-common/src/gpio/esp32c3.rs b/esp-hal-common/src/gpio/esp32c3.rs index 93b84f249ad..bbb8e8d1b65 100644 --- a/esp-hal-common/src/gpio/esp32c3.rs +++ b/esp-hal-common/src/gpio/esp32c3.rs @@ -2,7 +2,7 @@ use paste::paste; use crate::{ gpio::PhantomData, - pac::GPIO, + peripherals::GPIO, AlternateFunction, Bank0GpioRegisterAccess, GpioPin, @@ -20,8 +20,8 @@ pub const ZERO_INPUT: u8 = 0x1f; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; -pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO { - unsafe { &(&*crate::pac::IO_MUX::PTR).gpio[gpio_num as usize] } +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { + unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio[gpio_num as usize] } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal-common/src/gpio/esp32s2.rs b/esp-hal-common/src/gpio/esp32s2.rs index 90fb87d1dac..5d70cd0d3d0 100644 --- a/esp-hal-common/src/gpio/esp32s2.rs +++ b/esp-hal-common/src/gpio/esp32s2.rs @@ -2,7 +2,7 @@ use paste::paste; use crate::{ gpio::PhantomData, - pac::GPIO, + peripherals::GPIO, AlternateFunction, Bank0GpioRegisterAccess, Bank1GpioRegisterAccess, @@ -21,9 +21,9 @@ pub const ZERO_INPUT: u8 = 0x3c; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; -pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 { +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO0 { unsafe { - let iomux = &*crate::pac::IO_MUX::PTR; + let iomux = &*crate::peripherals::IO_MUX::PTR; match gpio_num { 0 => core::mem::transmute(&(iomux.gpio0)), @@ -293,8 +293,8 @@ crate::gpio::gpio! { macro_rules! impl_get_rtc_pad { ($pad_name:ident) => { paste!{ - pub(crate) fn []() -> &'static crate::pac::rtcio::[< $pad_name:upper >] { - use crate::pac::RTCIO; + pub(crate) fn []() -> &'static crate::peripherals::rtcio::[< $pad_name:upper >] { + use crate::peripherals::RTCIO; let rtcio = unsafe{ &*RTCIO::ptr() }; &rtcio.$pad_name } @@ -305,8 +305,8 @@ macro_rules! impl_get_rtc_pad { macro_rules! impl_get_rtc_pad_indexed { ($pad_name:ident, $idx:literal) => { paste!{ - pub(crate) fn []() -> &'static crate::pac::rtcio::[< $pad_name:upper >] { - use crate::pac::RTCIO; + pub(crate) fn []() -> &'static crate::peripherals::rtcio::[< $pad_name:upper >] { + use crate::peripherals::RTCIO; let rtcio = unsafe{ &*RTCIO::ptr() }; &rtcio.$pad_name[$idx] } diff --git a/esp-hal-common/src/gpio/esp32s3.rs b/esp-hal-common/src/gpio/esp32s3.rs index 999d7dc0456..e51df318e41 100644 --- a/esp-hal-common/src/gpio/esp32s3.rs +++ b/esp-hal-common/src/gpio/esp32s3.rs @@ -2,7 +2,7 @@ use paste::paste; use crate::{ gpio::PhantomData, - pac::GPIO, + peripherals::GPIO, AlternateFunction, Bank0GpioRegisterAccess, Bank1GpioRegisterAccess, @@ -21,8 +21,8 @@ pub const ZERO_INPUT: u8 = 0x3c; pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1; -pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO { - unsafe { &(&*crate::pac::IO_MUX::PTR).gpio[gpio_num as usize] } +pub(crate) const fn get_io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO { + unsafe { &(&*crate::peripherals::IO_MUX::PTR).gpio[gpio_num as usize] } } pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { diff --git a/esp-hal-common/src/i2c.rs b/esp-hal-common/src/i2c.rs index 35d4d113b5c..153eec4d1d7 100644 --- a/esp-hal-common/src/i2c.rs +++ b/esp-hal-common/src/i2c.rs @@ -7,8 +7,8 @@ use fugit::HertzU32; use crate::{ clock::Clocks, gpio::{InputPin, OutputPin}, - pac::i2c0::{RegisterBlock, COMD}, peripheral::{Peripheral, PeripheralRef}, + peripherals::i2c0::{RegisterBlock, COMD}, system::PeripheralClockControl, types::{InputSignal, OutputSignal}, }; diff --git a/esp-hal-common/src/i2s.rs b/esp-hal-common/src/i2s.rs index af574c483b6..29ac9a7a415 100644 --- a/esp-hal-common/src/i2s.rs +++ b/esp-hal-common/src/i2s.rs @@ -909,15 +909,15 @@ mod private { use super::{DataFormat, I2sRx, I2sTx, Standard, I2S_LL_MCLK_DIVIDER_MAX}; #[cfg(any(esp32c3, esp32s2))] - use crate::pac::i2s::RegisterBlock; + use crate::peripherals::i2s::RegisterBlock; // on ESP32-S3 I2S1 doesn't support all features - use that to avoid using those features // by accident #[cfg(any(esp32s3, esp32))] - use crate::pac::i2s1::RegisterBlock; + use crate::peripherals::i2s1::RegisterBlock; #[cfg(any(esp32c3, esp32s2))] - use crate::pac::I2S; + use crate::peripherals::I2S; #[cfg(any(esp32s3, esp32))] - use crate::pac::I2S0 as I2S; + use crate::peripherals::I2S0 as I2S; use crate::{ clock::Clocks, dma::{ @@ -1016,14 +1016,14 @@ mod private { impl I2s0Instance for I2S {} #[cfg(esp32s3)] - impl Instance for crate::pac::I2S1 { + impl Instance for crate::peripherals::I2S1 { fn register_access(&self) -> I2sPeripheral1 { I2sPeripheral1 {} } } #[cfg(esp32s3)] - impl I2s1Instance for crate::pac::I2S1 {} + impl I2s1Instance for crate::peripherals::I2S1 {} pub trait Signals { fn get_peripheral(&self) -> Peripheral; @@ -1797,7 +1797,7 @@ mod private { #[cfg(any(esp32s3, esp32))] impl RegBlock for I2sPeripheral1 { fn register_block(&self) -> &'static RegisterBlock { - unsafe { core::mem::transmute(crate::pac::I2S1::PTR) } + unsafe { core::mem::transmute(crate::peripherals::I2S1::PTR) } } } diff --git a/esp-hal-common/src/interrupt/riscv.rs b/esp-hal-common/src/interrupt/riscv.rs index 12cd1bdc7ea..af39d44c408 100644 --- a/esp-hal-common/src/interrupt/riscv.rs +++ b/esp-hal-common/src/interrupt/riscv.rs @@ -13,7 +13,7 @@ use riscv::register::mcause; use crate::{ - pac::{self, Interrupt}, + peripherals::{self, Interrupt}, Cpu, }; @@ -139,7 +139,7 @@ impl Priority { pub unsafe fn map(_core: Cpu, interrupt: Interrupt, which: CpuInterrupt) { let interrupt_number = interrupt as isize; let cpu_interrupt_number = which as isize; - let intr = &*crate::pac::INTERRUPT_CORE0::PTR; + let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; let intr_map_base = intr.mac_intr_map.as_ptr(); intr_map_base .offset(interrupt_number) @@ -149,7 +149,7 @@ pub unsafe fn map(_core: Cpu, interrupt: Interrupt, which: CpuInterrupt) { /// Enable a CPU interrupt pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) { let cpu_interrupt_number = which as isize; - let intr = &*crate::pac::INTERRUPT_CORE0::PTR; + let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; intr.cpu_int_enable .modify(|r, w| w.bits((1 << cpu_interrupt_number) | r.bits())); } @@ -158,7 +158,7 @@ pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) { pub fn disable(_core: Cpu, interrupt: Interrupt) { unsafe { let interrupt_number = interrupt as isize; - let intr = &*crate::pac::INTERRUPT_CORE0::PTR; + let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; let intr_map_base = intr.mac_intr_map.as_ptr(); intr_map_base.offset(interrupt_number).write_volatile(0); } @@ -170,7 +170,7 @@ pub fn disable(_core: Cpu, interrupt: Interrupt) { /// interrupt handler will take care of clearing edge interrupt bits. pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) { unsafe { - let intr = &*crate::pac::INTERRUPT_CORE0::PTR; + let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; let cpu_interrupt_number = which as isize; let interrupt_type = match kind { @@ -191,7 +191,7 @@ pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) { /// default). Avoid changing the priority of interrupts 1 - 15 when interrupt /// vectoring is enabled. pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) { - let intr = &*crate::pac::INTERRUPT_CORE0::PTR; + let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; let cpu_interrupt_number = which as isize; let intr_prio_base = intr.cpu_int_pri_0.as_ptr(); @@ -205,7 +205,7 @@ pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) pub fn clear(_core: Cpu, which: CpuInterrupt) { unsafe { let cpu_interrupt_number = which as isize; - let intr = &*crate::pac::INTERRUPT_CORE0::PTR; + let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; intr.cpu_int_clear .write(|w| w.bits(1 << cpu_interrupt_number)); } @@ -215,11 +215,11 @@ pub fn clear(_core: Cpu, which: CpuInterrupt) { #[inline] pub fn get_status(_core: Cpu) -> u128 { unsafe { - ((*crate::pac::INTERRUPT_CORE0::PTR) + ((*crate::peripherals::INTERRUPT_CORE0::PTR) .intr_status_reg_0 .read() .bits() as u128) - | ((*crate::pac::INTERRUPT_CORE0::PTR) + | ((*crate::peripherals::INTERRUPT_CORE0::PTR) .intr_status_reg_1 .read() .bits() as u128) @@ -258,7 +258,7 @@ mod vectored { #[inline] fn get_configured_interrupts(_core: Cpu, mut status: u128) -> [u128; 16] { unsafe { - let intr = &*crate::pac::INTERRUPT_CORE0::PTR; + let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; let intr_map_base = intr.mac_intr_map.as_ptr(); let intr_prio_base = intr.cpu_int_pri_0.as_ptr(); @@ -318,7 +318,7 @@ mod vectored { let interrupt_nr = interrupt_mask.trailing_zeros(); // Interrupt::try_from can fail if interrupt already de-asserted: // silently ignore - if let Ok(interrupt) = pac::Interrupt::try_from(interrupt_nr as u8) { + if let Ok(interrupt) = peripherals::Interrupt::try_from(interrupt_nr as u8) { handle_interrupt(interrupt, context) } interrupt_mask &= !(1u128 << interrupt_nr); @@ -331,7 +331,7 @@ mod vectored { // defined in each hal fn EspDefaultHandler(interrupt: Interrupt); } - let handler = pac::__EXTERNAL_INTERRUPTS[interrupt as usize]._handler; + let handler = peripherals::__EXTERNAL_INTERRUPTS[interrupt as usize]._handler; if handler as *const _ == EspDefaultHandler as *const unsafe extern "C" fn() { EspDefaultHandler(interrupt); } else { diff --git a/esp-hal-common/src/interrupt/xtensa.rs b/esp-hal-common/src/interrupt/xtensa.rs index cd7e013b7d0..395f91dd0eb 100644 --- a/esp-hal-common/src/interrupt/xtensa.rs +++ b/esp-hal-common/src/interrupt/xtensa.rs @@ -2,7 +2,7 @@ use xtensa_lx::interrupt::{self, InterruptNumber}; use xtensa_lx_rt::exception::Context; use crate::{ - pac::{self, Interrupt}, + peripherals::{self, Interrupt}, Cpu, }; @@ -156,28 +156,30 @@ pub fn get_status(core: Cpu) -> u128 { } #[cfg(esp32)] -unsafe fn core0_interrupt_peripheral() -> *const crate::pac::dport::RegisterBlock { - crate::pac::DPORT::PTR +unsafe fn core0_interrupt_peripheral() -> *const crate::peripherals::dport::RegisterBlock { + crate::peripherals::DPORT::PTR } #[cfg(esp32)] -unsafe fn core1_interrupt_peripheral() -> *const crate::pac::dport::RegisterBlock { - crate::pac::DPORT::PTR +unsafe fn core1_interrupt_peripheral() -> *const crate::peripherals::dport::RegisterBlock { + crate::peripherals::DPORT::PTR } #[cfg(esp32s2)] -unsafe fn core0_interrupt_peripheral() -> *const crate::pac::interrupt::RegisterBlock { - crate::pac::INTERRUPT::PTR +unsafe fn core0_interrupt_peripheral() -> *const crate::peripherals::interrupt::RegisterBlock { + crate::peripherals::INTERRUPT::PTR } #[cfg(esp32s3)] -unsafe fn core0_interrupt_peripheral() -> *const crate::pac::interrupt_core0::RegisterBlock { - crate::pac::INTERRUPT_CORE0::PTR +unsafe fn core0_interrupt_peripheral() -> *const crate::peripherals::interrupt_core0::RegisterBlock +{ + crate::peripherals::INTERRUPT_CORE0::PTR } #[cfg(esp32s3)] -unsafe fn core1_interrupt_peripheral() -> *const crate::pac::interrupt_core1::RegisterBlock { - crate::pac::INTERRUPT_CORE1::PTR +unsafe fn core1_interrupt_peripheral() -> *const crate::peripherals::interrupt_core1::RegisterBlock +{ + crate::peripherals::INTERRUPT_CORE1::PTR } #[cfg(feature = "vectored")] @@ -405,7 +407,7 @@ mod vectored { let mut interrupt_mask = interrupt_mask & chip_specific::INTERRUPT_EDGE; loop { let interrupt_nr = interrupt_mask.trailing_zeros(); - if let Ok(interrupt) = pac::Interrupt::try_from(interrupt_nr as u16) { + if let Ok(interrupt) = peripherals::Interrupt::try_from(interrupt_nr as u16) { handle_interrupt(level, interrupt, save_frame) } else { break; @@ -422,7 +424,7 @@ mod vectored { // Interrupt::try_from can fail if interrupt already de-asserted: // silently ignore - if let Ok(interrupt) = pac::Interrupt::try_from(interrupt_nr as u16) { + if let Ok(interrupt) = peripherals::Interrupt::try_from(interrupt_nr as u16) { handle_interrupt(level, interrupt, save_frame); } } @@ -436,7 +438,7 @@ mod vectored { fn EspDefaultHandler(level: u32, interrupt: Interrupt); } - let handler = pac::__INTERRUPTS[interrupt.number() as usize]._handler; + let handler = peripherals::__INTERRUPTS[interrupt.number() as usize]._handler; if handler as *const _ == EspDefaultHandler as *const unsafe extern "C" fn() { EspDefaultHandler(level, interrupt); } else { @@ -452,7 +454,7 @@ mod vectored { 0b_0000_0000_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0000_0000_0011_1111_1100_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0000_0000_0000; #[inline] pub fn interrupt_is_edge(interrupt: Interrupt) -> bool { - use pac::Interrupt::*; + use peripherals::Interrupt::*; [ TG0_T0_EDGE, TG0_T1_EDGE, @@ -474,7 +476,7 @@ mod vectored { 0b_0000_0000_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0011_1011_1111_1100_0000_0000_0000_0000_0000_0000_0000__0000_0000_0000_0000_0000_0000_0000_0000; #[inline] pub fn interrupt_is_edge(interrupt: Interrupt) -> bool { - use pac::Interrupt::*; + use peripherals::Interrupt::*; [ TG0_T0_EDGE, TG0_T1_EDGE, diff --git a/esp-hal-common/src/ledc/channel.rs b/esp-hal-common/src/ledc/channel.rs index 788262383fc..bf50513477a 100644 --- a/esp-hal-common/src/ledc/channel.rs +++ b/esp-hal-common/src/ledc/channel.rs @@ -8,7 +8,7 @@ use super::{ }; use crate::{ gpio::{types::OutputSignal, OutputPin}, - pac::ledc::RegisterBlock, + peripherals::ledc::RegisterBlock, }; /// Channel errors @@ -82,7 +82,7 @@ pub struct Channel<'a, S: TimerSpeed, O: OutputPin> { impl<'a, S: TimerSpeed, O: OutputPin> Channel<'a, S, O> { /// Return a new channel pub fn new(number: Number, output_pin: O) -> Self { - let ledc = unsafe { &*crate::pac::LEDC::ptr() }; + let ledc = unsafe { &*crate::peripherals::LEDC::ptr() }; Channel { ledc, timer: None, diff --git a/esp-hal-common/src/ledc/mod.rs b/esp-hal-common/src/ledc/mod.rs index bcdacbd858a..5c03a11670b 100644 --- a/esp-hal-common/src/ledc/mod.rs +++ b/esp-hal-common/src/ledc/mod.rs @@ -71,7 +71,8 @@ use self::{ use crate::{ clock::Clocks, gpio::OutputPin, - system::{Peripheral, PeripheralClockControl}, + peripheral::{Peripheral, PeripheralRef}, + system::{Peripheral as PeripheralEnable, PeripheralClockControl}, }; pub mod channel; @@ -84,10 +85,10 @@ pub enum LSGlobalClkSource { } /// LEDC (LED PWM Controller) -pub struct LEDC<'a> { - _instance: crate::pac::LEDC, - ledc: &'a crate::pac::ledc::RegisterBlock, - clock_control_config: &'a Clocks, +pub struct LEDC<'d> { + _instance: PeripheralRef<'d, crate::peripherals::LEDC>, + ledc: &'d crate::peripherals::ledc::RegisterBlock, + clock_control_config: &'d Clocks, } #[cfg(esp32)] @@ -104,16 +105,17 @@ impl Speed for HighSpeed {} impl Speed for LowSpeed {} -impl<'a> LEDC<'a> { +impl<'d> LEDC<'d> { /// Return a new LEDC pub fn new( - _instance: crate::pac::LEDC, - clock_control_config: &'a Clocks, + _instance: impl Peripheral

+ 'd, + clock_control_config: &'d Clocks, system: &mut PeripheralClockControl, ) -> Self { - system.enable(Peripheral::Ledc); + crate::into_ref!(_instance); + system.enable(PeripheralEnable::Ledc); - let ledc = unsafe { &*crate::pac::LEDC::ptr() }; + let ledc = unsafe { &*crate::peripherals::LEDC::ptr() }; LEDC { _instance, ledc, diff --git a/esp-hal-common/src/ledc/timer.rs b/esp-hal-common/src/ledc/timer.rs index 7c8bc295bb7..1916b0eab6e 100644 --- a/esp-hal-common/src/ledc/timer.rs +++ b/esp-hal-common/src/ledc/timer.rs @@ -3,7 +3,7 @@ use fugit::HertzU32; #[cfg(esp32)] use super::HighSpeed; use super::{LowSpeed, Speed}; -use crate::{clock::Clocks, pac::ledc}; +use crate::{clock::Clocks, peripherals::ledc}; const LEDC_TIMER_DIV_NUM_MAX: u64 = 0x3FFFF; @@ -130,7 +130,7 @@ pub trait TimerHW { /// Timer struct pub struct Timer<'a, S: TimerSpeed> { - ledc: &'a crate::pac::ledc::RegisterBlock, + ledc: &'a crate::peripherals::ledc::RegisterBlock, clock_control_config: &'a Clocks, number: Number, duty: Option, diff --git a/esp-hal-common/src/lib.rs b/esp-hal-common/src/lib.rs index 614beea78e6..b8ccd5e79b9 100644 --- a/esp-hal-common/src/lib.rs +++ b/esp-hal-common/src/lib.rs @@ -21,17 +21,6 @@ #![no_std] #![cfg_attr(xtensa, feature(asm_experimental_arch))] -#[cfg(esp32)] -pub(crate) use esp32 as pac; -#[cfg(esp32c2)] -pub(crate) use esp32c2 as pac; -#[cfg(esp32c3)] -pub(crate) use esp32c3 as pac; -#[cfg(esp32s2)] -pub(crate) use esp32s2 as pac; -#[cfg(esp32s3)] -pub(crate) use esp32s3 as pac; - #[cfg_attr(esp32, path = "peripherals/esp32.rs")] #[cfg_attr(esp32c3, path = "peripherals/esp32c3.rs")] #[cfg_attr(esp32c2, path = "peripherals/esp32c2.rs")] diff --git a/esp-hal-common/src/mcpwm/mod.rs b/esp-hal-common/src/mcpwm/mod.rs index 03f379f4229..22dc91a45cf 100644 --- a/esp-hal-common/src/mcpwm/mod.rs +++ b/esp-hal-common/src/mcpwm/mod.rs @@ -234,21 +234,23 @@ impl<'a> PeripheralClockConfig<'a> { pub struct FrequencyError; /// A MCPWM peripheral -pub unsafe trait PwmPeripheral: Deref { +pub unsafe trait PwmPeripheral: + Deref +{ /// Enable peripheral fn enable(system: &mut PeripheralClockControl); /// Get a pointer to the peripheral RegisterBlock - fn block() -> *const crate::pac::pwm0::RegisterBlock; + fn block() -> *const crate::peripherals::pwm0::RegisterBlock; /// Get operator GPIO mux output signal fn output_signal() -> OutputSignal; } -unsafe impl PwmPeripheral for crate::pac::PWM0 { +unsafe impl PwmPeripheral for crate::peripherals::PWM0 { fn enable(system: &mut PeripheralClockControl) { system.enable(Peripheral::Mcpwm0) } - fn block() -> *const crate::pac::pwm0::RegisterBlock { + fn block() -> *const crate::peripherals::pwm0::RegisterBlock { Self::ptr() } @@ -265,12 +267,12 @@ unsafe impl PwmPeripheral for crate::pac::PWM0 { } } -unsafe impl PwmPeripheral for crate::pac::PWM1 { +unsafe impl PwmPeripheral for crate::peripherals::PWM1 { fn enable(system: &mut PeripheralClockControl) { system.enable(Peripheral::Mcpwm1) } - fn block() -> *const crate::pac::pwm0::RegisterBlock { + fn block() -> *const crate::peripherals::pwm0::RegisterBlock { Self::ptr() } diff --git a/esp-hal-common/src/mcpwm/timer.rs b/esp-hal-common/src/mcpwm/timer.rs index adbc71c880c..1ba4e89edde 100644 --- a/esp-hal-common/src/mcpwm/timer.rs +++ b/esp-hal-common/src/mcpwm/timer.rs @@ -141,7 +141,7 @@ impl Timer { } } - fn cfg0(&mut self) -> &crate::pac::pwm0::TIMER0_CFG0 { + fn cfg0(&mut self) -> &crate::peripherals::pwm0::TIMER0_CFG0 { // SAFETY: // We only grant access to our CFG0 register with the lifetime of &mut self let block = unsafe { &*PWM::block() }; @@ -158,7 +158,7 @@ impl Timer { } } } - fn cfg1(&mut self) -> &crate::pac::pwm0::TIMER0_CFG1 { + fn cfg1(&mut self) -> &crate::peripherals::pwm0::TIMER0_CFG1 { // SAFETY: // We only grant access to our CFG1 register with the lifetime of &mut self let block = unsafe { &*PWM::block() }; diff --git a/esp-hal-common/src/otg_fs.rs b/esp-hal-common/src/otg_fs.rs index de097d48744..6cb6541ce1d 100644 --- a/esp-hal-common/src/otg_fs.rs +++ b/esp-hal-common/src/otg_fs.rs @@ -24,7 +24,7 @@ where P: UsbDp + Send + Sync, M: UsbDm + Send + Sync, { - _usb0: pac::USB0, + _usb0: peripherals::USB0, _usb_sel: S, _usb_dp: P, _usb_dm: M, @@ -37,7 +37,7 @@ where M: UsbDm + Send + Sync, { pub fn new( - usb0: pac::USB0, + usb0: peripherals::USB0, usb_sel: S, usb_dp: P, usb_dm: M, @@ -67,7 +67,7 @@ where P: UsbDp + Send + Sync, M: UsbDm + Send + Sync, { - const REGISTERS: *const () = pac::USB0::ptr() as *const (); + const REGISTERS: *const () = peripherals::USB0::ptr() as *const (); const HIGH_SPEED: bool = false; const FIFO_DEPTH_WORDS: usize = 256; @@ -75,7 +75,7 @@ where fn enable() { unsafe { - let usb_wrap = &*pac::USB_WRAP::PTR; + let usb_wrap = &*peripherals::USB_WRAP::PTR; usb_wrap.otg_conf.modify(|_, w| { w.usb_pad_enable() .set_bit() @@ -91,7 +91,7 @@ where #[cfg(esp32s3)] { - let rtc = &*pac::RTC_CNTL::PTR; + let rtc = &*peripherals::RTC_CNTL::PTR; rtc.usb_conf .modify(|_, w| w.sw_hw_usb_phy_sel().set_bit().sw_usb_phy_sel().set_bit()); } diff --git a/esp-hal-common/src/peripherals/esp32.rs b/esp-hal-common/src/peripherals/esp32.rs index b2799e750ef..200fa72ff48 100644 --- a/esp-hal-common/src/peripherals/esp32.rs +++ b/esp-hal-common/src/peripherals/esp32.rs @@ -1,6 +1,9 @@ +use esp32 as pac; +// We need to export this for users to use pub use pac::Interrupt; -use crate::pac; // We need to export this for users to use +// We need to export this in the hal for the drivers to use +pub(crate) use self::peripherals::*; crate::peripherals! { AES, @@ -63,5 +66,6 @@ mod peripherals { UART1, UART2, DPORT, + LEDC, } } diff --git a/esp-hal-common/src/peripherals/esp32c2.rs b/esp-hal-common/src/peripherals/esp32c2.rs index 94e0737c36b..8024cc705fd 100644 --- a/esp-hal-common/src/peripherals/esp32c2.rs +++ b/esp-hal-common/src/peripherals/esp32c2.rs @@ -1,6 +1,9 @@ +use esp32c2 as pac; +// We need to export this for users to use pub use pac::Interrupt; -use crate::pac; // We need to export this for users to use +// We need to export this in the hal for the drivers to use +pub(crate) use self::peripherals::*; crate::peripherals! { APB_CTRL, @@ -43,5 +46,6 @@ mod peripherals { UART0, UART1, SYSTEM, + LEDC, } } diff --git a/esp-hal-common/src/peripherals/esp32c3.rs b/esp-hal-common/src/peripherals/esp32c3.rs index dda1177c07b..2239125e1d1 100644 --- a/esp-hal-common/src/peripherals/esp32c3.rs +++ b/esp-hal-common/src/peripherals/esp32c3.rs @@ -1,6 +1,9 @@ +use esp32c3 as pac; +// We need to export this for users to use pub use pac::Interrupt; -use crate::pac; // We need to export this for users to use +// We need to export this in the hal for the drivers to use +pub(crate) use self::peripherals::*; crate::peripherals! { AES, @@ -55,5 +58,6 @@ mod peripherals { UART1, USB_DEVICE, SYSTEM, + LEDC, } } diff --git a/esp-hal-common/src/peripherals/esp32s2.rs b/esp-hal-common/src/peripherals/esp32s2.rs index e39317f61a4..98ec35ac42a 100644 --- a/esp-hal-common/src/peripherals/esp32s2.rs +++ b/esp-hal-common/src/peripherals/esp32s2.rs @@ -1,6 +1,9 @@ +use esp32s2 as pac; +// We need to export this for users to use pub use pac::Interrupt; -use crate::pac; // We need to export this for users to use +// We need to export this in the hal for the drivers to use +pub(crate) use self::peripherals::*; crate::peripherals! { AES, @@ -62,5 +65,6 @@ mod peripherals { UART0, UART1, SYSTEM, + LEDC, } } diff --git a/esp-hal-common/src/peripherals/esp32s3.rs b/esp-hal-common/src/peripherals/esp32s3.rs index 9f5e10b86be..3ade2533058 100644 --- a/esp-hal-common/src/peripherals/esp32s3.rs +++ b/esp-hal-common/src/peripherals/esp32s3.rs @@ -1,6 +1,9 @@ +use esp32c3 as pac; +// We need to export this for users to use pub use pac::Interrupt; -use crate::pac; // We need to export this for users to use +// We need to export this in the hal for the drivers to use +pub(crate) use self::peripherals::*; crate::peripherals! { AES, @@ -74,5 +77,6 @@ mod peripherals { UART2, USB_DEVICE, SYSTEM, + LEDC, } } diff --git a/esp-hal-common/src/pulse_control.rs b/esp-hal-common/src/pulse_control.rs index c36bfc769e0..5775aaa7897 100644 --- a/esp-hal-common/src/pulse_control.rs +++ b/esp-hal-common/src/pulse_control.rs @@ -85,7 +85,7 @@ pub use paste::paste; use crate::{ gpio::{types::OutputSignal, OutputPin}, - pac::RMT, + peripherals::RMT, system::PeripheralClockControl, }; diff --git a/esp-hal-common/src/rtc/esp32.rs b/esp-hal-common/src/rtc/esp32.rs index 9459ec63602..d907ea0fe4f 100644 --- a/esp-hal-common/src/rtc/esp32.rs +++ b/esp-hal-common/src/rtc/esp32.rs @@ -1,6 +1,6 @@ use crate::{ clock::XtalClock, - pac::RTC_CNTL, + peripherals::RTC_CNTL, rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock}, }; diff --git a/esp-hal-common/src/rtc/esp32c2.rs b/esp-hal-common/src/rtc/esp32c2.rs index c31a85a8ddc..96db85ba0d2 100644 --- a/esp-hal-common/src/rtc/esp32c2.rs +++ b/esp-hal-common/src/rtc/esp32c2.rs @@ -2,7 +2,7 @@ use paste::paste; use crate::{ clock::XtalClock, - pac::{APB_CTRL, EXTMEM, RTC_CNTL, SPI0, SPI1, SYSTEM}, + peripherals::{APB_CTRL, EXTMEM, RTC_CNTL, SPI0, SPI1, SYSTEM}, regi2c_write_mask, rom::regi2c_ctrl_write_reg_mask, rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock}, diff --git a/esp-hal-common/src/rtc/esp32c3.rs b/esp-hal-common/src/rtc/esp32c3.rs index c4a8201255f..6b8d7abfb56 100644 --- a/esp-hal-common/src/rtc/esp32c3.rs +++ b/esp-hal-common/src/rtc/esp32c3.rs @@ -2,7 +2,7 @@ use paste::paste; use crate::{ clock::XtalClock, - pac::{APB_CTRL, EXTMEM, RTC_CNTL, SPI0, SPI1, SYSTEM}, + peripherals::{APB_CTRL, EXTMEM, RTC_CNTL, SPI0, SPI1, SYSTEM}, regi2c_write_mask, rom::regi2c_ctrl_write_reg_mask, rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock}, diff --git a/esp-hal-common/src/rtc/esp32s2.rs b/esp-hal-common/src/rtc/esp32s2.rs index 9459ec63602..d907ea0fe4f 100644 --- a/esp-hal-common/src/rtc/esp32s2.rs +++ b/esp-hal-common/src/rtc/esp32s2.rs @@ -1,6 +1,6 @@ use crate::{ clock::XtalClock, - pac::RTC_CNTL, + peripherals::RTC_CNTL, rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock}, }; diff --git a/esp-hal-common/src/rtc/esp32s3.rs b/esp-hal-common/src/rtc/esp32s3.rs index 9459ec63602..d907ea0fe4f 100644 --- a/esp-hal-common/src/rtc/esp32s3.rs +++ b/esp-hal-common/src/rtc/esp32s3.rs @@ -1,6 +1,6 @@ use crate::{ clock::XtalClock, - pac::RTC_CNTL, + peripherals::RTC_CNTL, rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock}, }; diff --git a/esp-hal-common/src/rtc_cntl.rs b/esp-hal-common/src/rtc_cntl.rs index e60cca86ec2..82dfb2b7046 100644 --- a/esp-hal-common/src/rtc_cntl.rs +++ b/esp-hal-common/src/rtc_cntl.rs @@ -5,7 +5,7 @@ use fugit::{HertzU32, MicrosDurationU64}; use crate::efuse::Efuse; use crate::{ clock::{Clock, XtalClock}, - pac::{RTC_CNTL, TIMG0}, + peripherals::{RTC_CNTL, TIMG0}, rom::esp_rom_delay_us, }; diff --git a/esp-hal-common/src/sha.rs b/esp-hal-common/src/sha.rs index 6a5f0cdcf80..7b967692bf2 100644 --- a/esp-hal-common/src/sha.rs +++ b/esp-hal-common/src/sha.rs @@ -1,6 +1,6 @@ use core::convert::Infallible; -use crate::pac::SHA; +use crate::peripherals::SHA; // All the hash algorithms introduced in FIPS PUB 180-4 Spec. // – SHA-1 diff --git a/esp-hal-common/src/spi.rs b/esp-hal-common/src/spi.rs index e476eef36b2..36c16d29e4a 100644 --- a/esp-hal-common/src/spi.rs +++ b/esp-hal-common/src/spi.rs @@ -57,8 +57,8 @@ use crate::{ DmaError, DmaPeripheral, }, - pac::spi2::RegisterBlock, peripheral::{Peripheral, PeripheralRef}, + peripherals::spi2::RegisterBlock, system::PeripheralClockControl, types::{InputSignal, OutputSignal}, InputPin, diff --git a/esp-hal-common/src/systimer.rs b/esp-hal-common/src/systimer.rs index c310b13800a..09c23bf557f 100644 --- a/esp-hal-common/src/systimer.rs +++ b/esp-hal-common/src/systimer.rs @@ -3,16 +3,16 @@ use core::{intrinsics::transmute, marker::PhantomData}; use fugit::MillisDurationU32; use crate::{ - pac::{ + peripheral::{Peripheral, PeripheralRef}, + peripherals::{ generic::Reg, systimer::{ target0_conf::TARGET0_CONF_SPEC, target0_hi::TARGET0_HI_SPEC, target0_lo::TARGET0_LO_SPEC, }, + SYSTIMER, }, - peripheral::{Peripheral, PeripheralRef}, - peripherals::SYSTIMER, }; // TODO this only handles unit0 of the systimer diff --git a/esp-hal-common/src/timer.rs b/esp-hal-common/src/timer.rs index 6eafb22f403..490e390df25 100644 --- a/esp-hal-common/src/timer.rs +++ b/esp-hal-common/src/timer.rs @@ -13,10 +13,10 @@ use fugit::{HertzU32, MicrosDurationU64}; use void::Void; #[cfg(timg1)] -use crate::pac::TIMG1; +use crate::peripherals::TIMG1; use crate::{ clock::Clocks, - pac::{timg0::RegisterBlock, TIMG0}, + peripherals::{timg0::RegisterBlock, TIMG0}, }; /// Custom timer error type @@ -46,7 +46,7 @@ pub trait TimerGroupInstance { impl TimerGroupInstance for TIMG0 { #[inline(always)] fn register_block() -> *const RegisterBlock { - crate::pac::TIMG0::PTR + crate::peripherals::TIMG0::PTR } } @@ -54,7 +54,7 @@ impl TimerGroupInstance for TIMG0 { impl TimerGroupInstance for TIMG1 { #[inline(always)] fn register_block() -> *const RegisterBlock { - crate::pac::TIMG1::PTR + crate::peripherals::TIMG1::PTR } } diff --git a/esp-hal-common/src/uart.rs b/esp-hal-common/src/uart.rs index 7e90580710c..5848430deef 100644 --- a/esp-hal-common/src/uart.rs +++ b/esp-hal-common/src/uart.rs @@ -2,12 +2,15 @@ use self::config::Config; #[cfg(uart2)] -use crate::pac::UART2; +use crate::peripherals::UART2; use crate::{ clock::Clocks, - pac::uart0::{fifo::FIFO_SPEC, RegisterBlock}, peripheral::{Peripheral, PeripheralRef}, - peripherals::{UART0, UART1}, + peripherals::{ + uart0::{fifo::FIFO_SPEC, RegisterBlock}, + UART0, + UART1, + }, types::{InputSignal, OutputSignal}, InputPin, OutputPin, @@ -477,7 +480,7 @@ where if self.uart.get_rx_fifo_count() > 0 { let value = unsafe { let fifo = (self.uart.register_block().fifo.as_ptr() as *mut u8).offset(offset) - as *mut crate::pac::generic::Reg; + as *mut crate::peripherals::generic::Reg; (*fifo).read().rxfifo_rd_byte().bits() }; diff --git a/esp-hal-common/src/usb_serial_jtag.rs b/esp-hal-common/src/usb_serial_jtag.rs index fbe630a197f..29cb1af04de 100644 --- a/esp-hal-common/src/usb_serial_jtag.rs +++ b/esp-hal-common/src/usb_serial_jtag.rs @@ -1,8 +1,8 @@ use core::convert::Infallible; use crate::{ - pac::{usb_device::RegisterBlock, USB_DEVICE}, peripheral::{Peripheral, PeripheralRef}, + peripherals::{usb_device::RegisterBlock, USB_DEVICE}, }; pub struct UsbSerialJtag<'d, T> {