diff --git a/esp-hal-common/Cargo.toml b/esp-hal-common/Cargo.toml
index f9ded3cf578..e841324c9d1 100644
--- a/esp-hal-common/Cargo.toml
+++ b/esp-hal-common/Cargo.toml
@@ -66,6 +66,9 @@ esp32c3 = ["esp32c3/rt", "riscv", "procmacros/esp32c3"]
 esp32s2 = ["esp32s2/rt", "xtensa", "xtensa-lx/esp32s2", "xtensa-lx-rt/esp32s2",             "esp-synopsys-usb-otg", "usb-device", "procmacros/esp32s2"]
 esp32s3 = ["esp32s3/rt", "xtensa", "xtensa-lx/esp32s3", "xtensa-lx-rt/esp32s3", "lock_api", "esp-synopsys-usb-otg", "usb-device", "procmacros/esp32s3"]
 
+esp32_40mhz = []
+esp32_26mhz = []
+
 esp32c2_40mhz = []
 esp32c2_26mhz = []
 
diff --git a/esp-hal-common/build.rs b/esp-hal-common/build.rs
index e658154131b..957593cff82 100644
--- a/esp-hal-common/build.rs
+++ b/esp-hal-common/build.rs
@@ -12,6 +12,9 @@ fn main() {
         n => panic!("Exactly 1 chip must be enabled via its Cargo feature, {n} provided"),
     }
 
+    if cfg!(feature = "esp32") && cfg!(feature = "esp32_40mhz") && cfg!(feature = "esp32_26mhz") {
+        panic!("Only one xtal speed feature can be selected");
+    }
     if cfg!(feature = "esp32c2")
         && cfg!(feature = "esp32c2_40mhz")
         && cfg!(feature = "esp32c2_26mhz")
diff --git a/esp-hal-common/src/clock/mod.rs b/esp-hal-common/src/clock/mod.rs
index 6285aad9eaa..fa8318e9ac5 100644
--- a/esp-hal-common/src/clock/mod.rs
+++ b/esp-hal-common/src/clock/mod.rs
@@ -185,7 +185,8 @@ impl<'d> ClockControl<'d> {
     pub fn boot_defaults(
         clock_control: impl Peripheral<P = SystemClockControl> + 'd,
     ) -> ClockControl<'d> {
-        ClockControl {
+        #[cfg(feature = "esp32_40mhz")]
+        return ClockControl {
             _private: clock_control.into_ref(),
             desired_rates: RawClocks {
                 cpu_clock: HertzU32::MHz(80),
@@ -194,7 +195,19 @@ impl<'d> ClockControl<'d> {
                 i2c_clock: HertzU32::MHz(80),
                 pwm_clock: HertzU32::MHz(160),
             },
-        }
+        };
+
+        #[cfg(feature = "esp32_26mhz")]
+        return ClockControl {
+            _private: clock_control.into_ref(),
+            desired_rates: RawClocks {
+                cpu_clock: HertzU32::MHz(80),
+                apb_clock: HertzU32::MHz(80),
+                xtal_clock: HertzU32::MHz(26),
+                i2c_clock: HertzU32::MHz(80),
+                pwm_clock: HertzU32::MHz(160),
+            },
+        };
     }
 
     /// Configure the CPU clock speed.
@@ -205,7 +218,10 @@ impl<'d> ClockControl<'d> {
     ) -> ClockControl<'d> {
         // like NuttX use 40M hardcoded - if it turns out to be a problem
         // we will take care then
+        #[cfg(feature = "esp32_40mhz")]
         let xtal_freq = XtalClock::RtcXtalFreq40M;
+        #[cfg(feature = "esp32_26mhz")]
+        let xtal_freq = XtalClock::RtcXtalFreq26M;
         let pll_freq = match cpu_clock_speed {
             CpuClock::Clock80MHz => PllClock::Pll320MHz,
             CpuClock::Clock160MHz => PllClock::Pll320MHz,
diff --git a/esp-hal-common/src/rtc_cntl/rtc/esp32.rs b/esp-hal-common/src/rtc_cntl/rtc/esp32.rs
index 5dc440b04dd..b9e157e15ce 100644
--- a/esp-hal-common/src/rtc_cntl/rtc/esp32.rs
+++ b/esp-hal-common/src/rtc_cntl/rtc/esp32.rs
@@ -9,10 +9,16 @@ use crate::{
 pub(crate) fn init() {}
 
 pub(crate) fn configure_clock() {
+    #[cfg(feature = "esp32_40mhz")]
     assert!(matches!(
         RtcClock::get_xtal_freq(),
         XtalClock::RtcXtalFreq40M
     ));
+    #[cfg(feature = "esp32_26mhz")]
+    assert!(
+        matches!(RtcClock::get_xtal_freq(), XtalClock::RtcXtalFreq26M),
+        "Did you flash the right bootloader configured for 26Mhz xtal?"
+    );
 
     RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m);
 
diff --git a/esp32-hal/Cargo.toml b/esp32-hal/Cargo.toml
index 8dd8cd091f0..8015fcc2d4e 100644
--- a/esp32-hal/Cargo.toml
+++ b/esp32-hal/Cargo.toml
@@ -45,7 +45,7 @@ static_cell       = "1.0.0"
 aes = "0.8.2"
 
 [features]
-default           = ["rt", "vectored"]
+default           = ["rt", "vectored", "xtal40mhz"]
 bluetooth         = []
 eh1               = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb"]
 rt                = []
@@ -55,6 +55,8 @@ vectored          = ["esp-hal-common/vectored"]
 async             = ["esp-hal-common/async", "embedded-hal-async"]
 embassy           = ["esp-hal-common/embassy"]
 embassy-time-timg0 = ["esp-hal-common/embassy-time-timg0", "embassy-time/tick-hz-1_000_000"]
+xtal40mhz         = ["esp-hal-common/esp32_40mhz"]
+xtal26mhz         = ["esp-hal-common/esp32_26mhz"]
 
 [[example]]
 name              = "hello_rgb"
diff --git a/esp32-hal/build.rs b/esp32-hal/build.rs
index 0606210b850..8f2078327eb 100644
--- a/esp32-hal/build.rs
+++ b/esp32-hal/build.rs
@@ -1,6 +1,7 @@
 use std::{env, fs::File, io::Write, path::PathBuf};
 
 fn main() {
+    check_features();
     // Put the linker script somewhere the linker can find it
     let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
     File::create(out.join("memory.x"))
@@ -68,3 +69,9 @@ fn generate_memory_extras() -> Vec<u8> {
     .as_bytes()
     .to_vec()
 }
+
+fn check_features() {
+    if cfg!(feature = "esp32_40mhz") && cfg!(feature = "esp32_26mhz") {
+        panic!("Only one xtal speed feature can be selected");
+    }
+}