diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
index 861be92aa54..77aab858e03 100644
--- a/esp-hal/CHANGELOG.md
+++ b/esp-hal/CHANGELOG.md
@@ -65,6 +65,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - `I2c` SCL timeout is now defined in bus clock cycles. (#2477)
 - Trying to send a single-shot RMT transmission will result in an error now, `RMT` deals with `u32` now, `PulseCode` is a convenience trait now (#2463)
 - Removed `get_` prefixes from functions (#2528)
+- The `Camera` and `I8080` drivers' constructors now only accepts blocking-mode DMA channels. (#2519)
 
 ### Fixed
 
diff --git a/esp-hal/MIGRATING-0.21.md b/esp-hal/MIGRATING-0.21.md
index 6211533dba6..c6cb5fa5f0e 100644
--- a/esp-hal/MIGRATING-0.21.md
+++ b/esp-hal/MIGRATING-0.21.md
@@ -276,7 +276,9 @@ For example:
  }
 ```
 
-## Circular DMA transfer's `available` returns `Result<usize, DmaError>` now
+## DMA related changes
+
+### Circular DMA transfer's `available` returns `Result<usize, DmaError>` now
 
 In case of any error you should drop the transfer and restart it.
 
@@ -293,6 +295,22 @@ In case of any error you should drop the transfer and restart it.
 +        };
 ```
 
+### Channel, ChannelRx and ChannelTx types have changed
+
+- `Channel`'s `Async`/`Blocking` mode has been moved before the channel instance parameter.
+- `ChannelRx` and `ChannelTx` have gained a new `Async`/`Blocking` mode parameter.
+
+```diff
+-Channel<'d, DmaChannel0, Async>
++Channel<'d, Async, DmaChannel0>
+
+-ChannelRx<'d, DmaChannel0>
++ChannelRx<'d, Async, DmaChannel0>
+
+-ChannelTx<'d, DmaChannel0>
++ChannelTx<'d, Async, DmaChannel0>
+```
+
 ## Removed `peripheral_input` and `into_peripheral_output` from GPIO pin types
 
 Creating peripheral interconnect signals now consume the GPIO pin used for the connection.
@@ -357,7 +375,9 @@ refer to the `Config` struct as `uart::Config`.
 +)
 ```
 
-## I8080 driver split `set_byte_order()` into `set_8bits_order()` and `set_byte_order()`.
+## LCD_CAM changes
+
+### I8080 driver split `set_byte_order()` into `set_8bits_order()` and `set_byte_order()`.
 
 If you were using an 8-bit bus.
 
@@ -371,6 +391,29 @@ If you were using an 16-bit bus, you don't need to change anything, `set_byte_or
 If you were sharing the bus between an 8-bit and 16-bit device, you will have to call the corresponding method when
 you switch between devices. Be sure to read the documentation of the new methods.
 
+### Mixed mode constructors
+
+It is no longer possible to construct `I8080` or `Camera` with an async-mode DMA channel.
+Convert the DMA channel into blocking before passing it to these constructors.
+
+```diff
+ let lcd_cam = LcdCam::new(peripherals.LCD_CAM);
+ let channel = ctx
+     .dma
+     .channel0
+-    .configure(false, DmaPriority::Priority0)
+-    .into_async();
++    .configure(false, DmaPriority::Priority0);
+
+ let i8080 = I8080::new(
+     lcd_cam.lcd,
+     channel.tx,
+     pins,
+     20.MHz(),
+     Config::default(),
+ );
+```
+
 ## `rmt::Channel::transmit` now returns `Result`, `PulseCode` is now `u32`
 
 When trying to send a one-shot transmission will fail if it doesn't end with an end-marker.
diff --git a/esp-hal/src/aes/mod.rs b/esp-hal/src/aes/mod.rs
index 07356137159..34a14f03ce9 100644
--- a/esp-hal/src/aes/mod.rs
+++ b/esp-hal/src/aes/mod.rs
@@ -276,21 +276,21 @@ pub mod dma {
         /// The underlying [`Aes`](super::Aes) driver
         pub aes: super::Aes<'d>,
 
-        channel: Channel<'d, <AES as DmaEligible>::Dma, Blocking>,
+        channel: Channel<'d, Blocking, <AES as DmaEligible>::Dma>,
         rx_chain: DescriptorChain,
         tx_chain: DescriptorChain,
     }
 
     impl<'d> crate::aes::Aes<'d> {
         /// Enable DMA for the current instance of the AES driver
-        pub fn with_dma<C>(
+        pub fn with_dma<CH>(
             self,
-            channel: Channel<'d, C, Blocking>,
+            channel: Channel<'d, Blocking, CH>,
             rx_descriptors: &'static mut [DmaDescriptor],
             tx_descriptors: &'static mut [DmaDescriptor],
         ) -> AesDma<'d>
         where
-            C: DmaChannelConvert<<AES as DmaEligible>::Dma>,
+            CH: DmaChannelConvert<<AES as DmaEligible>::Dma>,
         {
             AesDma {
                 aes: self,
@@ -324,7 +324,7 @@ pub mod dma {
     }
 
     impl<'d> DmaSupportTx for AesDma<'d> {
-        type TX = ChannelTx<'d, <AES as DmaEligible>::Dma, Blocking>;
+        type TX = ChannelTx<'d, Blocking, <AES as DmaEligible>::Dma>;
 
         fn tx(&mut self) -> &mut Self::TX {
             &mut self.channel.tx
@@ -336,7 +336,7 @@ pub mod dma {
     }
 
     impl<'d> DmaSupportRx for AesDma<'d> {
-        type RX = ChannelRx<'d, <AES as DmaEligible>::Dma, Blocking>;
+        type RX = ChannelRx<'d, Blocking, <AES as DmaEligible>::Dma>;
 
         fn rx(&mut self) -> &mut Self::RX {
             &mut self.channel.rx
diff --git a/esp-hal/src/dma/gdma.rs b/esp-hal/src/dma/gdma.rs
index 1fdb7534d13..21459966429 100644
--- a/esp-hal/src/dma/gdma.rs
+++ b/esp-hal/src/dma/gdma.rs
@@ -519,7 +519,7 @@ impl<C: GdmaChannel> InterruptAccess<DmaRxInterrupt> for ChannelRxImpl<C> {
 #[non_exhaustive]
 pub struct ChannelCreator<const N: u8> {}
 
-impl<CH: DmaChannel, M: Mode> Channel<'_, CH, M> {
+impl<CH: DmaChannel, M: Mode> Channel<'_, M, CH> {
     /// Asserts that the channel is compatible with the given peripheral.
     pub fn runtime_ensure_compatible<P: DmaEligible>(&self, _peripheral: &PeripheralRef<'_, P>) {
         // No runtime checks; GDMA channels are compatible with any peripheral
@@ -583,7 +583,7 @@ macro_rules! impl_channel {
                     self,
                     burst_mode: bool,
                     priority: DmaPriority,
-                ) -> Channel<'a, [<DmaChannel $num>], Blocking> {
+                ) -> Channel<'a, Blocking, [<DmaChannel $num>]> {
                     let mut this = Channel {
                         tx: ChannelTx::new(ChannelTxImpl(SpecificGdmaChannel::<$num> {})),
                         rx: ChannelRx::new(ChannelRxImpl(SpecificGdmaChannel::<$num> {})),
diff --git a/esp-hal/src/dma/m2m.rs b/esp-hal/src/dma/m2m.rs
index dc2d5a54815..0b2009950eb 100644
--- a/esp-hal/src/dma/m2m.rs
+++ b/esp-hal/src/dma/m2m.rs
@@ -32,7 +32,7 @@ pub struct Mem2Mem<'d, M>
 where
     M: Mode,
 {
-    channel: Channel<'d, AnyGdmaChannel, M>,
+    channel: Channel<'d, M, AnyGdmaChannel>,
     rx_chain: DescriptorChain,
     tx_chain: DescriptorChain,
     peripheral: DmaPeripheral,
@@ -41,7 +41,7 @@ where
 impl<'d> Mem2Mem<'d, Blocking> {
     /// Create a new Mem2Mem instance.
     pub fn new<CH, DM>(
-        channel: Channel<'d, CH, DM>,
+        channel: Channel<'d, DM, CH>,
         peripheral: impl DmaEligible,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
@@ -49,7 +49,7 @@ impl<'d> Mem2Mem<'d, Blocking> {
     where
         CH: DmaChannelConvert<AnyGdmaChannel>,
         DM: Mode,
-        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
+        Channel<'d, Blocking, CH>: From<Channel<'d, DM, CH>>,
     {
         unsafe {
             Self::new_unsafe(
@@ -64,7 +64,7 @@ impl<'d> Mem2Mem<'d, Blocking> {
 
     /// Create a new Mem2Mem instance with specific chunk size.
     pub fn new_with_chunk_size<CH, DM>(
-        channel: Channel<'d, CH, DM>,
+        channel: Channel<'d, DM, CH>,
         peripheral: impl DmaEligible,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
@@ -73,7 +73,7 @@ impl<'d> Mem2Mem<'d, Blocking> {
     where
         CH: DmaChannelConvert<AnyGdmaChannel>,
         DM: Mode,
-        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
+        Channel<'d, Blocking, CH>: From<Channel<'d, DM, CH>>,
     {
         unsafe {
             Self::new_unsafe(
@@ -93,7 +93,7 @@ impl<'d> Mem2Mem<'d, Blocking> {
     /// You must ensure that your not using DMA for the same peripheral and
     /// that your the only one using the DmaPeripheral.
     pub unsafe fn new_unsafe<CH, DM>(
-        channel: Channel<'d, CH, DM>,
+        channel: Channel<'d, DM, CH>,
         peripheral: DmaPeripheral,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
@@ -102,7 +102,7 @@ impl<'d> Mem2Mem<'d, Blocking> {
     where
         CH: DmaChannelConvert<AnyGdmaChannel>,
         DM: Mode,
-        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
+        Channel<'d, Blocking, CH>: From<Channel<'d, DM, CH>>,
     {
         if !(1..=4092).contains(&chunk_size) {
             return Err(DmaError::InvalidChunkSize);
@@ -111,7 +111,7 @@ impl<'d> Mem2Mem<'d, Blocking> {
             return Err(DmaError::OutOfDescriptors);
         }
         Ok(Mem2Mem {
-            channel: Channel::<_, Blocking>::from(channel).degrade(),
+            channel: Channel::<Blocking, _>::from(channel).degrade(),
             peripheral,
             rx_chain: DescriptorChain::new_with_chunk_size(rx_descriptors, chunk_size),
             tx_chain: DescriptorChain::new_with_chunk_size(tx_descriptors, chunk_size),
@@ -194,7 +194,7 @@ impl<'d, M> DmaSupportRx for Mem2Mem<'d, M>
 where
     M: Mode,
 {
-    type RX = ChannelRx<'d, AnyGdmaChannel, M>;
+    type RX = ChannelRx<'d, M, AnyGdmaChannel>;
 
     fn rx(&mut self) -> &mut Self::RX {
         &mut self.channel.rx
diff --git a/esp-hal/src/dma/mod.rs b/esp-hal/src/dma/mod.rs
index a49f53d83d9..2cda5bebda6 100644
--- a/esp-hal/src/dma/mod.rs
+++ b/esp-hal/src/dma/mod.rs
@@ -1660,17 +1660,16 @@ pub trait Rx: crate::private::Sealed {
 // DMA receive channel
 #[non_exhaustive]
 #[doc(hidden)]
-pub struct ChannelRx<'a, CH, M>
+pub struct ChannelRx<'a, M, CH>
 where
     CH: DmaChannel,
 {
     pub(crate) burst_mode: bool,
     pub(crate) rx_impl: CH::Rx,
-    pub(crate) mode: PhantomData<M>,
-    pub(crate) _phantom: PhantomData<(&'a (), CH)>,
+    pub(crate) _phantom: PhantomData<(&'a (), CH, M)>,
 }
 
-impl<'a, CH> ChannelRx<'a, CH, Blocking>
+impl<'a, CH> ChannelRx<'a, Blocking, CH>
 where
     CH: DmaChannel,
 {
@@ -1683,20 +1682,18 @@ where
         Self {
             burst_mode: false,
             rx_impl,
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
 
     /// Converts a blocking channel to an async channel.
-    pub(crate) fn into_async(mut self) -> ChannelRx<'a, CH, Async> {
+    pub(crate) fn into_async(mut self) -> ChannelRx<'a, Async, CH> {
         if let Some(handler) = self.rx_impl.async_handler() {
             self.set_interrupt_handler(handler);
         }
         ChannelRx {
             burst_mode: false,
             rx_impl: self.rx_impl,
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
@@ -1718,39 +1715,37 @@ where
     }
 }
 
-impl<'a, CH> ChannelRx<'a, CH, Async>
+impl<'a, CH> ChannelRx<'a, Async, CH>
 where
     CH: DmaChannel,
 {
     /// Converts an async channel into a blocking channel.
-    pub(crate) fn into_blocking(self) -> ChannelRx<'a, CH, Blocking> {
+    pub(crate) fn into_blocking(self) -> ChannelRx<'a, Blocking, CH> {
         if let Some(interrupt) = self.rx_impl.peripheral_interrupt() {
             crate::interrupt::disable(Cpu::current(), interrupt);
         }
         ChannelRx {
             burst_mode: false,
             rx_impl: self.rx_impl,
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
 }
 
-impl<'a, CH, M> ChannelRx<'a, CH, M>
+impl<'a, M, CH> ChannelRx<'a, M, CH>
 where
-    CH: DmaChannel,
     M: Mode,
+    CH: DmaChannel,
 {
     /// Return a less specific (degraded) version of this channel.
     #[doc(hidden)]
-    pub fn degrade<DEG: DmaChannel>(self) -> ChannelRx<'a, DEG, M>
+    pub fn degrade<DEG: DmaChannel>(self) -> ChannelRx<'a, M, DEG>
     where
         CH: DmaChannelConvert<DEG>,
     {
         ChannelRx {
             burst_mode: self.burst_mode,
             rx_impl: CH::degrade_rx(self.rx_impl),
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
@@ -1762,17 +1757,17 @@ where
     }
 }
 
-impl<CH, M> crate::private::Sealed for ChannelRx<'_, CH, M>
+impl<M, CH> crate::private::Sealed for ChannelRx<'_, M, CH>
 where
-    CH: DmaChannel,
     M: Mode,
+    CH: DmaChannel,
 {
 }
 
-impl<CH, M> Rx for ChannelRx<'_, CH, M>
+impl<M, CH> Rx for ChannelRx<'_, M, CH>
 where
-    CH: DmaChannel,
     M: Mode,
+    CH: DmaChannel,
 {
     unsafe fn prepare_transfer_without_start(
         &mut self,
@@ -1950,18 +1945,17 @@ pub trait Tx: crate::private::Sealed {
 
 /// DMA transmit channel
 #[doc(hidden)]
-pub struct ChannelTx<'a, CH, M>
+pub struct ChannelTx<'a, M, CH>
 where
     CH: DmaChannel,
 {
     #[allow(unused)]
     pub(crate) burst_mode: bool,
     pub(crate) tx_impl: CH::Tx,
-    pub(crate) mode: PhantomData<M>,
-    pub(crate) _phantom: PhantomData<(&'a (), CH)>,
+    pub(crate) _phantom: PhantomData<(&'a (), CH, M)>,
 }
 
-impl<'a, CH> ChannelTx<'a, CH, Blocking>
+impl<'a, CH> ChannelTx<'a, Blocking, CH>
 where
     CH: DmaChannel,
 {
@@ -1969,20 +1963,18 @@ where
         Self {
             burst_mode: false,
             tx_impl,
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
 
     /// Converts a blocking channel to an async channel.
-    pub(crate) fn into_async(mut self) -> ChannelTx<'a, CH, Async> {
+    pub(crate) fn into_async(mut self) -> ChannelTx<'a, Async, CH> {
         if let Some(handler) = self.tx_impl.async_handler() {
             self.set_interrupt_handler(handler);
         }
         ChannelTx {
             burst_mode: false,
             tx_impl: self.tx_impl,
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
@@ -2004,39 +1996,37 @@ where
     }
 }
 
-impl<'a, CH> ChannelTx<'a, CH, Async>
+impl<'a, CH> ChannelTx<'a, Async, CH>
 where
     CH: DmaChannel,
 {
     /// Converts an async channel into a blocking channel.
-    pub(crate) fn into_blocking(self) -> ChannelTx<'a, CH, Blocking> {
+    pub(crate) fn into_blocking(self) -> ChannelTx<'a, Blocking, CH> {
         if let Some(interrupt) = self.tx_impl.peripheral_interrupt() {
             crate::interrupt::disable(Cpu::current(), interrupt);
         }
         ChannelTx {
             burst_mode: false,
             tx_impl: self.tx_impl,
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
 }
 
-impl<'a, CH, M> ChannelTx<'a, CH, M>
+impl<'a, M, CH> ChannelTx<'a, M, CH>
 where
-    CH: DmaChannel,
     M: Mode,
+    CH: DmaChannel,
 {
     /// Return a less specific (degraded) version of this channel.
     #[doc(hidden)]
-    pub fn degrade<DEG: DmaChannel>(self) -> ChannelTx<'a, DEG, M>
+    pub fn degrade<DEG: DmaChannel>(self) -> ChannelTx<'a, M, DEG>
     where
         CH: DmaChannelConvert<DEG>,
     {
         ChannelTx {
             burst_mode: self.burst_mode,
             tx_impl: CH::degrade_tx(self.tx_impl),
-            mode: PhantomData,
             _phantom: PhantomData,
         }
     }
@@ -2048,17 +2038,17 @@ where
     }
 }
 
-impl<CH, M> crate::private::Sealed for ChannelTx<'_, CH, M>
+impl<M, CH> crate::private::Sealed for ChannelTx<'_, M, CH>
 where
-    CH: DmaChannel,
     M: Mode,
+    CH: DmaChannel,
 {
 }
 
-impl<CH, M> Tx for ChannelTx<'_, CH, M>
+impl<M, CH> Tx for ChannelTx<'_, M, CH>
 where
-    CH: DmaChannel,
     M: Mode,
+    CH: DmaChannel,
 {
     unsafe fn prepare_transfer_without_start(
         &mut self,
@@ -2272,27 +2262,27 @@ pub trait InterruptAccess<T: EnumSetType>: crate::private::Sealed {
 }
 
 /// DMA Channel
-pub struct Channel<'d, CH, M>
+pub struct Channel<'d, M, CH>
 where
-    CH: DmaChannel,
     M: Mode,
+    CH: DmaChannel,
 {
     /// RX half of the channel
-    pub rx: ChannelRx<'d, CH, M>,
+    pub rx: ChannelRx<'d, M, CH>,
     /// TX half of the channel
-    pub tx: ChannelTx<'d, CH, M>,
+    pub tx: ChannelTx<'d, M, CH>,
 }
 
-impl<'d, C> Channel<'d, C, Blocking>
+impl<'d, CH> Channel<'d, Blocking, CH>
 where
-    C: DmaChannel,
+    CH: DmaChannel,
 {
     /// Sets the interrupt handler for RX and TX interrupts.
     ///
     /// Interrupts are not enabled at the peripheral level here.
     pub fn set_interrupt_handler(&mut self, handler: InterruptHandler)
     where
-        C: DmaChannel,
+        CH: DmaChannel,
     {
         self.rx.set_interrupt_handler(handler);
         self.tx.set_interrupt_handler(handler);
@@ -2347,7 +2337,7 @@ where
     }
 
     /// Converts a blocking channel to an async channel.
-    pub fn into_async(self) -> Channel<'d, C, Async> {
+    pub fn into_async(self) -> Channel<'d, Async, CH> {
         Channel {
             rx: self.rx.into_async(),
             tx: self.tx.into_async(),
@@ -2355,12 +2345,12 @@ where
     }
 }
 
-impl<'d, C> Channel<'d, C, Async>
+impl<'d, CH> Channel<'d, Async, CH>
 where
-    C: DmaChannel,
+    CH: DmaChannel,
 {
     /// Converts an async channel to a blocking channel.
-    pub fn into_blocking(self) -> Channel<'d, C, Blocking> {
+    pub fn into_blocking(self) -> Channel<'d, Blocking, CH> {
         Channel {
             rx: self.rx.into_blocking(),
             tx: self.tx.into_blocking(),
@@ -2368,26 +2358,27 @@ where
     }
 }
 
-impl<'d, C: DmaChannel> From<Channel<'d, C, Blocking>> for Channel<'d, C, Async> {
-    fn from(channel: Channel<'d, C, Blocking>) -> Self {
+impl<'d, CH: DmaChannel> From<Channel<'d, Blocking, CH>> for Channel<'d, Async, CH> {
+    fn from(channel: Channel<'d, Blocking, CH>) -> Self {
         channel.into_async()
     }
 }
 
-impl<'d, C: DmaChannel> From<Channel<'d, C, Async>> for Channel<'d, C, Blocking> {
-    fn from(channel: Channel<'d, C, Async>) -> Self {
+impl<'d, CH: DmaChannel> From<Channel<'d, Async, CH>> for Channel<'d, Blocking, CH> {
+    fn from(channel: Channel<'d, Async, CH>) -> Self {
         channel.into_blocking()
     }
 }
 
-impl<'d, CH, M: Mode> Channel<'d, CH, M>
+impl<'d, M, CH> Channel<'d, M, CH>
 where
+    M: Mode,
     CH: DmaChannel,
 {
     /// Return a less specific (degraded) version of this channel (both rx and
     /// tx).
     #[doc(hidden)]
-    pub fn degrade<DEG: DmaChannel>(self) -> Channel<'d, DEG, M>
+    pub fn degrade<DEG: DmaChannel>(self) -> Channel<'d, M, DEG>
     where
         CH: DmaChannelConvert<DEG>,
     {
diff --git a/esp-hal/src/dma/pdma.rs b/esp-hal/src/dma/pdma.rs
index 35f8425d698..776ea57fd07 100644
--- a/esp-hal/src/dma/pdma.rs
+++ b/esp-hal/src/dma/pdma.rs
@@ -425,7 +425,7 @@ macro_rules! ImplSpiChannel {
                     self,
                     burst_mode: bool,
                     priority: DmaPriority,
-                ) -> Channel<'a, [<Spi $num DmaChannel>], Blocking> {
+                ) -> Channel<'a, Blocking, [<Spi $num DmaChannel>]> {
                     let mut this = Channel {
                         tx: ChannelTx::new(SpiDmaTxChannelImpl([<Spi $num DmaChannel>] {})),
                         rx: ChannelRx::new(SpiDmaRxChannelImpl([<Spi $num DmaChannel>] {})),
@@ -839,7 +839,7 @@ macro_rules! ImplI2sChannel {
                     self,
                     burst_mode: bool,
                     priority: DmaPriority,
-                ) -> Channel<'a, [<I2s $num DmaChannel>], Blocking> {
+                ) -> Channel<'a, Blocking, [<I2s $num DmaChannel>]> {
                     let mut this = Channel {
                         tx: ChannelTx::new(I2sDmaTxChannelImpl([<I2s $num DmaChannel>] {})),
                         rx: ChannelRx::new(I2sDmaRxChannelImpl([<I2s $num DmaChannel>] {})),
@@ -917,9 +917,10 @@ impl<'d> Dma<'d> {
     }
 }
 
-impl<'d, C, M: Mode> Channel<'d, C, M>
+impl<'d, CH, M> Channel<'d, M, CH>
 where
-    C: DmaChannel,
+    CH: DmaChannel,
+    M: Mode,
 {
     /// Asserts that the channel is compatible with the given peripheral.
     pub fn runtime_ensure_compatible(&self, peripheral: &PeripheralRef<'_, impl DmaEligible>) {
diff --git a/esp-hal/src/i2s/master.rs b/esp-hal/src/i2s/master.rs
index aad2f309191..111596ae9ff 100644
--- a/esp-hal/src/i2s/master.rs
+++ b/esp-hal/src/i2s/master.rs
@@ -272,7 +272,7 @@ where
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<'d, CH, DmaMode>,
+        channel: Channel<'d, DmaMode, CH>,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self
@@ -371,14 +371,14 @@ impl<'d> I2s<'d, Blocking> {
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<'d, CH, DM>,
+        channel: Channel<'d, DM, CH>,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self
     where
         CH: DmaChannelConvert<<AnyI2s as DmaEligible>::Dma>,
         DM: Mode,
-        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
+        Channel<'d, Blocking, CH>: From<Channel<'d, DM, CH>>,
     {
         Self::new_typed(
             i2s.map_into(),
@@ -404,14 +404,14 @@ where
         standard: Standard,
         data_format: DataFormat,
         sample_rate: impl Into<fugit::HertzU32>,
-        channel: Channel<'d, CH, DM>,
+        channel: Channel<'d, DM, CH>,
         rx_descriptors: &'static mut [DmaDescriptor],
         tx_descriptors: &'static mut [DmaDescriptor],
     ) -> Self
     where
         CH: DmaChannelConvert<T::Dma>,
         DM: Mode,
-        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
+        Channel<'d, Blocking, CH>: From<Channel<'d, DM, CH>>,
     {
         crate::into_ref!(i2s);
         Self::new_internal(
@@ -463,7 +463,7 @@ where
     T: RegisterAccess,
 {
     i2s: PeripheralRef<'d, T>,
-    tx_channel: ChannelTx<'d, T::Dma, DmaMode>,
+    tx_channel: ChannelTx<'d, DmaMode, T::Dma>,
     tx_chain: DescriptorChain,
 }
 
@@ -496,7 +496,7 @@ where
     T: RegisterAccess,
     DmaMode: Mode,
 {
-    type TX = ChannelTx<'d, T::Dma, DmaMode>;
+    type TX = ChannelTx<'d, DmaMode, T::Dma>;
 
     fn tx(&mut self) -> &mut Self::TX {
         &mut self.tx_channel
@@ -595,7 +595,7 @@ where
     DmaMode: Mode,
 {
     i2s: PeripheralRef<'d, T>,
-    rx_channel: ChannelRx<'d, T::Dma, DmaMode>,
+    rx_channel: ChannelRx<'d, DmaMode, T::Dma>,
     rx_chain: DescriptorChain,
 }
 
@@ -628,7 +628,7 @@ where
     T: RegisterAccess,
     DmaMode: Mode,
 {
-    type RX = ChannelRx<'d, T::Dma, DmaMode>;
+    type RX = ChannelRx<'d, DmaMode, T::Dma>;
 
     fn rx(&mut self) -> &mut Self::RX {
         &mut self.rx_channel
@@ -772,7 +772,7 @@ mod private {
         M: Mode,
     {
         pub i2s: PeripheralRef<'d, T>,
-        pub tx_channel: ChannelTx<'d, T::Dma, M>,
+        pub tx_channel: ChannelTx<'d, M, T::Dma>,
         pub descriptors: &'static mut [DmaDescriptor],
     }
 
@@ -829,7 +829,7 @@ mod private {
         M: Mode,
     {
         pub i2s: PeripheralRef<'d, T>,
-        pub rx_channel: ChannelRx<'d, T::Dma, M>,
+        pub rx_channel: ChannelRx<'d, M, T::Dma>,
         pub descriptors: &'static mut [DmaDescriptor],
     }
 
diff --git a/esp-hal/src/i2s/parallel.rs b/esp-hal/src/i2s/parallel.rs
index dce4ae1a3d1..c7b84e630ce 100644
--- a/esp-hal/src/i2s/parallel.rs
+++ b/esp-hal/src/i2s/parallel.rs
@@ -176,7 +176,7 @@ where
     I: Instance,
 {
     instance: PeripheralRef<'d, I>,
-    tx_channel: ChannelTx<'d, I::Dma, DM>,
+    tx_channel: ChannelTx<'d, DM, I::Dma>,
 }
 
 impl<'d, DM> I2sParallel<'d, DM>
@@ -186,7 +186,7 @@ where
     /// Create a new I2S Parallel Interface
     pub fn new<CH>(
         i2s: impl Peripheral<P = impl Instance> + 'd,
-        channel: Channel<'d, CH, DM>,
+        channel: Channel<'d, DM, CH>,
         frequency: impl Into<fugit::HertzU32>,
         pins: impl TxPins<'d>,
         clock_pin: impl Peripheral<P = impl PeripheralOutput> + 'd,
@@ -206,7 +206,7 @@ where
     /// Create a new I2S Parallel Interface
     pub fn new_typed<CH>(
         i2s: impl Peripheral<P = I> + 'd,
-        channel: Channel<'d, CH, DM>,
+        channel: Channel<'d, DM, CH>,
         frequency: impl Into<fugit::HertzU32>,
         mut pins: impl TxPins<'d>,
         clock_pin: impl Peripheral<P = impl PeripheralOutput> + 'd,
diff --git a/esp-hal/src/lcd_cam/cam.rs b/esp-hal/src/lcd_cam/cam.rs
index a16e2adc24c..358643e871e 100644
--- a/esp-hal/src/lcd_cam/cam.rs
+++ b/esp-hal/src/lcd_cam/cam.rs
@@ -126,14 +126,14 @@ pub struct Cam<'d> {
 /// Represents the camera interface with DMA support.
 pub struct Camera<'d> {
     lcd_cam: PeripheralRef<'d, LCD_CAM>,
-    rx_channel: ChannelRx<'d, <LCD_CAM as DmaEligible>::Dma, Blocking>,
+    rx_channel: ChannelRx<'d, Blocking, <LCD_CAM as DmaEligible>::Dma>,
 }
 
 impl<'d> Camera<'d> {
     /// Creates a new `Camera` instance with DMA support.
     pub fn new<P, CH>(
         cam: Cam<'d>,
-        channel: ChannelRx<'d, CH, Blocking>,
+        channel: ChannelRx<'d, Blocking, CH>,
         _pins: P,
         frequency: HertzU32,
     ) -> Self
diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs
index 9cbf41290ef..bfc7465a623 100644
--- a/esp-hal/src/lcd_cam/lcd/i8080.rs
+++ b/esp-hal/src/lcd_cam/lcd/i8080.rs
@@ -90,7 +90,7 @@ use crate::{
 /// Represents the I8080 LCD interface.
 pub struct I8080<'d, DM: Mode> {
     lcd_cam: PeripheralRef<'d, LCD_CAM>,
-    tx_channel: ChannelTx<'d, <LCD_CAM as DmaEligible>::Dma, Blocking>,
+    tx_channel: ChannelTx<'d, Blocking, <LCD_CAM as DmaEligible>::Dma>,
     _mode: PhantomData<DM>,
 }
 
@@ -101,7 +101,7 @@ where
     /// Creates a new instance of the I8080 LCD interface.
     pub fn new<P, CH>(
         lcd: Lcd<'d, DM>,
-        channel: ChannelTx<'d, CH, Blocking>,
+        channel: ChannelTx<'d, Blocking, CH>,
         mut pins: P,
         frequency: HertzU32,
         config: Config,
diff --git a/esp-hal/src/parl_io.rs b/esp-hal/src/parl_io.rs
index f1f2a8c35a9..1b81ca2901e 100644
--- a/esp-hal/src/parl_io.rs
+++ b/esp-hal/src/parl_io.rs
@@ -23,8 +23,6 @@
 //!
 //! [Parallel IO TX]: https://github.com/esp-rs/esp-hal/blob/main/examples/src/bin/parl_io_tx.rs
 
-use core::marker::PhantomData;
-
 use enumset::{EnumSet, EnumSetType};
 use fugit::HertzU32;
 use peripheral::PeripheralRef;
@@ -769,7 +767,6 @@ where
         Ok(ParlIoTx {
             tx_channel: self.tx_channel,
             tx_chain: DescriptorChain::new(self.descriptors),
-            phantom: PhantomData,
         })
     }
 }
@@ -801,7 +798,6 @@ where
         Ok(ParlIoTx {
             tx_channel: self.tx_channel,
             tx_chain: DescriptorChain::new(self.descriptors),
-            phantom: PhantomData,
         })
     }
 }
@@ -811,9 +807,8 @@ pub struct ParlIoTx<'d, DM>
 where
     DM: Mode,
 {
-    tx_channel: ChannelTx<'d, <PARL_IO as DmaEligible>::Dma, DM>,
+    tx_channel: ChannelTx<'d, DM, <PARL_IO as DmaEligible>::Dma>,
     tx_chain: DescriptorChain,
-    phantom: PhantomData<DM>,
 }
 
 impl<DM> core::fmt::Debug for ParlIoTx<'_, DM>
@@ -850,7 +845,6 @@ where
         Ok(ParlIoRx {
             rx_channel: self.rx_channel,
             rx_chain: DescriptorChain::new(self.descriptors),
-            phantom: PhantomData,
         })
     }
 }
@@ -880,7 +874,6 @@ where
         Ok(ParlIoRx {
             rx_channel: self.rx_channel,
             rx_chain: DescriptorChain::new(self.descriptors),
-            phantom: PhantomData,
         })
     }
 }
@@ -890,9 +883,8 @@ pub struct ParlIoRx<'d, DM>
 where
     DM: Mode,
 {
-    rx_channel: ChannelRx<'d, <PARL_IO as DmaEligible>::Dma, DM>,
+    rx_channel: ChannelRx<'d, DM, <PARL_IO as DmaEligible>::Dma>,
     rx_chain: DescriptorChain,
-    phantom: PhantomData<DM>,
 }
 
 impl<DM> core::fmt::Debug for ParlIoRx<'_, DM>
@@ -1005,7 +997,7 @@ impl<'d> ParlIoFullDuplex<'d, Blocking> {
     /// Create a new instance of [ParlIoFullDuplex]
     pub fn new<CH, DM>(
         _parl_io: impl Peripheral<P = peripherals::PARL_IO> + 'd,
-        dma_channel: Channel<'d, CH, DM>,
+        dma_channel: Channel<'d, DM, CH>,
         tx_descriptors: &'static mut [DmaDescriptor],
         rx_descriptors: &'static mut [DmaDescriptor],
         frequency: HertzU32,
@@ -1013,21 +1005,19 @@ impl<'d> ParlIoFullDuplex<'d, Blocking> {
     where
         DM: Mode,
         CH: DmaChannelConvert<<PARL_IO as DmaEligible>::Dma>,
-        Channel<'d, CH, Blocking>: From<Channel<'d, CH, DM>>,
+        Channel<'d, Blocking, CH>: From<Channel<'d, DM, CH>>,
     {
-        let dma_channel = Channel::<'d, CH, Blocking>::from(dma_channel);
+        let dma_channel = Channel::<Blocking, CH>::from(dma_channel);
         internal_init(frequency)?;
 
         Ok(Self {
             tx: TxCreatorFullDuplex {
                 tx_channel: dma_channel.tx.degrade(),
                 descriptors: tx_descriptors,
-                phantom: PhantomData,
             },
             rx: RxCreatorFullDuplex {
                 rx_channel: dma_channel.rx.degrade(),
                 descriptors: rx_descriptors,
-                phantom: PhantomData,
             },
         })
     }
@@ -1038,12 +1028,10 @@ impl<'d> ParlIoFullDuplex<'d, Blocking> {
             tx: TxCreatorFullDuplex {
                 tx_channel: self.tx.tx_channel.into_async(),
                 descriptors: self.tx.descriptors,
-                phantom: PhantomData,
             },
             rx: RxCreatorFullDuplex {
                 rx_channel: self.rx.rx_channel.into_async(),
                 descriptors: self.rx.descriptors,
-                phantom: PhantomData,
             },
         }
     }
@@ -1092,12 +1080,10 @@ impl<'d> ParlIoFullDuplex<'d, Async> {
             tx: TxCreatorFullDuplex {
                 tx_channel: self.tx.tx_channel.into_blocking(),
                 descriptors: self.tx.descriptors,
-                phantom: PhantomData,
             },
             rx: RxCreatorFullDuplex {
                 rx_channel: self.rx.rx_channel.into_blocking(),
                 descriptors: self.rx.descriptors,
-                phantom: PhantomData,
             },
         }
     }
@@ -1121,7 +1107,7 @@ where
     // TODO: only take a TX DMA channel?
     pub fn new<CH>(
         _parl_io: impl Peripheral<P = peripherals::PARL_IO> + 'd,
-        dma_channel: Channel<'d, CH, DM>,
+        dma_channel: Channel<'d, DM, CH>,
         descriptors: &'static mut [DmaDescriptor],
         frequency: HertzU32,
     ) -> Result<Self, Error>
@@ -1134,7 +1120,6 @@ where
             tx: TxCreator {
                 tx_channel: dma_channel.tx.degrade(),
                 descriptors,
-                phantom: PhantomData,
             },
         })
     }
@@ -1196,7 +1181,7 @@ where
     // TODO: only take a RX DMA channel?
     pub fn new<CH>(
         _parl_io: impl Peripheral<P = peripherals::PARL_IO> + 'd,
-        dma_channel: Channel<'d, CH, DM>,
+        dma_channel: Channel<'d, DM, CH>,
         descriptors: &'static mut [DmaDescriptor],
         frequency: HertzU32,
     ) -> Result<Self, Error>
@@ -1209,7 +1194,6 @@ where
             rx: RxCreator {
                 rx_channel: dma_channel.rx.degrade(),
                 descriptors,
-                phantom: PhantomData,
             },
         })
     }
@@ -1360,7 +1344,7 @@ impl<'d, DM> DmaSupportTx for ParlIoTx<'d, DM>
 where
     DM: Mode,
 {
-    type TX = ChannelTx<'d, <PARL_IO as DmaEligible>::Dma, DM>;
+    type TX = ChannelTx<'d, DM, <PARL_IO as DmaEligible>::Dma>;
 
     fn tx(&mut self) -> &mut Self::TX {
         &mut self.tx_channel
@@ -1402,7 +1386,7 @@ where
     }
 
     fn start_receive_bytes_dma(
-        rx_channel: &mut ChannelRx<'d, <PARL_IO as DmaEligible>::Dma, DM>,
+        rx_channel: &mut ChannelRx<'d, DM, <PARL_IO as DmaEligible>::Dma>,
         rx_chain: &mut DescriptorChain,
         ptr: *mut u8,
         len: usize,
@@ -1456,7 +1440,7 @@ impl<'d, DM> DmaSupportRx for ParlIoRx<'d, DM>
 where
     DM: Mode,
 {
-    type RX = ChannelRx<'d, <PARL_IO as DmaEligible>::Dma, DM>;
+    type RX = ChannelRx<'d, DM, <PARL_IO as DmaEligible>::Dma>;
 
     fn rx(&mut self) -> &mut Self::RX {
         &mut self.rx_channel
@@ -1472,9 +1456,8 @@ pub struct TxCreator<'d, DM>
 where
     DM: Mode,
 {
-    tx_channel: ChannelTx<'d, <PARL_IO as DmaEligible>::Dma, DM>,
+    tx_channel: ChannelTx<'d, DM, <PARL_IO as DmaEligible>::Dma>,
     descriptors: &'static mut [DmaDescriptor],
-    phantom: PhantomData<DM>,
 }
 
 /// Creates a RX channel
@@ -1482,9 +1465,8 @@ pub struct RxCreator<'d, DM>
 where
     DM: Mode,
 {
-    rx_channel: ChannelRx<'d, <PARL_IO as DmaEligible>::Dma, DM>,
+    rx_channel: ChannelRx<'d, DM, <PARL_IO as DmaEligible>::Dma>,
     descriptors: &'static mut [DmaDescriptor],
-    phantom: PhantomData<DM>,
 }
 
 /// Creates a TX channel
@@ -1492,9 +1474,8 @@ pub struct TxCreatorFullDuplex<'d, DM>
 where
     DM: Mode,
 {
-    tx_channel: ChannelTx<'d, <PARL_IO as DmaEligible>::Dma, DM>,
+    tx_channel: ChannelTx<'d, DM, <PARL_IO as DmaEligible>::Dma>,
     descriptors: &'static mut [DmaDescriptor],
-    phantom: PhantomData<DM>,
 }
 
 /// Creates a RX channel
@@ -1502,9 +1483,8 @@ pub struct RxCreatorFullDuplex<'d, DM>
 where
     DM: Mode,
 {
-    rx_channel: ChannelRx<'d, <PARL_IO as DmaEligible>::Dma, DM>,
+    rx_channel: ChannelRx<'d, DM, <PARL_IO as DmaEligible>::Dma>,
     descriptors: &'static mut [DmaDescriptor],
-    phantom: PhantomData<DM>,
 }
 
 #[doc(hidden)]
diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs
index ba2b5080a94..2bc93c5d61c 100644
--- a/esp-hal/src/spi/master.rs
+++ b/esp-hal/src/spi/master.rs
@@ -474,11 +474,11 @@ where
     /// This method prepares the SPI instance for DMA transfers using SPI
     /// and returns an instance of `SpiDma` that supports DMA
     /// operations.
-    pub fn with_dma<CH, DM>(self, channel: Channel<'d, CH, DM>) -> SpiDma<'d, M, T>
+    pub fn with_dma<CH, DM>(self, channel: Channel<'d, DM, CH>) -> SpiDma<'d, M, T>
     where
         CH: DmaChannelConvert<T::Dma>,
         DM: Mode,
-        Channel<'d, CH, M>: From<Channel<'d, CH, DM>>,
+        Channel<'d, M, CH>: From<Channel<'d, DM, CH>>,
     {
         SpiDma::new(self.spi, channel.into())
     }
@@ -880,7 +880,7 @@ mod dma {
         M: Mode,
     {
         pub(crate) spi: PeripheralRef<'d, T>,
-        pub(crate) channel: Channel<'d, T::Dma, M>,
+        pub(crate) channel: Channel<'d, M, T::Dma>,
         tx_transfer_in_progress: bool,
         rx_transfer_in_progress: bool,
         #[cfg(all(esp32, spi_address_workaround))]
@@ -990,7 +990,7 @@ mod dma {
         T: Instance,
         M: Mode,
     {
-        pub(super) fn new<CH>(spi: PeripheralRef<'d, T>, channel: Channel<'d, CH, M>) -> Self
+        pub(super) fn new<CH>(spi: PeripheralRef<'d, T>, channel: Channel<'d, M, CH>) -> Self
         where
             CH: DmaChannelConvert<T::Dma>,
         {
diff --git a/esp-hal/src/spi/slave.rs b/esp-hal/src/spi/slave.rs
index 93af03ae7e7..7e00288f48f 100644
--- a/esp-hal/src/spi/slave.rs
+++ b/esp-hal/src/spi/slave.rs
@@ -202,14 +202,14 @@ pub mod dma {
         #[cfg_attr(esp32, doc = "\n\n**Note**: ESP32 only supports Mode 1 and 3.")]
         pub fn with_dma<CH, DM>(
             self,
-            channel: Channel<'d, CH, DM>,
+            channel: Channel<'d, DM, CH>,
             rx_descriptors: &'static mut [DmaDescriptor],
             tx_descriptors: &'static mut [DmaDescriptor],
         ) -> SpiDma<'d, M, T>
         where
             CH: DmaChannelConvert<T::Dma>,
             DM: Mode,
-            Channel<'d, CH, M>: From<Channel<'d, CH, DM>>,
+            Channel<'d, M, CH>: From<Channel<'d, DM, CH>>,
         {
             self.spi.info().set_data_mode(self.data_mode, true);
             SpiDma::new(self.spi, channel.into(), rx_descriptors, tx_descriptors)
@@ -223,7 +223,7 @@ pub mod dma {
         M: Mode,
     {
         pub(crate) spi: PeripheralRef<'d, T>,
-        pub(crate) channel: Channel<'d, T::Dma, M>,
+        pub(crate) channel: Channel<'d, M, T::Dma>,
         rx_chain: DescriptorChain,
         tx_chain: DescriptorChain,
     }
@@ -262,7 +262,7 @@ pub mod dma {
         T: InstanceDma,
         DmaMode: Mode,
     {
-        type TX = ChannelTx<'d, T::Dma, DmaMode>;
+        type TX = ChannelTx<'d, DmaMode, T::Dma>;
 
         fn tx(&mut self) -> &mut Self::TX {
             &mut self.channel.tx
@@ -278,7 +278,7 @@ pub mod dma {
         T: InstanceDma,
         DmaMode: Mode,
     {
-        type RX = ChannelRx<'d, T::Dma, DmaMode>;
+        type RX = ChannelRx<'d, DmaMode, T::Dma>;
 
         fn rx(&mut self) -> &mut Self::RX {
             &mut self.channel.rx
@@ -296,7 +296,7 @@ pub mod dma {
     {
         fn new<CH>(
             spi: PeripheralRef<'d, T>,
-            channel: Channel<'d, CH, DmaMode>,
+            channel: Channel<'d, DmaMode, CH>,
             rx_descriptors: &'static mut [DmaDescriptor],
             tx_descriptors: &'static mut [DmaDescriptor],
         ) -> Self
diff --git a/hil-test/tests/dma_mem2mem.rs b/hil-test/tests/dma_mem2mem.rs
index f65873ae6c5..d9a3a362be3 100644
--- a/hil-test/tests/dma_mem2mem.rs
+++ b/hil-test/tests/dma_mem2mem.rs
@@ -25,7 +25,7 @@ cfg_if::cfg_if! {
 }
 
 struct Context {
-    channel: Channel<'static, AnyGdmaChannel, Blocking>,
+    channel: Channel<'static, Blocking, AnyGdmaChannel>,
     dma_peripheral: DmaPeripheralType,
 }
 
diff --git a/hil-test/tests/qspi.rs b/hil-test/tests/qspi.rs
index c2f69b9ebdf..43b500d9a7a 100644
--- a/hil-test/tests/qspi.rs
+++ b/hil-test/tests/qspi.rs
@@ -43,7 +43,7 @@ struct Context {
     spi: Spi<'static, Blocking>,
     #[cfg(pcnt)]
     pcnt: esp_hal::peripherals::PCNT,
-    dma_channel: Channel<'static, DmaChannel0, Blocking>,
+    dma_channel: Channel<'static, Blocking, DmaChannel0>,
     gpios: [AnyPin; 3],
 }