diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
index 0cbba9c1a123f..70bc12a987d8f 100644
--- a/compiler/rustc_target/src/spec/mod.rs
+++ b/compiler/rustc_target/src/spec/mod.rs
@@ -988,9 +988,12 @@ supported_targets! {
     ("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
 
     ("xtensa-esp32-none-elf", xtensa_esp32_none_elf),
+    ("xtensa-esp32-espidf", xtensa_esp32_espidf),
     ("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf),
+    ("xtensa-esp32s2-espidf", xtensa_esp32s2_espidf),
     ("xtensa-esp8266-none-elf", xtensa_esp8266_none_elf),
     ("xtensa-esp32s3-none-elf", xtensa_esp32s3_none_elf),
+    ("xtensa-esp32s3-espidf", xtensa_esp32s3_espidf),
 
     ("i686-wrs-vxworks", i686_wrs_vxworks),
     ("x86_64-wrs-vxworks", x86_64_wrs_vxworks),
diff --git a/compiler/rustc_target/src/spec/xtensa_esp32_espidf.rs b/compiler/rustc_target/src/spec/xtensa_esp32_espidf.rs
new file mode 100644
index 0000000000000..e4301019b926b
--- /dev/null
+++ b/compiler/rustc_target/src/spec/xtensa_esp32_espidf.rs
@@ -0,0 +1,32 @@
+use crate::spec::{LinkerFlavor, Target, TargetOptions};
+use crate::abi::Endian;
+
+pub fn target() -> Target {
+    Target {
+        llvm_target: "xtensa-none-elf".to_string(),
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32".to_string(),
+        arch: "xtensa".to_string(),
+
+        options: TargetOptions {
+            endian: Endian::Little,
+            c_int_width: "32".to_string(),
+            families: vec!["unix".to_string()],
+            os: "espidf".to_string(),
+            env: "newlib".to_string(),
+            vendor: "espressif".to_string(),
+            linker_flavor: LinkerFlavor::Gcc,
+
+            executables: true,
+            cpu: "esp32".to_string(),
+            linker: Some("xtensa-esp32-elf-gcc".to_string()),
+
+            // The esp32 only supports native 32bit atomics. However, esp-idf will emulate 64bit atomics 
+            // so we claim a max atomic width of 64 here.
+            max_atomic_width: Some(64),
+            atomic_cas: true,
+
+            ..super::xtensa_base::opts()
+        },
+    }
+}
\ No newline at end of file
diff --git a/compiler/rustc_target/src/spec/xtensa_esp32s2_espidf.rs b/compiler/rustc_target/src/spec/xtensa_esp32s2_espidf.rs
new file mode 100644
index 0000000000000..16ce80b9da4ed
--- /dev/null
+++ b/compiler/rustc_target/src/spec/xtensa_esp32s2_espidf.rs
@@ -0,0 +1,40 @@
+use crate::spec::{LinkerFlavor, Target, TargetOptions};
+use crate::abi::Endian;
+
+pub fn target() -> Target {
+    Target {
+        llvm_target: "xtensa-none-elf".to_string(),
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32".to_string(),
+        arch: "xtensa".to_string(),
+
+        options: TargetOptions {
+            endian: Endian::Little,
+            c_int_width: "32".to_string(),
+            families: vec!["unix".to_string()],
+            os: "espidf".to_string(),
+            env: "newlib".to_string(),
+            vendor: "espressif".to_string(),
+            linker_flavor: LinkerFlavor::Gcc,
+
+            executables: true,
+            cpu: "esp32-s2".to_string(),
+            linker: Some("xtensa-esp32s2-elf-gcc".to_string()),
+
+            // See https://github.com/espressif/rust-esp32-example/issues/3#issuecomment-861054477
+            //
+            // Unlike the original ESP32 chip, ESP32-S2 does not really support atomics.
+            // If the missing hardware instruction ends up being emulated in ESP-IDF, we might want to revert
+            // this change and claim that atomics are supported "in hardware" (even though they would be emulated
+            // by actually trapping the illegal instruction exception handler and calling into an ESP-IDF C emulation code).
+            //
+            // However, for now we simultaneously claim "max_atomic_width: Some(64)" **and** atomic_cas: true,
+            // which should force the compiler to generate libcalls to functions that emulate atomics
+            // and which are already implemented in the ESP-IDF main branch anyway.
+            max_atomic_width: Some(64),
+            atomic_cas: true,
+
+            ..super::xtensa_base::opts()
+        },
+    }
+}
\ No newline at end of file
diff --git a/compiler/rustc_target/src/spec/xtensa_esp32s3_espidf.rs b/compiler/rustc_target/src/spec/xtensa_esp32s3_espidf.rs
new file mode 100644
index 0000000000000..fc75e09f21fbe
--- /dev/null
+++ b/compiler/rustc_target/src/spec/xtensa_esp32s3_espidf.rs
@@ -0,0 +1,32 @@
+use crate::spec::{LinkerFlavor, Target, TargetOptions};
+use crate::abi::Endian;
+
+pub fn target() -> Target {
+    Target {
+        llvm_target: "xtensa-none-elf".to_string(),
+        pointer_width: 32,
+        data_layout: "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32".to_string(),
+        arch: "xtensa".to_string(),
+
+        options: TargetOptions {
+            endian: Endian::Little,
+            c_int_width: "32".to_string(),
+            families: vec!["unix".to_string()],
+            os: "espidf".to_string(),
+            env: "newlib".to_string(),
+            vendor: "espressif".to_string(),
+            linker_flavor: LinkerFlavor::Gcc,
+
+            executables: true,
+            cpu: "esp32-s3".to_string(),
+            linker: Some("xtensa-esp32s3-elf-gcc".to_string()),
+
+            // The esp32s3 only supports native 32bit atomics. However, esp-idf will emulate 64bit atomics 
+            // so we claim a max atomic width of 64 here.
+            max_atomic_width: Some(64),
+            atomic_cas: true,
+
+            ..super::xtensa_base::opts()
+        },
+    }
+}
\ No newline at end of file